1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #include "X86TargetMachine.h"
16 #include "X86Relocations.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/CodeGen/MachineCodeEmitter.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Function.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Target/TargetOptions.h"
31 NumEmitted("x86-emitter", "Number of machine instructions emitted");
35 class Emitter : public MachineFunctionPass {
36 const X86InstrInfo *II;
37 MachineCodeEmitter &MCE;
38 std::vector<std::pair<MachineBasicBlock *, unsigned> > BBRefs;
40 explicit Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {}
41 Emitter(MachineCodeEmitter &mce, const X86InstrInfo& ii)
42 : II(&ii), MCE(mce) {}
44 bool runOnMachineFunction(MachineFunction &MF);
46 virtual const char *getPassName() const {
47 return "X86 Machine Code Emitter";
50 void emitInstruction(const MachineInstr &MI);
53 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
54 void emitPCRelativeValue(unsigned Address);
55 void emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall);
56 void emitGlobalAddressForPtr(GlobalValue *GV, int Disp = 0);
57 void emitExternalSymbolAddress(const char *ES, bool isPCRelative,
60 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
61 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
62 void emitConstant(unsigned Val, unsigned Size);
64 void emitMemModRMByte(const MachineInstr &MI,
65 unsigned Op, unsigned RegOpcodeField);
70 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
71 /// to the specified MCE object.
72 FunctionPass *llvm::createX86CodeEmitterPass(MachineCodeEmitter &MCE) {
73 return new Emitter(MCE);
76 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
77 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
78 MF.getTarget().getRelocationModel() != Reloc::Static) &&
79 "JIT relocation model must be set to static or default!");
80 II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
85 MCE.startFunction(MF);
86 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
88 MCE.StartMachineBasicBlock(MBB);
89 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
93 } while (MCE.finishFunction(MF));
95 // Resolve all forward branches now.
96 for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
97 unsigned Location = MCE.getMachineBasicBlockAddress(BBRefs[i].first);
98 unsigned Ref = BBRefs[i].second;
99 *((unsigned*)(intptr_t)Ref) = Location-Ref-4;
105 /// emitPCRelativeValue - Emit a 32-bit PC relative address.
107 void Emitter::emitPCRelativeValue(unsigned Address) {
108 MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
111 /// emitPCRelativeBlockAddress - This method keeps track of the information
112 /// necessary to resolve the address of this block later and emits a dummy
115 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
116 // Remember where this reference was and where it is to so we can
117 // deal with it later.
118 BBRefs.push_back(std::make_pair(MBB, MCE.getCurrentPCValue()));
122 /// emitGlobalAddressForCall - Emit the specified address to the code stream
123 /// assuming this is part of a function call, which is PC relative.
125 void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall) {
126 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
127 X86::reloc_pcrel_word, GV, 0,
128 !isTailCall /*Doesn'tNeedStub*/));
132 /// emitGlobalAddress - Emit the specified address to the code stream assuming
133 /// this is part of a "take the address of a global" instruction, which is not
136 void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, int Disp /* = 0 */) {
137 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
138 X86::reloc_absolute_word, GV));
139 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
142 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
143 /// be emitted to the current location in the function, and allow it to be PC
145 void Emitter::emitExternalSymbolAddress(const char *ES, bool isPCRelative,
147 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
148 isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES));
152 /// N86 namespace - Native X86 Register numbers... used by X86 backend.
156 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
161 // getX86RegNum - This function maps LLVM register identifiers to their X86
162 // specific numbering, which is used in various places encoding instructions.
164 static unsigned getX86RegNum(unsigned RegNo) {
166 case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
167 case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
168 case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
169 case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
170 case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
171 case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
172 case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
173 case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
175 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
176 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
177 return RegNo-X86::ST0;
179 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
180 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
181 return RegNo-X86::XMM0;
184 assert(MRegisterInfo::isVirtualRegister(RegNo) &&
185 "Unknown physical register!");
186 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
191 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
193 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
194 return RM | (RegOpcode << 3) | (Mod << 6);
197 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
198 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
201 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
202 // SIB byte is in the same format as the ModRMByte...
203 MCE.emitByte(ModRMByte(SS, Index, Base));
206 void Emitter::emitConstant(unsigned Val, unsigned Size) {
207 // Output the constant in little endian byte order...
208 for (unsigned i = 0; i != Size; ++i) {
209 MCE.emitByte(Val & 255);
214 static bool isDisp8(int Value) {
215 return Value == (signed char)Value;
218 void Emitter::emitMemModRMByte(const MachineInstr &MI,
219 unsigned Op, unsigned RegOpcodeField) {
220 const MachineOperand &Op3 = MI.getOperand(Op+3);
224 if (Op3.isGlobalAddress()) {
225 GV = Op3.getGlobal();
226 DispVal = Op3.getOffset();
227 } else if (Op3.isConstantPoolIndex()) {
228 DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
229 DispVal += Op3.getOffset();
230 } else if (Op3.isJumpTableIndex()) {
231 DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
233 DispVal = Op3.getImmedValue();
236 const MachineOperand &Base = MI.getOperand(Op);
237 const MachineOperand &Scale = MI.getOperand(Op+1);
238 const MachineOperand &IndexReg = MI.getOperand(Op+2);
240 unsigned BaseReg = Base.getReg();
242 // Is a SIB byte needed?
243 if (IndexReg.getReg() == 0 && BaseReg != X86::ESP) {
244 if (BaseReg == 0) { // Just a displacement?
245 // Emit special case [disp32] encoding
246 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
248 emitGlobalAddressForPtr(GV, DispVal);
250 emitConstant(DispVal, 4);
252 unsigned BaseRegNo = getX86RegNum(BaseReg);
254 // Emit the most general non-SIB encoding: [REG+disp32]
255 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
256 emitGlobalAddressForPtr(GV, DispVal);
257 } else if (DispVal == 0 && BaseRegNo != N86::EBP) {
258 // Emit simple indirect register encoding... [EAX] f.e.
259 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
260 } else if (isDisp8(DispVal)) {
261 // Emit the disp8 encoding... [REG+disp8]
262 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
263 emitConstant(DispVal, 1);
265 // Emit the most general non-SIB encoding: [REG+disp32]
266 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
267 emitConstant(DispVal, 4);
271 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
272 assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
274 bool ForceDisp32 = false;
275 bool ForceDisp8 = false;
277 // If there is no base register, we emit the special case SIB byte with
278 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
279 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
282 // Emit the normal disp32 encoding...
283 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
285 } else if (DispVal == 0 && BaseReg != X86::EBP) {
286 // Emit no displacement ModR/M byte
287 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
288 } else if (isDisp8(DispVal)) {
289 // Emit the disp8 encoding...
290 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
291 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
293 // Emit the normal disp32 encoding...
294 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
297 // Calculate what the SS field value should be...
298 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
299 unsigned SS = SSTable[Scale.getImmedValue()];
302 // Handle the SIB byte for the case where there is no base. The
303 // displacement has already been output.
304 assert(IndexReg.getReg() && "Index register must be specified!");
305 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
307 unsigned BaseRegNo = getX86RegNum(BaseReg);
309 if (IndexReg.getReg())
310 IndexRegNo = getX86RegNum(IndexReg.getReg());
312 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
313 emitSIBByte(SS, IndexRegNo, BaseRegNo);
316 // Do we need to output a displacement?
317 if (DispVal != 0 || ForceDisp32 || ForceDisp8) {
318 if (!ForceDisp32 && isDisp8(DispVal))
319 emitConstant(DispVal, 1);
321 emitGlobalAddressForPtr(GV, DispVal);
323 emitConstant(DispVal, 4);
328 static unsigned sizeOfImm(const TargetInstrDescriptor &Desc) {
329 switch (Desc.TSFlags & X86II::ImmMask) {
330 case X86II::Imm8: return 1;
331 case X86II::Imm16: return 2;
332 case X86II::Imm32: return 4;
333 default: assert(0 && "Immediate size not set!");
338 void Emitter::emitInstruction(const MachineInstr &MI) {
339 NumEmitted++; // Keep track of the # of mi's emitted
341 unsigned Opcode = MI.getOpcode();
342 const TargetInstrDescriptor &Desc = II->get(Opcode);
344 // Emit the repeat opcode prefix as needed.
345 if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
347 // Emit the operand size opcode prefix as needed.
348 if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);
350 switch (Desc.TSFlags & X86II::Op0Mask) {
352 MCE.emitByte(0x0F); // Two-byte opcode prefix
354 case X86II::REP: break; // already handled.
355 case X86II::XS: // F3 0F
359 case X86II::XD: // F2 0F
363 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
364 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
366 (((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
367 >> X86II::Op0Shift));
368 break; // Two-byte opcode prefix
369 default: assert(0 && "Invalid prefix!");
370 case 0: break; // No prefix!
373 unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
374 switch (Desc.TSFlags & X86II::FormMask) {
375 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
380 assert(0 && "psuedo instructions should be removed before code emission");
381 case X86::IMPLICIT_USE:
382 case X86::IMPLICIT_DEF:
383 case X86::IMPLICIT_DEF_R8:
384 case X86::IMPLICIT_DEF_R16:
385 case X86::IMPLICIT_DEF_R32:
386 case X86::IMPLICIT_DEF_FR32:
387 case X86::IMPLICIT_DEF_FR64:
388 case X86::IMPLICIT_DEF_VR64:
389 case X86::IMPLICIT_DEF_VR128:
390 case X86::FP_REG_KILL:
397 MCE.emitByte(BaseOpcode);
398 if (MI.getNumOperands() == 1) {
399 const MachineOperand &MO = MI.getOperand(0);
400 if (MO.isMachineBasicBlock()) {
401 emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
402 } else if (MO.isGlobalAddress()) {
403 bool isTailCall = Opcode == X86::TAILJMPd ||
404 Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
405 emitGlobalAddressForCall(MO.getGlobal(), isTailCall);
406 } else if (MO.isExternalSymbol()) {
407 bool isTailCall = Opcode == X86::TAILJMPd ||
408 Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
409 emitExternalSymbolAddress(MO.getSymbolName(), true, isTailCall);
410 } else if (MO.isImmediate()) {
411 emitConstant(MO.getImmedValue(), sizeOfImm(Desc));
413 assert(0 && "Unknown RawFrm operand!");
418 case X86II::AddRegFrm:
419 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
420 if (MI.getNumOperands() == 2) {
421 const MachineOperand &MO1 = MI.getOperand(1);
422 if (Value *V = MO1.getVRegValueOrNull()) {
423 assert(sizeOfImm(Desc) == 4 &&
424 "Don't know how to emit non-pointer values!");
425 emitGlobalAddressForPtr(cast<GlobalValue>(V));
426 } else if (MO1.isGlobalAddress()) {
427 assert(sizeOfImm(Desc) == 4 &&
428 "Don't know how to emit non-pointer values!");
429 assert(!MO1.isPCRelative() && "Function pointer ref is PC relative?");
430 emitGlobalAddressForPtr(MO1.getGlobal(), MO1.getOffset());
431 } else if (MO1.isExternalSymbol()) {
432 assert(sizeOfImm(Desc) == 4 &&
433 "Don't know how to emit non-pointer values!");
434 emitExternalSymbolAddress(MO1.getSymbolName(), false, false);
435 } else if (MO1.isJumpTableIndex()) {
436 assert(sizeOfImm(Desc) == 4 &&
437 "Don't know how to emit non-pointer values!");
438 emitConstant(MCE.getJumpTableEntryAddress(MO1.getJumpTableIndex()), 4);
440 emitConstant(MO1.getImmedValue(), sizeOfImm(Desc));
445 case X86II::MRMDestReg: {
446 MCE.emitByte(BaseOpcode);
447 emitRegModRMByte(MI.getOperand(0).getReg(),
448 getX86RegNum(MI.getOperand(1).getReg()));
449 if (MI.getNumOperands() == 3)
450 emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
453 case X86II::MRMDestMem:
454 MCE.emitByte(BaseOpcode);
455 emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
456 if (MI.getNumOperands() == 6)
457 emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
460 case X86II::MRMSrcReg:
461 MCE.emitByte(BaseOpcode);
462 emitRegModRMByte(MI.getOperand(1).getReg(),
463 getX86RegNum(MI.getOperand(0).getReg()));
464 if (MI.getNumOperands() == 3)
465 emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
468 case X86II::MRMSrcMem:
469 MCE.emitByte(BaseOpcode);
470 emitMemModRMByte(MI, 1, getX86RegNum(MI.getOperand(0).getReg()));
471 if (MI.getNumOperands() == 2+4)
472 emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
475 case X86II::MRM0r: case X86II::MRM1r:
476 case X86II::MRM2r: case X86II::MRM3r:
477 case X86II::MRM4r: case X86II::MRM5r:
478 case X86II::MRM6r: case X86II::MRM7r:
479 MCE.emitByte(BaseOpcode);
480 emitRegModRMByte(MI.getOperand(0).getReg(),
481 (Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
483 if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
484 emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(),
489 case X86II::MRM0m: case X86II::MRM1m:
490 case X86II::MRM2m: case X86II::MRM3m:
491 case X86II::MRM4m: case X86II::MRM5m:
492 case X86II::MRM6m: case X86II::MRM7m:
493 MCE.emitByte(BaseOpcode);
494 emitMemModRMByte(MI, 0, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m);
496 if (MI.getNumOperands() == 5) {
497 if (MI.getOperand(4).isImmediate())
498 emitConstant(MI.getOperand(4).getImmedValue(), sizeOfImm(Desc));
499 else if (MI.getOperand(4).isGlobalAddress())
500 emitGlobalAddressForPtr(MI.getOperand(4).getGlobal(),
501 MI.getOperand(4).getOffset());
502 else if (MI.getOperand(4).isJumpTableIndex())
503 emitConstant(MCE.getJumpTableEntryAddress(MI.getOperand(4)
504 .getJumpTableIndex()), 4);
506 assert(0 && "Unknown operand!");
510 case X86II::MRMInitReg:
511 MCE.emitByte(BaseOpcode);
512 emitRegModRMByte(MI.getOperand(0).getReg(),
513 getX86RegNum(MI.getOperand(0).getReg()));