1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/Function.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Target/TargetOptions.h"
34 STATISTIC(NumEmitted, "Number of machine instructions emitted");
37 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
38 const X86InstrInfo *II;
41 MachineCodeEmitter &MCE;
42 intptr_t PICBaseOffset;
47 explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
48 : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
49 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
50 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
51 Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
52 const X86InstrInfo &ii, const TargetData &td, bool is64)
53 : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
54 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
55 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
57 bool runOnMachineFunction(MachineFunction &MF);
59 virtual const char *getPassName() const {
60 return "X86 Machine Code Emitter";
63 void emitInstruction(const MachineInstr &MI,
64 const TargetInstrDesc *Desc);
66 void getAnalysisUsage(AnalysisUsage &AU) const {
67 AU.addRequired<MachineModuleInfo>();
68 MachineFunctionPass::getAnalysisUsage(AU);
72 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
73 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
74 int Disp = 0, intptr_t PCAdj = 0,
75 bool NeedStub = false, bool IsLazy = false);
76 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
77 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
79 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
82 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
85 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
86 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
87 void emitConstant(uint64_t Val, unsigned Size);
89 void emitMemModRMByte(const MachineInstr &MI,
90 unsigned Op, unsigned RegOpcodeField,
93 unsigned getX86RegNum(unsigned RegNo) const;
94 bool isX86_64ExtendedReg(const MachineOperand &MO);
95 unsigned determineREX(const MachineInstr &MI);
97 bool gvNeedsLazyPtr(const GlobalValue *GV);
102 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
103 /// to the specified MCE object.
104 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
105 MachineCodeEmitter &MCE) {
106 return new Emitter(TM, MCE);
109 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
110 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
111 MF.getTarget().getRelocationModel() != Reloc::Static) &&
112 "JIT relocation model must be set to static or default!");
114 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
116 II = ((X86TargetMachine&)TM).getInstrInfo();
117 TD = ((X86TargetMachine&)TM).getTargetData();
118 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
121 MCE.startFunction(MF);
122 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
124 MCE.StartMachineBasicBlock(MBB);
125 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
127 const TargetInstrDesc &Desc = I->getDesc();
128 emitInstruction(*I, &Desc);
129 // MOVPC32r is basically a call plus a pop instruction.
130 if (Desc.getOpcode() == X86::MOVPC32r)
131 emitInstruction(*I, &II->get(X86::POP32r));
132 NumEmitted++; // Keep track of the # of mi's emitted
135 } while (MCE.finishFunction(MF));
140 /// emitPCRelativeBlockAddress - This method keeps track of the information
141 /// necessary to resolve the address of this block later and emits a dummy
144 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
145 // Remember where this reference was and where it is to so we can
146 // deal with it later.
147 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
148 X86::reloc_pcrel_word, MBB));
152 /// emitGlobalAddress - Emit the specified address to the code stream assuming
153 /// this is part of a "take the address of a global" instruction.
155 void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
156 int Disp /* = 0 */, intptr_t PCAdj /* = 0 */,
157 bool NeedStub /* = false */,
158 bool isLazy /* = false */) {
159 intptr_t RelocCST = 0;
160 if (Reloc == X86::reloc_picrel_word)
161 RelocCST = PICBaseOffset;
162 else if (Reloc == X86::reloc_pcrel_word)
164 MachineRelocation MR = isLazy
165 ? MachineRelocation::getGVLazyPtr(MCE.getCurrentPCOffset(), Reloc,
166 GV, RelocCST, NeedStub)
167 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
168 GV, RelocCST, NeedStub);
169 MCE.addRelocation(MR);
170 if (Reloc == X86::reloc_absolute_dword)
172 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
175 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
176 /// be emitted to the current location in the function, and allow it to be PC
178 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
179 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
180 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
181 Reloc, ES, RelocCST));
182 if (Reloc == X86::reloc_absolute_dword)
187 /// emitConstPoolAddress - Arrange for the address of an constant pool
188 /// to be emitted to the current location in the function, and allow it to be PC
190 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
192 intptr_t PCAdj /* = 0 */) {
193 intptr_t RelocCST = 0;
194 if (Reloc == X86::reloc_picrel_word)
195 RelocCST = PICBaseOffset;
196 else if (Reloc == X86::reloc_pcrel_word)
198 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
199 Reloc, CPI, RelocCST));
200 if (Reloc == X86::reloc_absolute_dword)
202 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
205 /// emitJumpTableAddress - Arrange for the address of a jump table to
206 /// be emitted to the current location in the function, and allow it to be PC
208 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
209 intptr_t PCAdj /* = 0 */) {
210 intptr_t RelocCST = 0;
211 if (Reloc == X86::reloc_picrel_word)
212 RelocCST = PICBaseOffset;
213 else if (Reloc == X86::reloc_pcrel_word)
215 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
216 Reloc, JTI, RelocCST));
217 if (Reloc == X86::reloc_absolute_dword)
219 MCE.emitWordLE(0); // The relocated value will be added to the displacement
222 unsigned Emitter::getX86RegNum(unsigned RegNo) const {
223 return ((const X86RegisterInfo&)II->getRegisterInfo()).getX86RegNum(RegNo);
226 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
228 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
229 return RM | (RegOpcode << 3) | (Mod << 6);
232 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
233 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
236 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
237 // SIB byte is in the same format as the ModRMByte...
238 MCE.emitByte(ModRMByte(SS, Index, Base));
241 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
242 // Output the constant in little endian byte order...
243 for (unsigned i = 0; i != Size; ++i) {
244 MCE.emitByte(Val & 255);
249 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
250 /// sign-extended field.
251 static bool isDisp8(int Value) {
252 return Value == (signed char)Value;
255 bool Emitter::gvNeedsLazyPtr(const GlobalValue *GV) {
256 return !Is64BitMode &&
257 TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
260 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
261 int DispVal, intptr_t PCAdj) {
262 // If this is a simple integer displacement that doesn't require a relocation,
265 emitConstant(DispVal, 4);
269 // Otherwise, this is something that requires a relocation. Emit it as such
271 if (RelocOp->isGlobalAddress()) {
272 // In 64-bit static small code model, we could potentially emit absolute.
273 // But it's probably not beneficial.
274 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
275 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
276 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
277 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
278 bool NeedStub = isa<Function>(RelocOp->getGlobal());
279 bool isLazy = gvNeedsLazyPtr(RelocOp->getGlobal());
280 emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
281 PCAdj, NeedStub, isLazy);
282 } else if (RelocOp->isConstantPoolIndex()) {
283 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
284 emitConstPoolAddress(RelocOp->getIndex(), rt,
285 RelocOp->getOffset(), PCAdj);
286 } else if (RelocOp->isJumpTableIndex()) {
287 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
288 emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
290 assert(0 && "Unknown value to relocate!");
294 void Emitter::emitMemModRMByte(const MachineInstr &MI,
295 unsigned Op, unsigned RegOpcodeField,
297 const MachineOperand &Op3 = MI.getOperand(Op+3);
299 const MachineOperand *DispForReloc = 0;
301 // Figure out what sort of displacement we have to handle here.
302 if (Op3.isGlobalAddress()) {
304 } else if (Op3.isConstantPoolIndex()) {
305 if (Is64BitMode || IsPIC) {
308 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
309 DispVal += Op3.getOffset();
311 } else if (Op3.isJumpTableIndex()) {
312 if (Is64BitMode || IsPIC) {
315 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
318 DispVal = Op3.getImm();
321 const MachineOperand &Base = MI.getOperand(Op);
322 const MachineOperand &Scale = MI.getOperand(Op+1);
323 const MachineOperand &IndexReg = MI.getOperand(Op+2);
325 unsigned BaseReg = Base.getReg();
327 // Is a SIB byte needed?
328 if (IndexReg.getReg() == 0 &&
329 (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
330 if (BaseReg == 0) { // Just a displacement?
331 // Emit special case [disp32] encoding
332 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
334 emitDisplacementField(DispForReloc, DispVal, PCAdj);
336 unsigned BaseRegNo = getX86RegNum(BaseReg);
337 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
338 // Emit simple indirect register encoding... [EAX] f.e.
339 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
340 } else if (!DispForReloc && isDisp8(DispVal)) {
341 // Emit the disp8 encoding... [REG+disp8]
342 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
343 emitConstant(DispVal, 1);
345 // Emit the most general non-SIB encoding: [REG+disp32]
346 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
347 emitDisplacementField(DispForReloc, DispVal, PCAdj);
351 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
352 assert(IndexReg.getReg() != X86::ESP &&
353 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
355 bool ForceDisp32 = false;
356 bool ForceDisp8 = false;
358 // If there is no base register, we emit the special case SIB byte with
359 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
360 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
362 } else if (DispForReloc) {
363 // Emit the normal disp32 encoding.
364 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
366 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
367 // Emit no displacement ModR/M byte
368 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
369 } else if (isDisp8(DispVal)) {
370 // Emit the disp8 encoding...
371 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
372 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
374 // Emit the normal disp32 encoding...
375 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
378 // Calculate what the SS field value should be...
379 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
380 unsigned SS = SSTable[Scale.getImm()];
383 // Handle the SIB byte for the case where there is no base. The
384 // displacement has already been output.
385 assert(IndexReg.getReg() && "Index register must be specified!");
386 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
388 unsigned BaseRegNo = getX86RegNum(BaseReg);
390 if (IndexReg.getReg())
391 IndexRegNo = getX86RegNum(IndexReg.getReg());
393 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
394 emitSIBByte(SS, IndexRegNo, BaseRegNo);
397 // Do we need to output a displacement?
399 emitConstant(DispVal, 1);
400 } else if (DispVal != 0 || ForceDisp32) {
401 emitDisplacementField(DispForReloc, DispVal, PCAdj);
406 static unsigned sizeOfImm(const TargetInstrDesc *Desc) {
407 switch (Desc->TSFlags & X86II::ImmMask) {
408 case X86II::Imm8: return 1;
409 case X86II::Imm16: return 2;
410 case X86II::Imm32: return 4;
411 case X86II::Imm64: return 8;
412 default: assert(0 && "Immediate size not set!");
417 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
418 /// e.g. r8, xmm8, etc.
419 bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
420 if (!MO.isRegister()) return false;
421 switch (MO.getReg()) {
423 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
424 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
425 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
426 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
427 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
428 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
429 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
430 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
431 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
432 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
438 inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
439 return (reg == X86::SPL || reg == X86::BPL ||
440 reg == X86::SIL || reg == X86::DIL);
443 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
444 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
445 /// size, and 3) use of X86-64 extended registers.
446 unsigned Emitter::determineREX(const MachineInstr &MI) {
448 const TargetInstrDesc &Desc = MI.getDesc();
450 // Pseudo instructions do not need REX prefix byte.
451 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
453 if (Desc.TSFlags & X86II::REX_W)
456 unsigned NumOps = Desc.getNumOperands();
458 bool isTwoAddr = NumOps > 1 &&
459 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
461 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
462 unsigned i = isTwoAddr ? 1 : 0;
463 for (unsigned e = NumOps; i != e; ++i) {
464 const MachineOperand& MO = MI.getOperand(i);
465 if (MO.isRegister()) {
466 unsigned Reg = MO.getReg();
467 if (isX86_64NonExtLowByteReg(Reg))
472 switch (Desc.TSFlags & X86II::FormMask) {
473 case X86II::MRMInitReg:
474 if (isX86_64ExtendedReg(MI.getOperand(0)))
475 REX |= (1 << 0) | (1 << 2);
477 case X86II::MRMSrcReg: {
478 if (isX86_64ExtendedReg(MI.getOperand(0)))
480 i = isTwoAddr ? 2 : 1;
481 for (unsigned e = NumOps; i != e; ++i) {
482 const MachineOperand& MO = MI.getOperand(i);
483 if (isX86_64ExtendedReg(MO))
488 case X86II::MRMSrcMem: {
489 if (isX86_64ExtendedReg(MI.getOperand(0)))
492 i = isTwoAddr ? 2 : 1;
493 for (; i != NumOps; ++i) {
494 const MachineOperand& MO = MI.getOperand(i);
495 if (MO.isRegister()) {
496 if (isX86_64ExtendedReg(MO))
503 case X86II::MRM0m: case X86II::MRM1m:
504 case X86II::MRM2m: case X86II::MRM3m:
505 case X86II::MRM4m: case X86II::MRM5m:
506 case X86II::MRM6m: case X86II::MRM7m:
507 case X86II::MRMDestMem: {
508 unsigned e = isTwoAddr ? 5 : 4;
509 i = isTwoAddr ? 1 : 0;
510 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
513 for (; i != e; ++i) {
514 const MachineOperand& MO = MI.getOperand(i);
515 if (MO.isRegister()) {
516 if (isX86_64ExtendedReg(MO))
524 if (isX86_64ExtendedReg(MI.getOperand(0)))
526 i = isTwoAddr ? 2 : 1;
527 for (unsigned e = NumOps; i != e; ++i) {
528 const MachineOperand& MO = MI.getOperand(i);
529 if (isX86_64ExtendedReg(MO))
539 void Emitter::emitInstruction(const MachineInstr &MI,
540 const TargetInstrDesc *Desc) {
541 unsigned Opcode = Desc->Opcode;
543 // Emit the lock opcode prefix as needed.
544 if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
546 // Emit the repeat opcode prefix as needed.
547 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
549 // Emit the operand size opcode prefix as needed.
550 if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
552 // Emit the address size opcode prefix as needed.
553 if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
555 bool Need0FPrefix = false;
556 switch (Desc->TSFlags & X86II::Op0Mask) {
558 Need0FPrefix = true; // Two-byte opcode prefix
568 case X86II::REP: break; // already handled.
569 case X86II::XS: // F3 0F
573 case X86II::XD: // F2 0F
577 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
578 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
580 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
581 >> X86II::Op0Shift));
582 break; // Two-byte opcode prefix
583 default: assert(0 && "Invalid prefix!");
584 case 0: break; // No prefix!
589 unsigned REX = determineREX(MI);
591 MCE.emitByte(0x40 | REX);
594 // 0x0F escape code must be emitted just before the opcode.
598 // If this is a two-address instruction, skip one of the register operands.
599 unsigned NumOps = Desc->getNumOperands();
601 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
604 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
605 switch (Desc->TSFlags & X86II::FormMask) {
606 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
608 // Remember the current PC offset, this is the PIC relocation
612 assert(0 && "psuedo instructions should be removed before code emission");
613 case TargetInstrInfo::INLINEASM:
614 assert(0 && "JIT does not support inline asm!\n");
615 case TargetInstrInfo::LABEL:
616 MCE.emitLabel(MI.getOperand(0).getImm());
618 case X86::IMPLICIT_DEF_GR8:
619 case X86::IMPLICIT_DEF_GR16:
620 case X86::IMPLICIT_DEF_GR32:
621 case X86::IMPLICIT_DEF_GR64:
622 case X86::IMPLICIT_DEF_FR32:
623 case X86::IMPLICIT_DEF_FR64:
624 case X86::IMPLICIT_DEF_VR64:
625 case X86::IMPLICIT_DEF_VR128:
626 case X86::FP_REG_KILL:
628 case X86::MOVPC32r: {
629 // This emits the "call" portion of this pseudo instruction.
630 MCE.emitByte(BaseOpcode);
631 emitConstant(0, sizeOfImm(Desc));
632 // Remember PIC base.
633 PICBaseOffset = MCE.getCurrentPCOffset();
634 X86JITInfo *JTI = dynamic_cast<X86JITInfo*>(TM.getJITInfo());
635 JTI->setPICBase(MCE.getCurrentPCValue());
642 MCE.emitByte(BaseOpcode);
644 if (CurOp != NumOps) {
645 const MachineOperand &MO = MI.getOperand(CurOp++);
646 if (MO.isMachineBasicBlock()) {
647 emitPCRelativeBlockAddress(MO.getMBB());
648 } else if (MO.isGlobalAddress()) {
649 bool NeedStub = (Is64BitMode && TM.getCodeModel() == CodeModel::Large)
650 || Opcode == X86::TAILJMPd;
651 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
653 } else if (MO.isExternalSymbol()) {
654 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
655 } else if (MO.isImmediate()) {
656 emitConstant(MO.getImm(), sizeOfImm(Desc));
658 assert(0 && "Unknown RawFrm operand!");
663 case X86II::AddRegFrm:
664 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
666 if (CurOp != NumOps) {
667 const MachineOperand &MO1 = MI.getOperand(CurOp++);
668 unsigned Size = sizeOfImm(Desc);
669 if (MO1.isImmediate())
670 emitConstant(MO1.getImm(), Size);
672 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
673 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
674 if (Opcode == X86::MOV64ri)
675 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
676 if (MO1.isGlobalAddress()) {
677 bool NeedStub = isa<Function>(MO1.getGlobal());
678 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
679 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
681 } else if (MO1.isExternalSymbol())
682 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
683 else if (MO1.isConstantPoolIndex())
684 emitConstPoolAddress(MO1.getIndex(), rt);
685 else if (MO1.isJumpTableIndex())
686 emitJumpTableAddress(MO1.getIndex(), rt);
691 case X86II::MRMDestReg: {
692 MCE.emitByte(BaseOpcode);
693 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
694 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
697 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
700 case X86II::MRMDestMem: {
701 MCE.emitByte(BaseOpcode);
702 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
705 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
709 case X86II::MRMSrcReg:
710 MCE.emitByte(BaseOpcode);
711 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
712 getX86RegNum(MI.getOperand(CurOp).getReg()));
715 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
718 case X86II::MRMSrcMem: {
719 intptr_t PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0;
721 MCE.emitByte(BaseOpcode);
722 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
726 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
730 case X86II::MRM0r: case X86II::MRM1r:
731 case X86II::MRM2r: case X86II::MRM3r:
732 case X86II::MRM4r: case X86II::MRM5r:
733 case X86II::MRM6r: case X86II::MRM7r:
734 MCE.emitByte(BaseOpcode);
735 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
736 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
738 if (CurOp != NumOps) {
739 const MachineOperand &MO1 = MI.getOperand(CurOp++);
740 unsigned Size = sizeOfImm(Desc);
741 if (MO1.isImmediate())
742 emitConstant(MO1.getImm(), Size);
744 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
745 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
746 if (Opcode == X86::MOV64ri32)
747 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
748 if (MO1.isGlobalAddress()) {
749 bool NeedStub = isa<Function>(MO1.getGlobal());
750 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
751 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
753 } else if (MO1.isExternalSymbol())
754 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
755 else if (MO1.isConstantPoolIndex())
756 emitConstPoolAddress(MO1.getIndex(), rt);
757 else if (MO1.isJumpTableIndex())
758 emitJumpTableAddress(MO1.getIndex(), rt);
763 case X86II::MRM0m: case X86II::MRM1m:
764 case X86II::MRM2m: case X86II::MRM3m:
765 case X86II::MRM4m: case X86II::MRM5m:
766 case X86II::MRM6m: case X86II::MRM7m: {
767 intptr_t PCAdj = (CurOp+4 != NumOps) ?
768 (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
770 MCE.emitByte(BaseOpcode);
771 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
775 if (CurOp != NumOps) {
776 const MachineOperand &MO = MI.getOperand(CurOp++);
777 unsigned Size = sizeOfImm(Desc);
778 if (MO.isImmediate())
779 emitConstant(MO.getImm(), Size);
781 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
782 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
783 if (Opcode == X86::MOV64mi32)
784 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
785 if (MO.isGlobalAddress()) {
786 bool NeedStub = isa<Function>(MO.getGlobal());
787 bool isLazy = gvNeedsLazyPtr(MO.getGlobal());
788 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
790 } else if (MO.isExternalSymbol())
791 emitExternalSymbolAddress(MO.getSymbolName(), rt);
792 else if (MO.isConstantPoolIndex())
793 emitConstPoolAddress(MO.getIndex(), rt);
794 else if (MO.isJumpTableIndex())
795 emitJumpTableAddress(MO.getIndex(), rt);
801 case X86II::MRMInitReg:
802 MCE.emitByte(BaseOpcode);
803 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
804 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
805 getX86RegNum(MI.getOperand(CurOp).getReg()));
810 assert((Desc->isVariadic() || CurOp == NumOps) && "Unknown encoding!");