1 //===-- X86/MachineCodeEmitter.cpp - Convert X86 code to machine code -----===//
3 // This file contains the pass that transforms the X86 machine instructions into
4 // actual executable machine code.
6 //===----------------------------------------------------------------------===//
8 #include "X86TargetMachine.h"
10 #include "llvm/PassManager.h"
11 #include "llvm/CodeGen/MachineCodeEmitter.h"
12 #include "llvm/CodeGen/MachineFunctionPass.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/Value.h"
17 class Emitter : public MachineFunctionPass {
18 const X86InstrInfo *II;
19 MachineCodeEmitter &MCE;
22 Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {}
24 bool runOnMachineFunction(MachineFunction &MF);
26 virtual const char *getPassName() const {
27 return "X86 Machine Code Emitter";
31 void emitBasicBlock(MachineBasicBlock &MBB);
32 void emitInstruction(MachineInstr &MI);
34 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
35 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
36 void emitConstant(unsigned Val, unsigned Size);
38 void emitMemModRMByte(const MachineInstr &MI,
39 unsigned Op, unsigned RegOpcodeField);
45 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
46 /// machine code emitted. This uses a MAchineCodeEmitter object to handle
47 /// actually outputting the machine code and resolving things like the address
48 /// of functions. This method should returns true if machine code emission is
51 bool X86TargetMachine::addPassesToEmitMachineCode(PassManager &PM,
52 MachineCodeEmitter &MCE) {
53 PM.add(new Emitter(MCE));
57 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
58 II = &((X86TargetMachine&)MF.getTarget()).getInstrInfo();
60 MCE.startFunction(MF);
61 MCE.emitConstantPool(MF.getConstantPool());
62 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
64 MCE.finishFunction(MF);
68 void Emitter::emitBasicBlock(MachineBasicBlock &MBB) {
69 MCE.startBasicBlock(MBB);
70 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
75 namespace N86 { // Native X86 Register numbers...
77 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
82 // getX86RegNum - This function maps LLVM register identifiers to their X86
83 // specific numbering, which is used in various places encoding instructions.
85 static unsigned getX86RegNum(unsigned RegNo) {
87 case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
88 case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
89 case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
90 case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
91 case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
92 case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
93 case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
94 case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
96 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
97 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
98 return RegNo-X86::ST0;
100 assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
101 "Unknown physical register!");
102 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
107 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
109 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
110 return RM | (RegOpcode << 3) | (Mod << 6);
113 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
114 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
117 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
118 // SIB byte is in the same format as the ModRMByte...
119 MCE.emitByte(ModRMByte(SS, Index, Base));
122 void Emitter::emitConstant(unsigned Val, unsigned Size) {
123 // Output the constant in little endian byte order...
124 for (unsigned i = 0; i != Size; ++i) {
125 MCE.emitByte(Val & 255);
130 static bool isDisp8(int Value) {
131 return Value == (signed char)Value;
134 void Emitter::emitMemModRMByte(const MachineInstr &MI,
135 unsigned Op, unsigned RegOpcodeField) {
136 const MachineOperand &Disp = MI.getOperand(Op+3);
137 if (MI.getOperand(Op).isConstantPoolIndex()) {
138 // Emit a direct address reference [disp32] where the displacement is
139 // controlled by the MCE.
140 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
141 unsigned Index = MI.getOperand(Op).getConstantPoolIndex();
142 MCE.emitFunctionConstantValueAddress(Index, Disp.getImmedValue());
146 const MachineOperand &BaseReg = MI.getOperand(Op);
147 const MachineOperand &Scale = MI.getOperand(Op+1);
148 const MachineOperand &IndexReg = MI.getOperand(Op+2);
150 // Is a SIB byte needed?
151 if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
152 if (BaseReg.getReg() == 0) { // Just a displacement?
153 // Emit special case [disp32] encoding
154 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
155 emitConstant(Disp.getImmedValue(), 4);
157 unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
158 if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
159 // Emit simple indirect register encoding... [EAX] f.e.
160 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
161 } else if (isDisp8(Disp.getImmedValue())) {
162 // Emit the disp8 encoding... [REG+disp8]
163 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
164 emitConstant(Disp.getImmedValue(), 1);
166 // Emit the most general non-SIB encoding: [REG+disp32]
167 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
168 emitConstant(Disp.getImmedValue(), 4);
172 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
173 assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
175 bool ForceDisp32 = false;
176 bool ForceDisp8 = false;
177 if (BaseReg.getReg() == 0) {
178 // If there is no base register, we emit the special case SIB byte with
179 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
180 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
182 } else if (Disp.getImmedValue() == 0 && BaseReg.getReg() != X86::EBP) {
183 // Emit no displacement ModR/M byte
184 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
185 } else if (isDisp8(Disp.getImmedValue())) {
186 // Emit the disp8 encoding...
187 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
188 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
190 // Emit the normal disp32 encoding...
191 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
194 // Calculate what the SS field value should be...
195 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
196 unsigned SS = SSTable[Scale.getImmedValue()];
198 if (BaseReg.getReg() == 0) {
199 // Handle the SIB byte for the case where there is no base. The
200 // displacement has already been output.
201 assert(IndexReg.getReg() && "Index register must be specified!");
202 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
204 unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
206 if (IndexReg.getReg())
207 IndexRegNo = getX86RegNum(IndexReg.getReg());
209 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
210 emitSIBByte(SS, IndexRegNo, BaseRegNo);
213 // Do we need to output a displacement?
214 if (Disp.getImmedValue() != 0 || ForceDisp32 || ForceDisp8) {
215 if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
216 emitConstant(Disp.getImmedValue(), 1);
218 emitConstant(Disp.getImmedValue(), 4);
223 unsigned sizeOfPtr(const TargetInstrDescriptor &Desc) {
224 switch (Desc.TSFlags & X86II::ArgMask) {
225 case X86II::Arg8: return 1;
226 case X86II::Arg16: return 2;
227 case X86II::Arg32: return 4;
228 case X86II::ArgF32: return 4;
229 case X86II::ArgF64: return 8;
230 case X86II::ArgF80: return 10;
231 default: assert(0 && "Memory size not set!");
237 void Emitter::emitInstruction(MachineInstr &MI) {
238 unsigned Opcode = MI.getOpcode();
239 const TargetInstrDescriptor &Desc = II->get(Opcode);
241 // Emit instruction prefixes if neccesary
242 if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
244 switch (Desc.TSFlags & X86II::Op0Mask) {
246 MCE.emitByte(0x0F); // Two-byte opcode prefix
248 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
249 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
251 (((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
252 >> X86II::Op0Shift));
253 break; // Two-byte opcode prefix
254 default: assert(0 && "Invalid prefix!");
255 case 0: break; // No prefix!
258 unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
259 switch (Desc.TSFlags & X86II::FormMask) {
260 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
262 std::cerr << "X86 Machine Code Emitter: No 'form', not emitting: " << MI;
266 MCE.emitByte(BaseOpcode);
267 if (MI.getNumOperands() == 1) {
268 MachineOperand &MO = MI.getOperand(0);
269 if (MO.isPCRelativeDisp()) {
270 MCE.emitPCRelativeDisp(MO.getVRegValue());
271 } else if (MO.isGlobalAddress()) {
272 MCE.emitGlobalAddress(MO.getGlobal(), MO.isPCRelative());
273 } else if (MO.isExternalSymbol()) {
274 MCE.emitGlobalAddress(MO.getSymbolName(), MO.isPCRelative());
276 assert(0 && "Unknown RawFrm operand!");
281 case X86II::AddRegFrm:
282 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
283 if (MI.getNumOperands() == 2) {
284 MachineOperand &MO1 = MI.getOperand(1);
285 if (MO1.isImmediate() || MO1.getVRegValueOrNull() ||
286 MO1.isGlobalAddress() || MO1.isExternalSymbol()) {
287 unsigned Size = sizeOfPtr(Desc);
288 if (Value *V = MO1.getVRegValueOrNull()) {
289 assert(Size == 4 && "Don't know how to emit non-pointer values!");
290 MCE.emitGlobalAddress(cast<GlobalValue>(V), false);
291 } else if (MO1.isGlobalAddress()) {
292 assert(Size == 4 && "Don't know how to emit non-pointer values!");
293 MCE.emitGlobalAddress(MO1.getGlobal(), MO1.isPCRelative());
294 } else if (MO1.isExternalSymbol()) {
295 assert(Size == 4 && "Don't know how to emit non-pointer values!");
296 MCE.emitGlobalAddress(MO1.getSymbolName(), MO1.isPCRelative());
298 emitConstant(MO1.getImmedValue(), Size);
304 case X86II::MRMDestReg: {
305 MCE.emitByte(BaseOpcode);
306 MachineOperand &SrcOp = MI.getOperand(1+II->isTwoAddrInstr(Opcode));
307 emitRegModRMByte(MI.getOperand(0).getReg(), getX86RegNum(SrcOp.getReg()));
308 if (MI.getNumOperands() == 4)
309 emitConstant(MI.getOperand(3).getImmedValue(), sizeOfPtr(Desc));
312 case X86II::MRMDestMem:
313 MCE.emitByte(BaseOpcode);
314 emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
317 case X86II::MRMSrcReg:
318 MCE.emitByte(BaseOpcode);
319 emitRegModRMByte(MI.getOperand(MI.getNumOperands()-1).getReg(),
320 getX86RegNum(MI.getOperand(0).getReg()));
323 case X86II::MRMSrcMem:
324 MCE.emitByte(BaseOpcode);
325 emitMemModRMByte(MI, MI.getNumOperands()-4,
326 getX86RegNum(MI.getOperand(0).getReg()));
329 case X86II::MRMS0r: case X86II::MRMS1r:
330 case X86II::MRMS2r: case X86II::MRMS3r:
331 case X86II::MRMS4r: case X86II::MRMS5r:
332 case X86II::MRMS6r: case X86II::MRMS7r:
333 MCE.emitByte(BaseOpcode);
334 emitRegModRMByte(MI.getOperand(0).getReg(),
335 (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r);
337 if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
338 unsigned Size = sizeOfPtr(Desc);
339 emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(), Size);
343 case X86II::MRMS0m: case X86II::MRMS1m:
344 case X86II::MRMS2m: case X86II::MRMS3m:
345 case X86II::MRMS4m: case X86II::MRMS5m:
346 case X86II::MRMS6m: case X86II::MRMS7m:
347 MCE.emitByte(BaseOpcode);
348 emitMemModRMByte(MI, 0, (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0m);
350 if (MI.getNumOperands() == 5) {
351 unsigned Size = sizeOfPtr(Desc);
352 emitConstant(MI.getOperand(4).getImmedValue(), Size);