1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/JITCodeEmitter.h"
25 #include "llvm/CodeGen/ObjectCodeEmitter.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/Function.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/MC/MCCodeEmitter.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/Compiler.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 STATISTIC(NumEmitted, "Number of machine instructions emitted");
45 template<class CodeEmitter>
46 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
47 const X86InstrInfo *II;
51 intptr_t PICBaseOffset;
56 explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
57 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
58 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
59 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
60 Emitter(X86TargetMachine &tm, CodeEmitter &mce,
61 const X86InstrInfo &ii, const TargetData &td, bool is64)
62 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
63 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
64 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
66 bool runOnMachineFunction(MachineFunction &MF);
68 virtual const char *getPassName() const {
69 return "X86 Machine Code Emitter";
72 void emitInstruction(const MachineInstr &MI,
73 const TargetInstrDesc *Desc);
75 void getAnalysisUsage(AnalysisUsage &AU) const {
77 AU.addRequired<MachineModuleInfo>();
78 MachineFunctionPass::getAnalysisUsage(AU);
82 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
83 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
84 intptr_t Disp = 0, intptr_t PCAdj = 0,
85 bool NeedStub = false, bool Indirect = false);
86 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
87 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
89 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
92 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
93 intptr_t Adj = 0, bool IsPCRel = true);
95 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
96 void emitRegModRMByte(unsigned RegOpcodeField);
97 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
98 void emitConstant(uint64_t Val, unsigned Size);
100 void emitMemModRMByte(const MachineInstr &MI,
101 unsigned Op, unsigned RegOpcodeField,
104 unsigned getX86RegNum(unsigned RegNo) const;
107 template<class CodeEmitter>
108 char Emitter<CodeEmitter>::ID = 0;
109 } // end anonymous namespace.
111 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
112 /// to the specified templated MachineCodeEmitter object.
114 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
115 MachineCodeEmitter &MCE) {
116 return new Emitter<MachineCodeEmitter>(TM, MCE);
118 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
119 JITCodeEmitter &JCE) {
120 return new Emitter<JITCodeEmitter>(TM, JCE);
122 FunctionPass *llvm::createX86ObjectCodeEmitterPass(X86TargetMachine &TM,
123 ObjectCodeEmitter &OCE) {
124 return new Emitter<ObjectCodeEmitter>(TM, OCE);
127 template<class CodeEmitter>
128 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
130 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
132 II = TM.getInstrInfo();
133 TD = TM.getTargetData();
134 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
135 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
138 DEBUG(errs() << "JITTing function '"
139 << MF.getFunction()->getName() << "'\n");
140 MCE.startFunction(MF);
141 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
143 MCE.StartMachineBasicBlock(MBB);
144 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
146 const TargetInstrDesc &Desc = I->getDesc();
147 emitInstruction(*I, &Desc);
148 // MOVPC32r is basically a call plus a pop instruction.
149 if (Desc.getOpcode() == X86::MOVPC32r)
150 emitInstruction(*I, &II->get(X86::POP32r));
151 NumEmitted++; // Keep track of the # of mi's emitted
154 } while (MCE.finishFunction(MF));
159 /// emitPCRelativeBlockAddress - This method keeps track of the information
160 /// necessary to resolve the address of this block later and emits a dummy
163 template<class CodeEmitter>
164 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
165 // Remember where this reference was and where it is to so we can
166 // deal with it later.
167 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
168 X86::reloc_pcrel_word, MBB));
172 /// emitGlobalAddress - Emit the specified address to the code stream assuming
173 /// this is part of a "take the address of a global" instruction.
175 template<class CodeEmitter>
176 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
177 intptr_t Disp /* = 0 */,
178 intptr_t PCAdj /* = 0 */,
179 bool NeedStub /* = false */,
180 bool Indirect /* = false */) {
181 intptr_t RelocCST = Disp;
182 if (Reloc == X86::reloc_picrel_word)
183 RelocCST = PICBaseOffset;
184 else if (Reloc == X86::reloc_pcrel_word)
186 MachineRelocation MR = Indirect
187 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
188 GV, RelocCST, NeedStub)
189 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
190 GV, RelocCST, NeedStub);
191 MCE.addRelocation(MR);
192 // The relocated value will be added to the displacement
193 if (Reloc == X86::reloc_absolute_dword)
194 MCE.emitDWordLE(Disp);
196 MCE.emitWordLE((int32_t)Disp);
199 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
200 /// be emitted to the current location in the function, and allow it to be PC
202 template<class CodeEmitter>
203 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
205 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
206 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
207 Reloc, ES, RelocCST));
208 if (Reloc == X86::reloc_absolute_dword)
214 /// emitConstPoolAddress - Arrange for the address of an constant pool
215 /// to be emitted to the current location in the function, and allow it to be PC
217 template<class CodeEmitter>
218 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
219 intptr_t Disp /* = 0 */,
220 intptr_t PCAdj /* = 0 */) {
221 intptr_t RelocCST = 0;
222 if (Reloc == X86::reloc_picrel_word)
223 RelocCST = PICBaseOffset;
224 else if (Reloc == X86::reloc_pcrel_word)
226 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
227 Reloc, CPI, RelocCST));
228 // The relocated value will be added to the displacement
229 if (Reloc == X86::reloc_absolute_dword)
230 MCE.emitDWordLE(Disp);
232 MCE.emitWordLE((int32_t)Disp);
235 /// emitJumpTableAddress - Arrange for the address of a jump table to
236 /// be emitted to the current location in the function, and allow it to be PC
238 template<class CodeEmitter>
239 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
240 intptr_t PCAdj /* = 0 */) {
241 intptr_t RelocCST = 0;
242 if (Reloc == X86::reloc_picrel_word)
243 RelocCST = PICBaseOffset;
244 else if (Reloc == X86::reloc_pcrel_word)
246 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
247 Reloc, JTI, RelocCST));
248 // The relocated value will be added to the displacement
249 if (Reloc == X86::reloc_absolute_dword)
255 template<class CodeEmitter>
256 unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
257 return II->getRegisterInfo().getX86RegNum(RegNo);
260 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
262 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
263 return RM | (RegOpcode << 3) | (Mod << 6);
266 template<class CodeEmitter>
267 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
268 unsigned RegOpcodeFld){
269 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
272 template<class CodeEmitter>
273 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
274 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
277 template<class CodeEmitter>
278 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
281 // SIB byte is in the same format as the ModRMByte...
282 MCE.emitByte(ModRMByte(SS, Index, Base));
285 template<class CodeEmitter>
286 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
287 // Output the constant in little endian byte order...
288 for (unsigned i = 0; i != Size; ++i) {
289 MCE.emitByte(Val & 255);
294 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
295 /// sign-extended field.
296 static bool isDisp8(int Value) {
297 return Value == (signed char)Value;
300 static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
301 const TargetMachine &TM) {
302 // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer
303 // mechanism as 32-bit mode.
304 if (TM.getSubtarget<X86Subtarget>().is64Bit() &&
305 !TM.getSubtarget<X86Subtarget>().isTargetDarwin())
308 // Return true if this is a reference to a stub containing the address of the
309 // global, not the global itself.
310 return isGlobalStubReference(GVOp.getTargetFlags());
313 template<class CodeEmitter>
314 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
316 intptr_t Adj /* = 0 */,
317 bool IsPCRel /* = true */) {
318 // If this is a simple integer displacement that doesn't require a relocation,
321 emitConstant(DispVal, 4);
325 // Otherwise, this is something that requires a relocation. Emit it as such
327 unsigned RelocType = Is64BitMode ?
328 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
329 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
330 if (RelocOp->isGlobal()) {
331 // In 64-bit static small code model, we could potentially emit absolute.
332 // But it's probably not beneficial. If the MCE supports using RIP directly
333 // do it, otherwise fallback to absolute (this is determined by IsPCRel).
334 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
335 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
336 bool NeedStub = isa<Function>(RelocOp->getGlobal());
337 bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
338 emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
339 Adj, NeedStub, Indirect);
340 } else if (RelocOp->isSymbol()) {
341 emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
342 } else if (RelocOp->isCPI()) {
343 emitConstPoolAddress(RelocOp->getIndex(), RelocType,
344 RelocOp->getOffset(), Adj);
346 assert(RelocOp->isJTI() && "Unexpected machine operand!");
347 emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
351 template<class CodeEmitter>
352 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
353 unsigned Op,unsigned RegOpcodeField,
355 const MachineOperand &Op3 = MI.getOperand(Op+3);
357 const MachineOperand *DispForReloc = 0;
359 // Figure out what sort of displacement we have to handle here.
360 if (Op3.isGlobal()) {
362 } else if (Op3.isSymbol()) {
364 } else if (Op3.isCPI()) {
365 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
368 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
369 DispVal += Op3.getOffset();
371 } else if (Op3.isJTI()) {
372 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
375 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
378 DispVal = Op3.getImm();
381 const MachineOperand &Base = MI.getOperand(Op);
382 const MachineOperand &Scale = MI.getOperand(Op+1);
383 const MachineOperand &IndexReg = MI.getOperand(Op+2);
385 unsigned BaseReg = Base.getReg();
387 // Indicate that the displacement will use an pcrel or absolute reference
388 // by default. MCEs able to resolve addresses on-the-fly use pcrel by default
389 // while others, unless explicit asked to use RIP, use absolute references.
390 bool IsPCRel = MCE.earlyResolveAddresses() ? true : false;
392 // Is a SIB byte needed?
393 // If no BaseReg, issue a RIP relative instruction only if the MCE can
394 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
395 // 2-7) and absolute references.
396 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
397 IndexReg.getReg() == 0 &&
398 ((BaseReg == 0 && MCE.earlyResolveAddresses()) || BaseReg == X86::RIP ||
399 (BaseReg != 0 && getX86RegNum(BaseReg) != N86::ESP))) {
400 if (BaseReg == 0 || BaseReg == X86::RIP) { // Just a displacement?
401 // Emit special case [disp32] encoding
402 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
403 emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
405 unsigned BaseRegNo = getX86RegNum(BaseReg);
406 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
407 // Emit simple indirect register encoding... [EAX] f.e.
408 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
409 } else if (!DispForReloc && isDisp8(DispVal)) {
410 // Emit the disp8 encoding... [REG+disp8]
411 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
412 emitConstant(DispVal, 1);
414 // Emit the most general non-SIB encoding: [REG+disp32]
415 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
416 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
420 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
421 assert(IndexReg.getReg() != X86::ESP &&
422 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
424 bool ForceDisp32 = false;
425 bool ForceDisp8 = false;
427 // If there is no base register, we emit the special case SIB byte with
428 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
429 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
431 } else if (DispForReloc) {
432 // Emit the normal disp32 encoding.
433 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
435 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
436 // Emit no displacement ModR/M byte
437 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
438 } else if (isDisp8(DispVal)) {
439 // Emit the disp8 encoding...
440 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
441 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
443 // Emit the normal disp32 encoding...
444 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
447 // Calculate what the SS field value should be...
448 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
449 unsigned SS = SSTable[Scale.getImm()];
452 // Handle the SIB byte for the case where there is no base, see Intel
453 // Manual 2A, table 2-7. The displacement has already been output.
455 if (IndexReg.getReg())
456 IndexRegNo = getX86RegNum(IndexReg.getReg());
457 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
459 emitSIBByte(SS, IndexRegNo, 5);
461 unsigned BaseRegNo = getX86RegNum(BaseReg);
463 if (IndexReg.getReg())
464 IndexRegNo = getX86RegNum(IndexReg.getReg());
466 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
467 emitSIBByte(SS, IndexRegNo, BaseRegNo);
470 // Do we need to output a displacement?
472 emitConstant(DispVal, 1);
473 } else if (DispVal != 0 || ForceDisp32) {
474 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
479 template<class CodeEmitter>
480 void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI,
481 const TargetInstrDesc *Desc) {
484 MCE.processDebugLoc(MI.getDebugLoc());
486 unsigned Opcode = Desc->Opcode;
488 // Emit the lock opcode prefix as needed.
489 if (Desc->TSFlags & X86II::LOCK)
492 // Emit segment override opcode prefix as needed.
493 switch (Desc->TSFlags & X86II::SegOvrMask) {
500 default: llvm_unreachable("Invalid segment!");
501 case 0: break; // No segment override!
504 // Emit the repeat opcode prefix as needed.
505 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
508 // Emit the operand size opcode prefix as needed.
509 if (Desc->TSFlags & X86II::OpSize)
512 // Emit the address size opcode prefix as needed.
513 if (Desc->TSFlags & X86II::AdSize)
516 bool Need0FPrefix = false;
517 switch (Desc->TSFlags & X86II::Op0Mask) {
518 case X86II::TB: // Two-byte opcode prefix
519 case X86II::T8: // 0F 38
520 case X86II::TA: // 0F 3A
523 case X86II::TF: // F2 0F 38
527 case X86II::REP: break; // already handled.
528 case X86II::XS: // F3 0F
532 case X86II::XD: // F2 0F
536 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
537 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
539 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
540 >> X86II::Op0Shift));
541 break; // Two-byte opcode prefix
542 default: llvm_unreachable("Invalid prefix!");
543 case 0: break; // No prefix!
546 // Handle REX prefix.
548 if (unsigned REX = X86InstrInfo::determineREX(MI))
549 MCE.emitByte(0x40 | REX);
552 // 0x0F escape code must be emitted just before the opcode.
556 switch (Desc->TSFlags & X86II::Op0Mask) {
557 case X86II::TF: // F2 0F 38
558 case X86II::T8: // 0F 38
561 case X86II::TA: // 0F 3A
566 // If this is a two-address instruction, skip one of the register operands.
567 unsigned NumOps = Desc->getNumOperands();
569 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
571 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
572 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
575 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
576 switch (Desc->TSFlags & X86II::FormMask) {
578 llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
580 // Remember the current PC offset, this is the PIC relocation
584 llvm_unreachable("psuedo instructions should be removed before code"
587 case TargetInstrInfo::INLINEASM:
588 // We allow inline assembler nodes with empty bodies - they can
589 // implicitly define registers, which is ok for JIT.
590 assert(MI.getOperand(0).getSymbolName()[0] == 0 &&
591 "JIT does not support inline asm!");
593 case TargetInstrInfo::DBG_LABEL:
594 case TargetInstrInfo::EH_LABEL:
595 case TargetInstrInfo::GC_LABEL:
596 MCE.emitLabel(MI.getOperand(0).getImm());
598 case TargetInstrInfo::IMPLICIT_DEF:
600 case X86::FP_REG_KILL:
602 case X86::MOVPC32r: {
603 // This emits the "call" portion of this pseudo instruction.
604 MCE.emitByte(BaseOpcode);
605 emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
606 // Remember PIC base.
607 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
608 X86JITInfo *JTI = TM.getJITInfo();
609 JTI->setPICBase(MCE.getCurrentPCValue());
615 case X86II::RawFrm: {
616 MCE.emitByte(BaseOpcode);
621 const MachineOperand &MO = MI.getOperand(CurOp++);
623 DEBUG(errs() << "RawFrm CurOp " << CurOp << "\n");
624 DEBUG(errs() << "isMBB " << MO.isMBB() << "\n");
625 DEBUG(errs() << "isGlobal " << MO.isGlobal() << "\n");
626 DEBUG(errs() << "isSymbol " << MO.isSymbol() << "\n");
627 DEBUG(errs() << "isImm " << MO.isImm() << "\n");
630 emitPCRelativeBlockAddress(MO.getMBB());
635 // Assume undefined functions may be outside the Small codespace.
638 (TM.getCodeModel() == CodeModel::Large ||
639 TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
640 Opcode == X86::TAILJMPd;
641 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
642 MO.getOffset(), 0, NeedStub);
647 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
651 assert(MO.isImm() && "Unknown RawFrm operand!");
652 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
653 // Fix up immediate operand for pc relative calls.
654 intptr_t Imm = (intptr_t)MO.getImm();
655 Imm = Imm - MCE.getCurrentPCValue() - 4;
656 emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
658 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
662 case X86II::AddRegFrm: {
663 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
668 const MachineOperand &MO1 = MI.getOperand(CurOp++);
669 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
671 emitConstant(MO1.getImm(), Size);
675 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
676 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
677 if (Opcode == X86::MOV64ri64i32)
678 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
679 // This should not occur on Darwin for relocatable objects.
680 if (Opcode == X86::MOV64ri)
681 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
682 if (MO1.isGlobal()) {
683 bool NeedStub = isa<Function>(MO1.getGlobal());
684 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
685 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
687 } else if (MO1.isSymbol())
688 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
689 else if (MO1.isCPI())
690 emitConstPoolAddress(MO1.getIndex(), rt);
691 else if (MO1.isJTI())
692 emitJumpTableAddress(MO1.getIndex(), rt);
696 case X86II::MRMDestReg: {
697 MCE.emitByte(BaseOpcode);
698 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
699 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
702 emitConstant(MI.getOperand(CurOp++).getImm(),
703 X86InstrInfo::sizeOfImm(Desc));
706 case X86II::MRMDestMem: {
707 MCE.emitByte(BaseOpcode);
708 emitMemModRMByte(MI, CurOp,
709 getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
711 CurOp += X86AddrNumOperands + 1;
713 emitConstant(MI.getOperand(CurOp++).getImm(),
714 X86InstrInfo::sizeOfImm(Desc));
718 case X86II::MRMSrcReg:
719 MCE.emitByte(BaseOpcode);
720 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
721 getX86RegNum(MI.getOperand(CurOp).getReg()));
724 emitConstant(MI.getOperand(CurOp++).getImm(),
725 X86InstrInfo::sizeOfImm(Desc));
728 case X86II::MRMSrcMem: {
729 // FIXME: Maybe lea should have its own form?
731 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
732 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
733 AddrOperands = X86AddrNumOperands - 1; // No segment register
735 AddrOperands = X86AddrNumOperands;
737 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
738 X86InstrInfo::sizeOfImm(Desc) : 0;
740 MCE.emitByte(BaseOpcode);
741 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
743 CurOp += AddrOperands + 1;
745 emitConstant(MI.getOperand(CurOp++).getImm(),
746 X86InstrInfo::sizeOfImm(Desc));
750 case X86II::MRM0r: case X86II::MRM1r:
751 case X86II::MRM2r: case X86II::MRM3r:
752 case X86II::MRM4r: case X86II::MRM5r:
753 case X86II::MRM6r: case X86II::MRM7r: {
754 MCE.emitByte(BaseOpcode);
756 // Special handling of lfence, mfence, monitor, and mwait.
757 if (Desc->getOpcode() == X86::LFENCE ||
758 Desc->getOpcode() == X86::MFENCE ||
759 Desc->getOpcode() == X86::MONITOR ||
760 Desc->getOpcode() == X86::MWAIT) {
761 emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
763 switch (Desc->getOpcode()) {
773 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
774 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
780 const MachineOperand &MO1 = MI.getOperand(CurOp++);
781 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
783 emitConstant(MO1.getImm(), Size);
787 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
788 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
789 if (Opcode == X86::MOV64ri32)
790 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
791 if (MO1.isGlobal()) {
792 bool NeedStub = isa<Function>(MO1.getGlobal());
793 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
794 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
796 } else if (MO1.isSymbol())
797 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
798 else if (MO1.isCPI())
799 emitConstPoolAddress(MO1.getIndex(), rt);
800 else if (MO1.isJTI())
801 emitJumpTableAddress(MO1.getIndex(), rt);
805 case X86II::MRM0m: case X86II::MRM1m:
806 case X86II::MRM2m: case X86II::MRM3m:
807 case X86II::MRM4m: case X86II::MRM5m:
808 case X86II::MRM6m: case X86II::MRM7m: {
809 intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
810 (MI.getOperand(CurOp+X86AddrNumOperands).isImm() ?
811 X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
813 MCE.emitByte(BaseOpcode);
814 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
816 CurOp += X86AddrNumOperands;
821 const MachineOperand &MO = MI.getOperand(CurOp++);
822 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
824 emitConstant(MO.getImm(), Size);
828 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
829 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
830 if (Opcode == X86::MOV64mi32)
831 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
833 bool NeedStub = isa<Function>(MO.getGlobal());
834 bool Indirect = gvNeedsNonLazyPtr(MO, TM);
835 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
837 } else if (MO.isSymbol())
838 emitExternalSymbolAddress(MO.getSymbolName(), rt);
840 emitConstPoolAddress(MO.getIndex(), rt);
842 emitJumpTableAddress(MO.getIndex(), rt);
846 case X86II::MRMInitReg:
847 MCE.emitByte(BaseOpcode);
848 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
849 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
850 getX86RegNum(MI.getOperand(CurOp).getReg()));
855 if (!Desc->isVariadic() && CurOp != NumOps) {
857 errs() << "Cannot encode all operands of: " << MI << "\n";
863 // Adapt the Emitter / CodeEmitter interfaces to MCCodeEmitter.
865 // FIXME: This is a total hack designed to allow work on llvm-mc to proceed
866 // without being blocked on various cleanups needed to support a clean interface
867 // to instruction encoding.
871 #include "llvm/DerivedTypes.h"
874 class MCSingleInstructionCodeEmitter : public MachineCodeEmitter {
878 MCSingleInstructionCodeEmitter() { reset(); }
882 BufferEnd = array_endof(Data);
887 return StringRef(reinterpret_cast<char*>(BufferBegin),
888 CurBufferPtr - BufferBegin);
891 virtual void startFunction(MachineFunction &F) {}
892 virtual bool finishFunction(MachineFunction &F) { return false; }
893 virtual void emitLabel(uint64_t LabelID) {}
894 virtual void StartMachineBasicBlock(MachineBasicBlock *MBB) {}
895 virtual bool earlyResolveAddresses() const { return false; }
896 virtual void addRelocation(const MachineRelocation &MR) { }
897 virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const {
900 virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const {
903 virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const {
906 virtual uintptr_t getLabelAddress(uint64_t LabelID) const {
909 virtual void setModuleInfo(MachineModuleInfo* Info) {}
912 class X86MCCodeEmitter : public MCCodeEmitter {
913 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
914 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
917 X86TargetMachine &TM;
918 llvm::Function *DummyF;
920 mutable llvm::MachineFunction *DummyMF;
921 llvm::MachineBasicBlock *DummyMBB;
923 MCSingleInstructionCodeEmitter *InstrEmitter;
924 Emitter<MachineCodeEmitter> *Emit;
927 X86MCCodeEmitter(X86TargetMachine &_TM) : TM(_TM) {
928 // Verily, thou shouldst avert thine eyes.
929 const llvm::FunctionType *FTy =
930 FunctionType::get(llvm::Type::getVoidTy(getGlobalContext()), false);
931 DummyF = Function::Create(FTy, GlobalValue::InternalLinkage);
932 DummyTD = new TargetData("");
933 DummyMF = new MachineFunction(DummyF, TM);
934 DummyMBB = DummyMF->CreateMachineBasicBlock();
936 InstrEmitter = new MCSingleInstructionCodeEmitter();
937 Emit = new Emitter<MachineCodeEmitter>(TM, *InstrEmitter,
941 ~X86MCCodeEmitter() {
948 bool AddRegToInstr(const MCInst &MI, MachineInstr *Instr,
949 unsigned Start) const {
950 if (Start + 1 > MI.getNumOperands())
953 const MCOperand &Op = MI.getOperand(Start);
954 if (!Op.isReg()) return false;
956 Instr->addOperand(MachineOperand::CreateReg(Op.getReg(), false));
960 bool AddImmToInstr(const MCInst &MI, MachineInstr *Instr,
961 unsigned Start) const {
962 if (Start + 1 > MI.getNumOperands())
965 const MCOperand &Op = MI.getOperand(Start);
967 Instr->addOperand(MachineOperand::CreateImm(Op.getImm()));
973 const MCExpr *Expr = Op.getExpr();
974 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
975 Instr->addOperand(MachineOperand::CreateImm(CE->getValue()));
979 // FIXME: Relocation / fixup.
980 Instr->addOperand(MachineOperand::CreateImm(0));
984 bool AddLMemToInstr(const MCInst &MI, MachineInstr *Instr,
985 unsigned Start) const {
986 return (AddRegToInstr(MI, Instr, Start + 0) &&
987 AddImmToInstr(MI, Instr, Start + 1) &&
988 AddRegToInstr(MI, Instr, Start + 2) &&
989 AddImmToInstr(MI, Instr, Start + 3));
992 bool AddMemToInstr(const MCInst &MI, MachineInstr *Instr,
993 unsigned Start) const {
994 return (AddRegToInstr(MI, Instr, Start + 0) &&
995 AddImmToInstr(MI, Instr, Start + 1) &&
996 AddRegToInstr(MI, Instr, Start + 2) &&
997 AddImmToInstr(MI, Instr, Start + 3) &&
998 AddRegToInstr(MI, Instr, Start + 4));
1001 void EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
1004 // Convert the MCInst to a MachineInstr so we can (ab)use the regular
1006 const X86InstrInfo &II = *TM.getInstrInfo();
1007 const TargetInstrDesc &Desc = II.get(MI.getOpcode());
1008 MachineInstr *Instr = DummyMF->CreateMachineInstr(Desc, DebugLoc());
1009 DummyMBB->push_back(Instr);
1011 unsigned Opcode = MI.getOpcode();
1012 unsigned NumOps = MI.getNumOperands();
1014 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1) {
1015 Instr->addOperand(MachineOperand::CreateReg(0, false));
1017 } else if (NumOps > 2 &&
1018 Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
1019 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
1023 switch (Desc.TSFlags & X86II::FormMask) {
1024 case X86II::MRMDestReg:
1025 case X86II::MRMSrcReg:
1026 // Matching doesn't fill this in completely, we have to choose operand 0
1027 // for a tied register.
1028 OK &= AddRegToInstr(MI, Instr, 0); CurOp++;
1029 OK &= AddRegToInstr(MI, Instr, CurOp++);
1031 OK &= AddImmToInstr(MI, Instr, CurOp);
1035 if (CurOp < NumOps) {
1036 // Hack to make branches work.
1037 if (!(Desc.TSFlags & X86II::ImmMask) &&
1038 MI.getOperand(0).isExpr() &&
1039 isa<MCSymbolRefExpr>(MI.getOperand(0).getExpr()))
1040 Instr->addOperand(MachineOperand::CreateMBB(DummyMBB));
1042 OK &= AddImmToInstr(MI, Instr, CurOp);
1046 case X86II::AddRegFrm:
1047 OK &= AddRegToInstr(MI, Instr, CurOp++);
1049 OK &= AddImmToInstr(MI, Instr, CurOp);
1052 case X86II::MRM0r: case X86II::MRM1r:
1053 case X86II::MRM2r: case X86II::MRM3r:
1054 case X86II::MRM4r: case X86II::MRM5r:
1055 case X86II::MRM6r: case X86II::MRM7r:
1056 // Matching doesn't fill this in completely, we have to choose operand 0
1057 // for a tied register.
1058 OK &= AddRegToInstr(MI, Instr, 0); CurOp++;
1060 OK &= AddImmToInstr(MI, Instr, CurOp);
1063 case X86II::MRM0m: case X86II::MRM1m:
1064 case X86II::MRM2m: case X86II::MRM3m:
1065 case X86II::MRM4m: case X86II::MRM5m:
1066 case X86II::MRM6m: case X86II::MRM7m:
1067 OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
1069 OK &= AddImmToInstr(MI, Instr, CurOp);
1072 case X86II::MRMSrcMem:
1073 OK &= AddRegToInstr(MI, Instr, CurOp++);
1074 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
1075 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
1076 OK &= AddLMemToInstr(MI, Instr, CurOp);
1078 OK &= AddMemToInstr(MI, Instr, CurOp);
1081 case X86II::MRMDestMem:
1082 OK &= AddMemToInstr(MI, Instr, CurOp); CurOp += 5;
1083 OK &= AddRegToInstr(MI, Instr, CurOp);
1087 case X86II::MRMInitReg:
1094 errs() << "couldn't convert inst '";
1096 errs() << "' to machine instr:\n";
1100 InstrEmitter->reset();
1102 Emit->emitInstruction(*Instr, &Desc);
1103 OS << InstrEmitter->str();
1105 Instr->eraseFromParent();
1110 // Ok, now you can look.
1111 MCCodeEmitter *llvm::createX86MCCodeEmitter(const Target &,
1112 TargetMachine &TM) {
1113 return new X86MCCodeEmitter(static_cast<X86TargetMachine&>(TM));