1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #include "X86TargetMachine.h"
16 #include "X86Relocations.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/CodeGen/MachineCodeEmitter.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Function.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/Target/TargetOptions.h"
32 NumEmitted("x86-emitter", "Number of machine instructions emitted");
36 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
37 const X86InstrInfo *II;
39 MachineCodeEmitter &MCE;
41 explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
42 : II(0), TM(tm), MCE(mce) {}
43 Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
44 const X86InstrInfo& ii)
45 : II(&ii), TM(tm), MCE(mce) {}
47 bool runOnMachineFunction(MachineFunction &MF);
49 virtual const char *getPassName() const {
50 return "X86 Machine Code Emitter";
53 void emitInstruction(const MachineInstr &MI);
56 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
57 void emitPCRelativeValue(unsigned Address);
58 void emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall);
59 void emitGlobalAddressForPtr(GlobalValue *GV, int Disp = 0);
60 void emitExternalSymbolAddress(const char *ES, bool isPCRelative);
62 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal);
64 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
65 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
66 void emitConstant(unsigned Val, unsigned Size);
68 void emitMemModRMByte(const MachineInstr &MI,
69 unsigned Op, unsigned RegOpcodeField);
74 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
75 /// to the specified MCE object.
76 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
77 MachineCodeEmitter &MCE) {
78 return new Emitter(TM, MCE);
81 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
82 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
83 MF.getTarget().getRelocationModel() != Reloc::Static) &&
84 "JIT relocation model must be set to static or default!");
85 II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
88 MCE.startFunction(MF);
89 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
91 MCE.StartMachineBasicBlock(MBB);
92 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
96 } while (MCE.finishFunction(MF));
101 /// emitPCRelativeValue - Emit a 32-bit PC relative address.
103 void Emitter::emitPCRelativeValue(unsigned Address) {
104 MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
107 /// emitPCRelativeBlockAddress - This method keeps track of the information
108 /// necessary to resolve the address of this block later and emits a dummy
111 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
112 // Remember where this reference was and where it is to so we can
113 // deal with it later.
114 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
115 X86::reloc_pcrel_word, MBB));
119 /// emitGlobalAddressForCall - Emit the specified address to the code stream
120 /// assuming this is part of a function call, which is PC relative.
122 void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool isTailCall) {
123 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
124 X86::reloc_pcrel_word, GV, 0,
125 !isTailCall /*Doesn'tNeedStub*/));
129 /// emitGlobalAddress - Emit the specified address to the code stream assuming
130 /// this is part of a "take the address of a global" instruction, which is not
133 void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, int Disp /* = 0 */) {
134 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
135 X86::reloc_absolute_word, GV));
136 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
139 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
140 /// be emitted to the current location in the function, and allow it to be PC
142 void Emitter::emitExternalSymbolAddress(const char *ES, bool isPCRelative) {
143 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
144 isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES));
148 /// N86 namespace - Native X86 Register numbers... used by X86 backend.
152 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
157 // getX86RegNum - This function maps LLVM register identifiers to their X86
158 // specific numbering, which is used in various places encoding instructions.
160 static unsigned getX86RegNum(unsigned RegNo) {
162 case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
163 case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
164 case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
165 case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
166 case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
167 case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
168 case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
169 case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
171 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
172 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
173 return RegNo-X86::ST0;
175 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
176 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
177 return RegNo-X86::XMM0;
180 assert(MRegisterInfo::isVirtualRegister(RegNo) &&
181 "Unknown physical register!");
182 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
187 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
189 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
190 return RM | (RegOpcode << 3) | (Mod << 6);
193 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
194 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
197 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
198 // SIB byte is in the same format as the ModRMByte...
199 MCE.emitByte(ModRMByte(SS, Index, Base));
202 void Emitter::emitConstant(unsigned Val, unsigned Size) {
203 // Output the constant in little endian byte order...
204 for (unsigned i = 0; i != Size; ++i) {
205 MCE.emitByte(Val & 255);
210 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
211 /// sign-extended field.
212 static bool isDisp8(int Value) {
213 return Value == (signed char)Value;
216 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
218 // If this is a simple integer displacement that doesn't require a relocation,
221 emitConstant(DispVal, 4);
225 // Otherwise, this is something that requires a relocation. Emit it as such
227 if (RelocOp->isGlobalAddress()) {
228 emitGlobalAddressForPtr(RelocOp->getGlobal(), RelocOp->getOffset());
230 assert(0 && "Unknown value to relocate!");
234 void Emitter::emitMemModRMByte(const MachineInstr &MI,
235 unsigned Op, unsigned RegOpcodeField) {
236 const MachineOperand &Op3 = MI.getOperand(Op+3);
238 const MachineOperand *DispForReloc = 0;
240 // Figure out what sort of displacement we have to handle here.
241 if (Op3.isGlobalAddress()) {
243 } else if (Op3.isConstantPoolIndex()) {
244 DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
245 DispVal += Op3.getOffset();
246 } else if (Op3.isJumpTableIndex()) {
247 DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
249 DispVal = Op3.getImmedValue();
252 const MachineOperand &Base = MI.getOperand(Op);
253 const MachineOperand &Scale = MI.getOperand(Op+1);
254 const MachineOperand &IndexReg = MI.getOperand(Op+2);
256 unsigned BaseReg = Base.getReg();
258 // Is a SIB byte needed?
259 if (IndexReg.getReg() == 0 && BaseReg != X86::ESP) {
260 if (BaseReg == 0) { // Just a displacement?
261 // Emit special case [disp32] encoding
262 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
264 emitDisplacementField(DispForReloc, DispVal);
266 unsigned BaseRegNo = getX86RegNum(BaseReg);
267 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
268 // Emit simple indirect register encoding... [EAX] f.e.
269 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
270 } else if (!DispForReloc && isDisp8(DispVal)) {
271 // Emit the disp8 encoding... [REG+disp8]
272 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
273 emitConstant(DispVal, 1);
275 // Emit the most general non-SIB encoding: [REG+disp32]
276 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
277 emitDisplacementField(DispForReloc, DispVal);
281 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
282 assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
284 bool ForceDisp32 = false;
285 bool ForceDisp8 = false;
287 // If there is no base register, we emit the special case SIB byte with
288 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
289 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
291 } else if (DispForReloc) {
292 // Emit the normal disp32 encoding.
293 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
295 } else if (DispVal == 0 && BaseReg != X86::EBP) {
296 // Emit no displacement ModR/M byte
297 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
298 } else if (isDisp8(DispVal)) {
299 // Emit the disp8 encoding...
300 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
301 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
303 // Emit the normal disp32 encoding...
304 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
307 // Calculate what the SS field value should be...
308 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
309 unsigned SS = SSTable[Scale.getImmedValue()];
312 // Handle the SIB byte for the case where there is no base. The
313 // displacement has already been output.
314 assert(IndexReg.getReg() && "Index register must be specified!");
315 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
317 unsigned BaseRegNo = getX86RegNum(BaseReg);
319 if (IndexReg.getReg())
320 IndexRegNo = getX86RegNum(IndexReg.getReg());
322 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
323 emitSIBByte(SS, IndexRegNo, BaseRegNo);
326 // Do we need to output a displacement?
328 emitConstant(DispVal, 1);
329 } else if (DispVal != 0 || ForceDisp32) {
330 emitDisplacementField(DispForReloc, DispVal);
335 static unsigned sizeOfImm(const TargetInstrDescriptor &Desc) {
336 switch (Desc.TSFlags & X86II::ImmMask) {
337 case X86II::Imm8: return 1;
338 case X86II::Imm16: return 2;
339 case X86II::Imm32: return 4;
340 default: assert(0 && "Immediate size not set!");
345 void Emitter::emitInstruction(const MachineInstr &MI) {
346 NumEmitted++; // Keep track of the # of mi's emitted
348 unsigned Opcode = MI.getOpcode();
349 const TargetInstrDescriptor &Desc = II->get(Opcode);
351 // Emit the repeat opcode prefix as needed.
352 if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
354 // Emit the operand size opcode prefix as needed.
355 if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);
357 switch (Desc.TSFlags & X86II::Op0Mask) {
359 MCE.emitByte(0x0F); // Two-byte opcode prefix
361 case X86II::REP: break; // already handled.
362 case X86II::XS: // F3 0F
366 case X86II::XD: // F2 0F
370 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
371 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
373 (((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
374 >> X86II::Op0Shift));
375 break; // Two-byte opcode prefix
376 default: assert(0 && "Invalid prefix!");
377 case 0: break; // No prefix!
380 unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
381 switch (Desc.TSFlags & X86II::FormMask) {
382 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
387 assert(0 && "psuedo instructions should be removed before code emission");
388 case TargetInstrInfo::INLINEASM:
389 std::cerr << "JIT does not support inline asm!\n";
391 case X86::IMPLICIT_USE:
392 case X86::IMPLICIT_DEF:
393 case X86::IMPLICIT_DEF_GR8:
394 case X86::IMPLICIT_DEF_GR16:
395 case X86::IMPLICIT_DEF_GR32:
396 case X86::IMPLICIT_DEF_FR32:
397 case X86::IMPLICIT_DEF_FR64:
398 case X86::IMPLICIT_DEF_VR64:
399 case X86::IMPLICIT_DEF_VR128:
400 case X86::FP_REG_KILL:
407 MCE.emitByte(BaseOpcode);
408 if (Desc.numOperands == 1) {
409 const MachineOperand &MO = MI.getOperand(0);
410 if (MO.isMachineBasicBlock()) {
411 emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
412 } else if (MO.isGlobalAddress()) {
413 bool isTailCall = Opcode == X86::TAILJMPd ||
414 Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
415 emitGlobalAddressForCall(MO.getGlobal(), isTailCall);
416 } else if (MO.isExternalSymbol()) {
417 emitExternalSymbolAddress(MO.getSymbolName(), true);
418 } else if (MO.isImmediate()) {
419 emitConstant(MO.getImmedValue(), sizeOfImm(Desc));
421 assert(0 && "Unknown RawFrm operand!");
426 case X86II::AddRegFrm:
427 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
428 if (MI.getNumOperands() == 2) {
429 const MachineOperand &MO1 = MI.getOperand(1);
430 if (MO1.isGlobalAddress()) {
431 assert(sizeOfImm(Desc) == 4 &&
432 "Don't know how to emit non-pointer values!");
433 emitGlobalAddressForPtr(MO1.getGlobal(), MO1.getOffset());
434 } else if (MO1.isExternalSymbol()) {
435 assert(sizeOfImm(Desc) == 4 &&
436 "Don't know how to emit non-pointer values!");
437 emitExternalSymbolAddress(MO1.getSymbolName(), false);
438 } else if (MO1.isJumpTableIndex()) {
439 assert(sizeOfImm(Desc) == 4 &&
440 "Don't know how to emit non-pointer values!");
441 emitConstant(MCE.getJumpTableEntryAddress(MO1.getJumpTableIndex()), 4);
443 emitConstant(MO1.getImmedValue(), sizeOfImm(Desc));
448 case X86II::MRMDestReg: {
449 MCE.emitByte(BaseOpcode);
450 emitRegModRMByte(MI.getOperand(0).getReg(),
451 getX86RegNum(MI.getOperand(1).getReg()));
452 if (MI.getNumOperands() == 3)
453 emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
456 case X86II::MRMDestMem:
457 MCE.emitByte(BaseOpcode);
458 emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
459 if (MI.getNumOperands() == 6)
460 emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
463 case X86II::MRMSrcReg:
464 MCE.emitByte(BaseOpcode);
465 emitRegModRMByte(MI.getOperand(1).getReg(),
466 getX86RegNum(MI.getOperand(0).getReg()));
467 if (MI.getNumOperands() == 3)
468 emitConstant(MI.getOperand(2).getImmedValue(), sizeOfImm(Desc));
471 case X86II::MRMSrcMem:
472 MCE.emitByte(BaseOpcode);
473 emitMemModRMByte(MI, 1, getX86RegNum(MI.getOperand(0).getReg()));
474 if (MI.getNumOperands() == 2+4)
475 emitConstant(MI.getOperand(5).getImmedValue(), sizeOfImm(Desc));
478 case X86II::MRM0r: case X86II::MRM1r:
479 case X86II::MRM2r: case X86II::MRM3r:
480 case X86II::MRM4r: case X86II::MRM5r:
481 case X86II::MRM6r: case X86II::MRM7r:
482 MCE.emitByte(BaseOpcode);
483 emitRegModRMByte(MI.getOperand(0).getReg(),
484 (Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
486 if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
487 emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(),
492 case X86II::MRM0m: case X86II::MRM1m:
493 case X86II::MRM2m: case X86II::MRM3m:
494 case X86II::MRM4m: case X86II::MRM5m:
495 case X86II::MRM6m: case X86II::MRM7m:
496 MCE.emitByte(BaseOpcode);
497 emitMemModRMByte(MI, 0, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m);
499 if (MI.getNumOperands() == 5) {
500 if (MI.getOperand(4).isImmediate())
501 emitConstant(MI.getOperand(4).getImmedValue(), sizeOfImm(Desc));
502 else if (MI.getOperand(4).isGlobalAddress())
503 emitGlobalAddressForPtr(MI.getOperand(4).getGlobal(),
504 MI.getOperand(4).getOffset());
505 else if (MI.getOperand(4).isJumpTableIndex())
506 emitConstant(MCE.getJumpTableEntryAddress(MI.getOperand(4)
507 .getJumpTableIndex()), 4);
509 assert(0 && "Unknown operand!");
513 case X86II::MRMInitReg:
514 MCE.emitByte(BaseOpcode);
515 emitRegModRMByte(MI.getOperand(0).getReg(),
516 getX86RegNum(MI.getOperand(0).getReg()));