1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/Function.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Target/TargetOptions.h"
35 STATISTIC(NumEmitted, "Number of machine instructions emitted");
38 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
39 const X86InstrInfo *II;
42 MachineCodeEmitter &MCE;
43 intptr_t PICBaseOffset;
48 explicit Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
49 : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
50 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
51 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
52 Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce,
53 const X86InstrInfo &ii, const TargetData &td, bool is64)
54 : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
55 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
56 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
58 bool runOnMachineFunction(MachineFunction &MF);
60 virtual const char *getPassName() const {
61 return "X86 Machine Code Emitter";
64 void emitInstruction(const MachineInstr &MI,
65 const TargetInstrDesc *Desc);
67 void getAnalysisUsage(AnalysisUsage &AU) const {
68 AU.addRequired<MachineModuleInfo>();
69 MachineFunctionPass::getAnalysisUsage(AU);
73 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
74 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
75 int Disp = 0, intptr_t PCAdj = 0,
76 bool NeedStub = false, bool IsLazy = false);
77 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
78 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
80 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
83 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
86 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
87 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
88 void emitConstant(uint64_t Val, unsigned Size);
90 void emitMemModRMByte(const MachineInstr &MI,
91 unsigned Op, unsigned RegOpcodeField,
94 unsigned getX86RegNum(unsigned RegNo) const;
96 bool gvNeedsLazyPtr(const GlobalValue *GV);
101 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
102 /// to the specified MCE object.
103 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
104 MachineCodeEmitter &MCE) {
105 return new Emitter(TM, MCE);
108 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
109 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
110 MF.getTarget().getRelocationModel() != Reloc::Static) &&
111 "JIT relocation model must be set to static or default!");
113 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
115 II = TM.getInstrInfo();
116 TD = TM.getTargetData();
117 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
118 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
121 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
122 MCE.startFunction(MF);
123 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
125 MCE.StartMachineBasicBlock(MBB);
126 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
128 const TargetInstrDesc &Desc = I->getDesc();
129 emitInstruction(*I, &Desc);
130 // MOVPC32r is basically a call plus a pop instruction.
131 if (Desc.getOpcode() == X86::MOVPC32r)
132 emitInstruction(*I, &II->get(X86::POP32r));
133 NumEmitted++; // Keep track of the # of mi's emitted
136 } while (MCE.finishFunction(MF));
141 /// emitPCRelativeBlockAddress - This method keeps track of the information
142 /// necessary to resolve the address of this block later and emits a dummy
145 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
146 // Remember where this reference was and where it is to so we can
147 // deal with it later.
148 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
149 X86::reloc_pcrel_word, MBB));
153 /// emitGlobalAddress - Emit the specified address to the code stream assuming
154 /// this is part of a "take the address of a global" instruction.
156 void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
157 int Disp /* = 0 */, intptr_t PCAdj /* = 0 */,
158 bool NeedStub /* = false */,
159 bool isLazy /* = false */) {
160 intptr_t RelocCST = 0;
161 if (Reloc == X86::reloc_picrel_word)
162 RelocCST = PICBaseOffset;
163 else if (Reloc == X86::reloc_pcrel_word)
165 MachineRelocation MR = isLazy
166 ? MachineRelocation::getGVLazyPtr(MCE.getCurrentPCOffset(), Reloc,
167 GV, RelocCST, NeedStub)
168 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
169 GV, RelocCST, NeedStub);
170 MCE.addRelocation(MR);
171 if (Reloc == X86::reloc_absolute_dword)
173 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
176 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
177 /// be emitted to the current location in the function, and allow it to be PC
179 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
180 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
181 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
182 Reloc, ES, RelocCST));
183 if (Reloc == X86::reloc_absolute_dword)
188 /// emitConstPoolAddress - Arrange for the address of an constant pool
189 /// to be emitted to the current location in the function, and allow it to be PC
191 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
193 intptr_t PCAdj /* = 0 */) {
194 intptr_t RelocCST = 0;
195 if (Reloc == X86::reloc_picrel_word)
196 RelocCST = PICBaseOffset;
197 else if (Reloc == X86::reloc_pcrel_word)
199 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
200 Reloc, CPI, RelocCST));
201 if (Reloc == X86::reloc_absolute_dword)
203 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
206 /// emitJumpTableAddress - Arrange for the address of a jump table to
207 /// be emitted to the current location in the function, and allow it to be PC
209 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
210 intptr_t PCAdj /* = 0 */) {
211 intptr_t RelocCST = 0;
212 if (Reloc == X86::reloc_picrel_word)
213 RelocCST = PICBaseOffset;
214 else if (Reloc == X86::reloc_pcrel_word)
216 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
217 Reloc, JTI, RelocCST));
218 if (Reloc == X86::reloc_absolute_dword)
220 MCE.emitWordLE(0); // The relocated value will be added to the displacement
223 unsigned Emitter::getX86RegNum(unsigned RegNo) const {
224 return II->getRegisterInfo().getX86RegNum(RegNo);
227 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
229 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
230 return RM | (RegOpcode << 3) | (Mod << 6);
233 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
234 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
237 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
238 // SIB byte is in the same format as the ModRMByte...
239 MCE.emitByte(ModRMByte(SS, Index, Base));
242 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
243 // Output the constant in little endian byte order...
244 for (unsigned i = 0; i != Size; ++i) {
245 MCE.emitByte(Val & 255);
250 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
251 /// sign-extended field.
252 static bool isDisp8(int Value) {
253 return Value == (signed char)Value;
256 bool Emitter::gvNeedsLazyPtr(const GlobalValue *GV) {
257 return !Is64BitMode &&
258 TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
261 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
262 int DispVal, intptr_t PCAdj) {
263 // If this is a simple integer displacement that doesn't require a relocation,
266 emitConstant(DispVal, 4);
270 // Otherwise, this is something that requires a relocation. Emit it as such
272 if (RelocOp->isGlobalAddress()) {
273 // In 64-bit static small code model, we could potentially emit absolute.
274 // But it's probably not beneficial.
275 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
276 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
277 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
278 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
279 bool NeedStub = isa<Function>(RelocOp->getGlobal());
280 bool isLazy = gvNeedsLazyPtr(RelocOp->getGlobal());
281 emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
282 PCAdj, NeedStub, isLazy);
283 } else if (RelocOp->isConstantPoolIndex()) {
284 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
285 emitConstPoolAddress(RelocOp->getIndex(), rt,
286 RelocOp->getOffset(), PCAdj);
287 } else if (RelocOp->isJumpTableIndex()) {
288 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
289 emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
291 assert(0 && "Unknown value to relocate!");
295 void Emitter::emitMemModRMByte(const MachineInstr &MI,
296 unsigned Op, unsigned RegOpcodeField,
298 const MachineOperand &Op3 = MI.getOperand(Op+3);
300 const MachineOperand *DispForReloc = 0;
302 // Figure out what sort of displacement we have to handle here.
303 if (Op3.isGlobalAddress()) {
305 } else if (Op3.isConstantPoolIndex()) {
306 if (Is64BitMode || IsPIC) {
309 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
310 DispVal += Op3.getOffset();
312 } else if (Op3.isJumpTableIndex()) {
313 if (Is64BitMode || IsPIC) {
316 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
319 DispVal = Op3.getImm();
322 const MachineOperand &Base = MI.getOperand(Op);
323 const MachineOperand &Scale = MI.getOperand(Op+1);
324 const MachineOperand &IndexReg = MI.getOperand(Op+2);
326 unsigned BaseReg = Base.getReg();
328 // Is a SIB byte needed?
329 if (IndexReg.getReg() == 0 &&
330 (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
331 if (BaseReg == 0) { // Just a displacement?
332 // Emit special case [disp32] encoding
333 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
335 emitDisplacementField(DispForReloc, DispVal, PCAdj);
337 unsigned BaseRegNo = getX86RegNum(BaseReg);
338 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
339 // Emit simple indirect register encoding... [EAX] f.e.
340 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
341 } else if (!DispForReloc && isDisp8(DispVal)) {
342 // Emit the disp8 encoding... [REG+disp8]
343 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
344 emitConstant(DispVal, 1);
346 // Emit the most general non-SIB encoding: [REG+disp32]
347 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
348 emitDisplacementField(DispForReloc, DispVal, PCAdj);
352 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
353 assert(IndexReg.getReg() != X86::ESP &&
354 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
356 bool ForceDisp32 = false;
357 bool ForceDisp8 = false;
359 // If there is no base register, we emit the special case SIB byte with
360 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
361 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
363 } else if (DispForReloc) {
364 // Emit the normal disp32 encoding.
365 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
367 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
368 // Emit no displacement ModR/M byte
369 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
370 } else if (isDisp8(DispVal)) {
371 // Emit the disp8 encoding...
372 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
373 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
375 // Emit the normal disp32 encoding...
376 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
379 // Calculate what the SS field value should be...
380 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
381 unsigned SS = SSTable[Scale.getImm()];
384 // Handle the SIB byte for the case where there is no base. The
385 // displacement has already been output.
386 assert(IndexReg.getReg() && "Index register must be specified!");
387 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
389 unsigned BaseRegNo = getX86RegNum(BaseReg);
391 if (IndexReg.getReg())
392 IndexRegNo = getX86RegNum(IndexReg.getReg());
394 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
395 emitSIBByte(SS, IndexRegNo, BaseRegNo);
398 // Do we need to output a displacement?
400 emitConstant(DispVal, 1);
401 } else if (DispVal != 0 || ForceDisp32) {
402 emitDisplacementField(DispForReloc, DispVal, PCAdj);
407 void Emitter::emitInstruction(const MachineInstr &MI,
408 const TargetInstrDesc *Desc) {
411 unsigned Opcode = Desc->Opcode;
413 // Emit the lock opcode prefix as needed.
414 if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
416 // Emit the repeat opcode prefix as needed.
417 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
419 // Emit the operand size opcode prefix as needed.
420 if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
422 // Emit the address size opcode prefix as needed.
423 if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
425 bool Need0FPrefix = false;
426 switch (Desc->TSFlags & X86II::Op0Mask) {
427 case X86II::TB: // Two-byte opcode prefix
428 case X86II::T8: // 0F 38
429 case X86II::TA: // 0F 3A
432 case X86II::REP: break; // already handled.
433 case X86II::XS: // F3 0F
437 case X86II::XD: // F2 0F
441 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
442 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
444 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
445 >> X86II::Op0Shift));
446 break; // Two-byte opcode prefix
447 default: assert(0 && "Invalid prefix!");
448 case 0: break; // No prefix!
453 unsigned REX = X86InstrInfo::determineREX(MI);
455 MCE.emitByte(0x40 | REX);
458 // 0x0F escape code must be emitted just before the opcode.
462 switch (Desc->TSFlags & X86II::Op0Mask) {
463 case X86II::T8: // 0F 38
466 case X86II::TA: // 0F 3A
471 // If this is a two-address instruction, skip one of the register operands.
472 unsigned NumOps = Desc->getNumOperands();
474 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
476 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
477 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
480 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
481 switch (Desc->TSFlags & X86II::FormMask) {
482 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
484 // Remember the current PC offset, this is the PIC relocation
488 assert(0 && "psuedo instructions should be removed before code emission");
490 case TargetInstrInfo::INLINEASM:
491 assert(0 && "JIT does not support inline asm!\n");
493 case TargetInstrInfo::LABEL:
494 MCE.emitLabel(MI.getOperand(0).getImm());
496 case TargetInstrInfo::IMPLICIT_DEF:
497 case TargetInstrInfo::DECLARE:
499 case X86::FP_REG_KILL:
501 case X86::MOVPC32r: {
502 // This emits the "call" portion of this pseudo instruction.
503 MCE.emitByte(BaseOpcode);
504 emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
505 // Remember PIC base.
506 PICBaseOffset = MCE.getCurrentPCOffset();
507 X86JITInfo *JTI = TM.getJITInfo();
508 JTI->setPICBase(MCE.getCurrentPCValue());
515 MCE.emitByte(BaseOpcode);
517 if (CurOp != NumOps) {
518 const MachineOperand &MO = MI.getOperand(CurOp++);
519 if (MO.isMachineBasicBlock()) {
520 emitPCRelativeBlockAddress(MO.getMBB());
521 } else if (MO.isGlobalAddress()) {
522 bool NeedStub = (Is64BitMode && TM.getCodeModel() == CodeModel::Large)
523 || Opcode == X86::TAILJMPd;
524 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
526 } else if (MO.isExternalSymbol()) {
527 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
528 } else if (MO.isImmediate()) {
529 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
531 assert(0 && "Unknown RawFrm operand!");
536 case X86II::AddRegFrm:
537 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
539 if (CurOp != NumOps) {
540 const MachineOperand &MO1 = MI.getOperand(CurOp++);
541 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
542 if (MO1.isImmediate())
543 emitConstant(MO1.getImm(), Size);
545 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
546 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
547 if (Opcode == X86::MOV64ri)
548 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
549 if (MO1.isGlobalAddress()) {
550 bool NeedStub = isa<Function>(MO1.getGlobal());
551 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
552 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
554 } else if (MO1.isExternalSymbol())
555 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
556 else if (MO1.isConstantPoolIndex())
557 emitConstPoolAddress(MO1.getIndex(), rt);
558 else if (MO1.isJumpTableIndex())
559 emitJumpTableAddress(MO1.getIndex(), rt);
564 case X86II::MRMDestReg: {
565 MCE.emitByte(BaseOpcode);
566 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
567 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
570 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
573 case X86II::MRMDestMem: {
574 MCE.emitByte(BaseOpcode);
575 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
578 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
582 case X86II::MRMSrcReg:
583 MCE.emitByte(BaseOpcode);
584 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
585 getX86RegNum(MI.getOperand(CurOp).getReg()));
588 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
591 case X86II::MRMSrcMem: {
592 intptr_t PCAdj = (CurOp+5 != NumOps) ? X86InstrInfo::sizeOfImm(Desc) : 0;
594 MCE.emitByte(BaseOpcode);
595 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
599 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
603 case X86II::MRM0r: case X86II::MRM1r:
604 case X86II::MRM2r: case X86II::MRM3r:
605 case X86II::MRM4r: case X86II::MRM5r:
606 case X86II::MRM6r: case X86II::MRM7r:
607 MCE.emitByte(BaseOpcode);
608 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
609 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
611 if (CurOp != NumOps) {
612 const MachineOperand &MO1 = MI.getOperand(CurOp++);
613 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
614 if (MO1.isImmediate())
615 emitConstant(MO1.getImm(), Size);
617 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
618 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
619 if (Opcode == X86::MOV64ri32)
620 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
621 if (MO1.isGlobalAddress()) {
622 bool NeedStub = isa<Function>(MO1.getGlobal());
623 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
624 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
626 } else if (MO1.isExternalSymbol())
627 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
628 else if (MO1.isConstantPoolIndex())
629 emitConstPoolAddress(MO1.getIndex(), rt);
630 else if (MO1.isJumpTableIndex())
631 emitJumpTableAddress(MO1.getIndex(), rt);
636 case X86II::MRM0m: case X86II::MRM1m:
637 case X86II::MRM2m: case X86II::MRM3m:
638 case X86II::MRM4m: case X86II::MRM5m:
639 case X86II::MRM6m: case X86II::MRM7m: {
640 intptr_t PCAdj = (CurOp+4 != NumOps) ?
641 (MI.getOperand(CurOp+4).isImmediate() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
643 MCE.emitByte(BaseOpcode);
644 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
648 if (CurOp != NumOps) {
649 const MachineOperand &MO = MI.getOperand(CurOp++);
650 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
651 if (MO.isImmediate())
652 emitConstant(MO.getImm(), Size);
654 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
655 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
656 if (Opcode == X86::MOV64mi32)
657 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
658 if (MO.isGlobalAddress()) {
659 bool NeedStub = isa<Function>(MO.getGlobal());
660 bool isLazy = gvNeedsLazyPtr(MO.getGlobal());
661 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
663 } else if (MO.isExternalSymbol())
664 emitExternalSymbolAddress(MO.getSymbolName(), rt);
665 else if (MO.isConstantPoolIndex())
666 emitConstPoolAddress(MO.getIndex(), rt);
667 else if (MO.isJumpTableIndex())
668 emitJumpTableAddress(MO.getIndex(), rt);
674 case X86II::MRMInitReg:
675 MCE.emitByte(BaseOpcode);
676 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
677 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
678 getX86RegNum(MI.getOperand(CurOp).getReg()));
683 if (!Desc->isVariadic() && CurOp != NumOps) {
684 cerr << "Cannot encode: ";