1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/JITCodeEmitter.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Target/TargetOptions.h"
36 STATISTIC(NumEmitted, "Number of machine instructions emitted");
39 template<class CodeEmitter>
40 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
41 const X86InstrInfo *II;
45 intptr_t PICBaseOffset;
50 explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
51 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
52 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
53 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
54 Emitter(X86TargetMachine &tm, CodeEmitter &mce,
55 const X86InstrInfo &ii, const TargetData &td, bool is64)
56 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
57 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
58 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
60 bool runOnMachineFunction(MachineFunction &MF);
62 virtual const char *getPassName() const {
63 return "X86 Machine Code Emitter";
66 void emitInstruction(const MachineInstr &MI,
67 const TargetInstrDesc *Desc);
69 void getAnalysisUsage(AnalysisUsage &AU) const {
70 AU.addRequired<MachineModuleInfo>();
71 MachineFunctionPass::getAnalysisUsage(AU);
75 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
76 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
77 intptr_t Disp = 0, intptr_t PCAdj = 0,
78 bool NeedStub = false, bool Indirect = false);
79 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
80 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
82 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
85 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
88 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
89 void emitRegModRMByte(unsigned RegOpcodeField);
90 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
91 void emitConstant(uint64_t Val, unsigned Size);
93 void emitMemModRMByte(const MachineInstr &MI,
94 unsigned Op, unsigned RegOpcodeField,
97 unsigned getX86RegNum(unsigned RegNo) const;
99 bool gvNeedsNonLazyPtr(const GlobalValue *GV);
102 template<class CodeEmitter>
103 char Emitter<CodeEmitter>::ID = 0;
106 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
107 /// to the specified templated MachineCodeEmitter object.
111 FunctionPass *createX86CodeEmitterPass(X86TargetMachine &TM,
112 MachineCodeEmitter &MCE) {
113 return new Emitter<MachineCodeEmitter>(TM, MCE);
115 FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
116 JITCodeEmitter &JCE) {
117 return new Emitter<JITCodeEmitter>(TM, JCE);
120 } // end namespace llvm
122 template<class CodeEmitter>
123 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
125 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
127 II = TM.getInstrInfo();
128 TD = TM.getTargetData();
129 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
130 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
133 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
134 MCE.startFunction(MF);
135 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
137 MCE.StartMachineBasicBlock(MBB);
138 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
140 const TargetInstrDesc &Desc = I->getDesc();
141 emitInstruction(*I, &Desc);
142 // MOVPC32r is basically a call plus a pop instruction.
143 if (Desc.getOpcode() == X86::MOVPC32r)
144 emitInstruction(*I, &II->get(X86::POP32r));
145 NumEmitted++; // Keep track of the # of mi's emitted
148 } while (MCE.finishFunction(MF));
153 /// emitPCRelativeBlockAddress - This method keeps track of the information
154 /// necessary to resolve the address of this block later and emits a dummy
157 template<class CodeEmitter>
158 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
159 // Remember where this reference was and where it is to so we can
160 // deal with it later.
161 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
162 X86::reloc_pcrel_word, MBB));
166 /// emitGlobalAddress - Emit the specified address to the code stream assuming
167 /// this is part of a "take the address of a global" instruction.
169 template<class CodeEmitter>
170 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
171 intptr_t Disp /* = 0 */,
172 intptr_t PCAdj /* = 0 */,
173 bool NeedStub /* = false */,
174 bool Indirect /* = false */) {
175 intptr_t RelocCST = 0;
176 if (Reloc == X86::reloc_picrel_word)
177 RelocCST = PICBaseOffset;
178 else if (Reloc == X86::reloc_pcrel_word)
180 MachineRelocation MR = Indirect
181 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
182 GV, RelocCST, NeedStub)
183 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
184 GV, RelocCST, NeedStub);
185 MCE.addRelocation(MR);
186 // The relocated value will be added to the displacement
187 if (Reloc == X86::reloc_absolute_dword)
188 MCE.emitDWordLE(Disp);
190 MCE.emitWordLE((int32_t)Disp);
193 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
194 /// be emitted to the current location in the function, and allow it to be PC
196 template<class CodeEmitter>
197 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
199 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
200 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
201 Reloc, ES, RelocCST));
202 if (Reloc == X86::reloc_absolute_dword)
208 /// emitConstPoolAddress - Arrange for the address of an constant pool
209 /// to be emitted to the current location in the function, and allow it to be PC
211 template<class CodeEmitter>
212 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
213 intptr_t Disp /* = 0 */,
214 intptr_t PCAdj /* = 0 */) {
215 intptr_t RelocCST = 0;
216 if (Reloc == X86::reloc_picrel_word)
217 RelocCST = PICBaseOffset;
218 else if (Reloc == X86::reloc_pcrel_word)
220 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
221 Reloc, CPI, RelocCST));
222 // The relocated value will be added to the displacement
223 if (Reloc == X86::reloc_absolute_dword)
224 MCE.emitDWordLE(Disp);
226 MCE.emitWordLE((int32_t)Disp);
229 /// emitJumpTableAddress - Arrange for the address of a jump table to
230 /// be emitted to the current location in the function, and allow it to be PC
232 template<class CodeEmitter>
233 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
234 intptr_t PCAdj /* = 0 */) {
235 intptr_t RelocCST = 0;
236 if (Reloc == X86::reloc_picrel_word)
237 RelocCST = PICBaseOffset;
238 else if (Reloc == X86::reloc_pcrel_word)
240 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
241 Reloc, JTI, RelocCST));
242 // The relocated value will be added to the displacement
243 if (Reloc == X86::reloc_absolute_dword)
249 template<class CodeEmitter>
250 unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
251 return II->getRegisterInfo().getX86RegNum(RegNo);
254 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
256 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
257 return RM | (RegOpcode << 3) | (Mod << 6);
260 template<class CodeEmitter>
261 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
262 unsigned RegOpcodeFld){
263 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
266 template<class CodeEmitter>
267 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
268 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
271 template<class CodeEmitter>
272 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
275 // SIB byte is in the same format as the ModRMByte...
276 MCE.emitByte(ModRMByte(SS, Index, Base));
279 template<class CodeEmitter>
280 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
281 // Output the constant in little endian byte order...
282 for (unsigned i = 0; i != Size; ++i) {
283 MCE.emitByte(Val & 255);
288 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
289 /// sign-extended field.
290 static bool isDisp8(int Value) {
291 return Value == (signed char)Value;
294 template<class CodeEmitter>
295 bool Emitter<CodeEmitter>::gvNeedsNonLazyPtr(const GlobalValue *GV) {
296 // For Darwin, simulate the linktime GOT by using the same non-lazy-pointer
297 // mechanism as 32-bit mode.
298 return (!Is64BitMode || TM.getSubtarget<X86Subtarget>().isTargetDarwin()) &&
299 TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
302 template<class CodeEmitter>
303 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
304 int DispVal, intptr_t PCAdj) {
305 // If this is a simple integer displacement that doesn't require a relocation,
308 emitConstant(DispVal, 4);
312 // Otherwise, this is something that requires a relocation. Emit it as such
314 if (RelocOp->isGlobal()) {
315 // In 64-bit static small code model, we could potentially emit absolute.
316 // But it's probably not beneficial.
317 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
318 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
319 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
320 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
321 bool NeedStub = isa<Function>(RelocOp->getGlobal());
322 bool Indirect = gvNeedsNonLazyPtr(RelocOp->getGlobal());
323 emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
324 PCAdj, NeedStub, Indirect);
325 } else if (RelocOp->isCPI()) {
326 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
327 emitConstPoolAddress(RelocOp->getIndex(), rt,
328 RelocOp->getOffset(), PCAdj);
329 } else if (RelocOp->isJTI()) {
330 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
331 emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
333 assert(0 && "Unknown value to relocate!");
337 template<class CodeEmitter>
338 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
339 unsigned Op, unsigned RegOpcodeField,
341 const MachineOperand &Op3 = MI.getOperand(Op+3);
343 const MachineOperand *DispForReloc = 0;
345 // Figure out what sort of displacement we have to handle here.
346 if (Op3.isGlobal()) {
348 } else if (Op3.isCPI()) {
349 if (Is64BitMode || IsPIC) {
352 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
353 DispVal += Op3.getOffset();
355 } else if (Op3.isJTI()) {
356 if (Is64BitMode || IsPIC) {
359 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
362 DispVal = Op3.getImm();
365 const MachineOperand &Base = MI.getOperand(Op);
366 const MachineOperand &Scale = MI.getOperand(Op+1);
367 const MachineOperand &IndexReg = MI.getOperand(Op+2);
369 unsigned BaseReg = Base.getReg();
371 // Is a SIB byte needed?
372 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
373 IndexReg.getReg() == 0 &&
374 (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
375 if (BaseReg == 0) { // Just a displacement?
376 // Emit special case [disp32] encoding
377 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
379 emitDisplacementField(DispForReloc, DispVal, PCAdj);
381 unsigned BaseRegNo = getX86RegNum(BaseReg);
382 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
383 // Emit simple indirect register encoding... [EAX] f.e.
384 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
385 } else if (!DispForReloc && isDisp8(DispVal)) {
386 // Emit the disp8 encoding... [REG+disp8]
387 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
388 emitConstant(DispVal, 1);
390 // Emit the most general non-SIB encoding: [REG+disp32]
391 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
392 emitDisplacementField(DispForReloc, DispVal, PCAdj);
396 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
397 assert(IndexReg.getReg() != X86::ESP &&
398 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
400 bool ForceDisp32 = false;
401 bool ForceDisp8 = false;
403 // If there is no base register, we emit the special case SIB byte with
404 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
405 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
407 } else if (DispForReloc) {
408 // Emit the normal disp32 encoding.
409 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
411 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
412 // Emit no displacement ModR/M byte
413 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
414 } else if (isDisp8(DispVal)) {
415 // Emit the disp8 encoding...
416 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
417 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
419 // Emit the normal disp32 encoding...
420 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
423 // Calculate what the SS field value should be...
424 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
425 unsigned SS = SSTable[Scale.getImm()];
428 // Handle the SIB byte for the case where there is no base. The
429 // displacement has already been output.
431 if (IndexReg.getReg())
432 IndexRegNo = getX86RegNum(IndexReg.getReg());
434 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
435 emitSIBByte(SS, IndexRegNo, 5);
437 unsigned BaseRegNo = getX86RegNum(BaseReg);
439 if (IndexReg.getReg())
440 IndexRegNo = getX86RegNum(IndexReg.getReg());
442 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
443 emitSIBByte(SS, IndexRegNo, BaseRegNo);
446 // Do we need to output a displacement?
448 emitConstant(DispVal, 1);
449 } else if (DispVal != 0 || ForceDisp32) {
450 emitDisplacementField(DispForReloc, DispVal, PCAdj);
455 template<class CodeEmitter>
456 void Emitter<CodeEmitter>::emitInstruction(
457 const MachineInstr &MI,
458 const TargetInstrDesc *Desc) {
461 unsigned Opcode = Desc->Opcode;
463 // Emit the lock opcode prefix as needed.
464 if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
466 // Emit segment override opcode prefix as needed.
467 switch (Desc->TSFlags & X86II::SegOvrMask) {
474 default: assert(0 && "Invalid segment!");
475 case 0: break; // No segment override!
478 // Emit the repeat opcode prefix as needed.
479 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
481 // Emit the operand size opcode prefix as needed.
482 if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
484 // Emit the address size opcode prefix as needed.
485 if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
487 bool Need0FPrefix = false;
488 switch (Desc->TSFlags & X86II::Op0Mask) {
489 case X86II::TB: // Two-byte opcode prefix
490 case X86II::T8: // 0F 38
491 case X86II::TA: // 0F 3A
494 case X86II::REP: break; // already handled.
495 case X86II::XS: // F3 0F
499 case X86II::XD: // F2 0F
503 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
504 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
506 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
507 >> X86II::Op0Shift));
508 break; // Two-byte opcode prefix
509 default: assert(0 && "Invalid prefix!");
510 case 0: break; // No prefix!
515 unsigned REX = X86InstrInfo::determineREX(MI);
517 MCE.emitByte(0x40 | REX);
520 // 0x0F escape code must be emitted just before the opcode.
524 switch (Desc->TSFlags & X86II::Op0Mask) {
525 case X86II::T8: // 0F 38
528 case X86II::TA: // 0F 3A
533 // If this is a two-address instruction, skip one of the register operands.
534 unsigned NumOps = Desc->getNumOperands();
536 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
538 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
539 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
542 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
543 switch (Desc->TSFlags & X86II::FormMask) {
544 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
546 // Remember the current PC offset, this is the PIC relocation
550 assert(0 && "psuedo instructions should be removed before code emission");
552 case TargetInstrInfo::INLINEASM: {
553 // We allow inline assembler nodes with empty bodies - they can
554 // implicitly define registers, which is ok for JIT.
555 if (MI.getOperand(0).getSymbolName()[0]) {
556 assert(0 && "JIT does not support inline asm!\n");
561 case TargetInstrInfo::DBG_LABEL:
562 case TargetInstrInfo::EH_LABEL:
563 MCE.emitLabel(MI.getOperand(0).getImm());
565 case TargetInstrInfo::IMPLICIT_DEF:
566 case TargetInstrInfo::DECLARE:
568 case X86::FP_REG_KILL:
570 case X86::MOVPC32r: {
571 // This emits the "call" portion of this pseudo instruction.
572 MCE.emitByte(BaseOpcode);
573 emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
574 // Remember PIC base.
575 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
576 X86JITInfo *JTI = TM.getJITInfo();
577 JTI->setPICBase(MCE.getCurrentPCValue());
584 MCE.emitByte(BaseOpcode);
586 if (CurOp != NumOps) {
587 const MachineOperand &MO = MI.getOperand(CurOp++);
589 DOUT << "RawFrm CurOp " << CurOp << "\n";
590 DOUT << "isMBB " << MO.isMBB() << "\n";
591 DOUT << "isGlobal " << MO.isGlobal() << "\n";
592 DOUT << "isSymbol " << MO.isSymbol() << "\n";
593 DOUT << "isImm " << MO.isImm() << "\n";
596 emitPCRelativeBlockAddress(MO.getMBB());
597 } else if (MO.isGlobal()) {
598 // Assume undefined functions may be outside the Small codespace.
601 (TM.getCodeModel() == CodeModel::Large ||
602 TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
603 Opcode == X86::TAILJMPd;
604 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
605 MO.getOffset(), 0, NeedStub);
606 } else if (MO.isSymbol()) {
607 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
608 } else if (MO.isImm()) {
609 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
610 // Fix up immediate operand for pc relative calls.
611 intptr_t Imm = (intptr_t)MO.getImm();
612 Imm = Imm - MCE.getCurrentPCValue() - 4;
613 emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
615 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
617 assert(0 && "Unknown RawFrm operand!");
622 case X86II::AddRegFrm:
623 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
625 if (CurOp != NumOps) {
626 const MachineOperand &MO1 = MI.getOperand(CurOp++);
627 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
629 emitConstant(MO1.getImm(), Size);
631 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
632 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
633 // This should not occur on Darwin for relocatable objects.
634 if (Opcode == X86::MOV64ri)
635 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
636 if (MO1.isGlobal()) {
637 bool NeedStub = isa<Function>(MO1.getGlobal());
638 bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
639 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
641 } else if (MO1.isSymbol())
642 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
643 else if (MO1.isCPI())
644 emitConstPoolAddress(MO1.getIndex(), rt);
645 else if (MO1.isJTI())
646 emitJumpTableAddress(MO1.getIndex(), rt);
651 case X86II::MRMDestReg: {
652 MCE.emitByte(BaseOpcode);
653 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
654 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
657 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
660 case X86II::MRMDestMem: {
661 MCE.emitByte(BaseOpcode);
662 emitMemModRMByte(MI, CurOp,
663 getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
665 CurOp += X86AddrNumOperands + 1;
667 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
671 case X86II::MRMSrcReg:
672 MCE.emitByte(BaseOpcode);
673 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
674 getX86RegNum(MI.getOperand(CurOp).getReg()));
677 emitConstant(MI.getOperand(CurOp++).getImm(),
678 X86InstrInfo::sizeOfImm(Desc));
681 case X86II::MRMSrcMem: {
682 // FIXME: Maybe lea should have its own form?
684 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
685 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
686 AddrOperands = X86AddrNumOperands - 1; // No segment register
688 AddrOperands = X86AddrNumOperands;
690 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
691 X86InstrInfo::sizeOfImm(Desc) : 0;
693 MCE.emitByte(BaseOpcode);
694 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
696 CurOp += AddrOperands + 1;
698 emitConstant(MI.getOperand(CurOp++).getImm(),
699 X86InstrInfo::sizeOfImm(Desc));
703 case X86II::MRM0r: case X86II::MRM1r:
704 case X86II::MRM2r: case X86II::MRM3r:
705 case X86II::MRM4r: case X86II::MRM5r:
706 case X86II::MRM6r: case X86II::MRM7r: {
707 MCE.emitByte(BaseOpcode);
709 // Special handling of lfence, mfence, monitor, and mwait.
710 if (Desc->getOpcode() == X86::LFENCE ||
711 Desc->getOpcode() == X86::MFENCE ||
712 Desc->getOpcode() == X86::MONITOR ||
713 Desc->getOpcode() == X86::MWAIT) {
714 emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
716 switch (Desc->getOpcode()) {
726 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
727 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
730 if (CurOp != NumOps) {
731 const MachineOperand &MO1 = MI.getOperand(CurOp++);
732 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
734 emitConstant(MO1.getImm(), Size);
736 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
737 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
738 if (Opcode == X86::MOV64ri32)
739 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
740 if (MO1.isGlobal()) {
741 bool NeedStub = isa<Function>(MO1.getGlobal());
742 bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
743 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
745 } else if (MO1.isSymbol())
746 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
747 else if (MO1.isCPI())
748 emitConstPoolAddress(MO1.getIndex(), rt);
749 else if (MO1.isJTI())
750 emitJumpTableAddress(MO1.getIndex(), rt);
756 case X86II::MRM0m: case X86II::MRM1m:
757 case X86II::MRM2m: case X86II::MRM3m:
758 case X86II::MRM4m: case X86II::MRM5m:
759 case X86II::MRM6m: case X86II::MRM7m: {
760 intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
761 (MI.getOperand(CurOp+X86AddrNumOperands).isImm() ?
762 X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
764 MCE.emitByte(BaseOpcode);
765 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
767 CurOp += X86AddrNumOperands;
769 if (CurOp != NumOps) {
770 const MachineOperand &MO = MI.getOperand(CurOp++);
771 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
773 emitConstant(MO.getImm(), Size);
775 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
776 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
777 if (Opcode == X86::MOV64mi32)
778 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
780 bool NeedStub = isa<Function>(MO.getGlobal());
781 bool Indirect = gvNeedsNonLazyPtr(MO.getGlobal());
782 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
784 } else if (MO.isSymbol())
785 emitExternalSymbolAddress(MO.getSymbolName(), rt);
787 emitConstPoolAddress(MO.getIndex(), rt);
789 emitJumpTableAddress(MO.getIndex(), rt);
795 case X86II::MRMInitReg:
796 MCE.emitByte(BaseOpcode);
797 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
798 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
799 getX86RegNum(MI.getOperand(CurOp).getReg()));
804 if (!Desc->isVariadic() && CurOp != NumOps) {
805 cerr << "Cannot encode: ";