1 //===-- X86CodeEmitter.cpp - Convert X86 code to machine code -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
17 #include "X86InstrInfo.h"
18 #include "X86JITInfo.h"
19 #include "X86Relocations.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/JITCodeEmitter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/MC/MCCodeEmitter.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/MC/MCInst.h"
32 #include "llvm/PassManager.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 STATISTIC(NumEmitted, "Number of machine instructions emitted");
42 template<class CodeEmitter>
43 class Emitter : public MachineFunctionPass {
44 const X86InstrInfo *II;
48 MachineModuleInfo *MMI;
49 intptr_t PICBaseOffset;
54 explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
55 : MachineFunctionPass(ID), II(0), TD(0), TM(tm),
56 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
57 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
59 bool runOnMachineFunction(MachineFunction &MF);
61 virtual const char *getPassName() const {
62 return "X86 Machine Code Emitter";
65 void emitOpcodePrefix(uint64_t TSFlags, int MemOperand,
66 const MachineInstr &MI,
67 const MCInstrDesc *Desc) const;
69 void emitVEXOpcodePrefix(uint64_t TSFlags, int MemOperand,
70 const MachineInstr &MI,
71 const MCInstrDesc *Desc) const;
73 void emitSegmentOverridePrefix(uint64_t TSFlags,
75 const MachineInstr &MI) const;
77 void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc);
79 void getAnalysisUsage(AnalysisUsage &AU) const {
81 AU.addRequired<MachineModuleInfo>();
82 MachineFunctionPass::getAnalysisUsage(AU);
86 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
87 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
88 intptr_t Disp = 0, intptr_t PCAdj = 0,
89 bool Indirect = false);
90 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
91 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
93 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
96 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
97 intptr_t Adj = 0, bool IsPCRel = true);
99 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
100 void emitRegModRMByte(unsigned RegOpcodeField);
101 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
102 void emitConstant(uint64_t Val, unsigned Size);
104 void emitMemModRMByte(const MachineInstr &MI,
105 unsigned Op, unsigned RegOpcodeField,
108 unsigned getX86RegNum(unsigned RegNo) const {
109 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
110 return TRI->getEncodingValue(RegNo) & 0x7;
113 unsigned char getVEXRegisterEncoding(const MachineInstr &MI,
114 unsigned OpNum) const;
117 template<class CodeEmitter>
118 char Emitter<CodeEmitter>::ID = 0;
119 } // end anonymous namespace.
121 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
122 /// to the specified JITCodeEmitter object.
123 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
124 JITCodeEmitter &JCE) {
125 return new Emitter<JITCodeEmitter>(TM, JCE);
128 template<class CodeEmitter>
129 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
130 MMI = &getAnalysis<MachineModuleInfo>();
131 MCE.setModuleInfo(MMI);
133 II = TM.getInstrInfo();
134 TD = TM.getDataLayout();
135 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
136 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
139 DEBUG(dbgs() << "JITTing function '" << MF.getName() << "'\n");
140 MCE.startFunction(MF);
141 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
143 MCE.StartMachineBasicBlock(MBB);
144 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
146 const MCInstrDesc &Desc = I->getDesc();
147 emitInstruction(*I, &Desc);
148 // MOVPC32r is basically a call plus a pop instruction.
149 if (Desc.getOpcode() == X86::MOVPC32r)
150 emitInstruction(*I, &II->get(X86::POP32r));
151 ++NumEmitted; // Keep track of the # of mi's emitted
154 } while (MCE.finishFunction(MF));
159 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
160 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
161 /// size, and 3) use of X86-64 extended registers.
162 static unsigned determineREX(const MachineInstr &MI) {
164 const MCInstrDesc &Desc = MI.getDesc();
166 // Pseudo instructions do not need REX prefix byte.
167 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
169 if (Desc.TSFlags & X86II::REX_W)
172 unsigned NumOps = Desc.getNumOperands();
174 bool isTwoAddr = NumOps > 1 &&
175 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1;
177 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
178 unsigned i = isTwoAddr ? 1 : 0;
179 for (unsigned e = NumOps; i != e; ++i) {
180 const MachineOperand& MO = MI.getOperand(i);
182 unsigned Reg = MO.getReg();
183 if (X86II::isX86_64NonExtLowByteReg(Reg))
188 switch (Desc.TSFlags & X86II::FormMask) {
189 case X86II::MRMSrcReg: {
190 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
192 i = isTwoAddr ? 2 : 1;
193 for (unsigned e = NumOps; i != e; ++i) {
194 const MachineOperand& MO = MI.getOperand(i);
195 if (X86InstrInfo::isX86_64ExtendedReg(MO))
200 case X86II::MRMSrcMem: {
201 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
204 i = isTwoAddr ? 2 : 1;
205 for (; i != NumOps; ++i) {
206 const MachineOperand& MO = MI.getOperand(i);
208 if (X86InstrInfo::isX86_64ExtendedReg(MO))
215 case X86II::MRM0m: case X86II::MRM1m:
216 case X86II::MRM2m: case X86II::MRM3m:
217 case X86II::MRM4m: case X86II::MRM5m:
218 case X86II::MRM6m: case X86II::MRM7m:
219 case X86II::MRMDestMem: {
220 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
221 i = isTwoAddr ? 1 : 0;
222 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
225 for (; i != e; ++i) {
226 const MachineOperand& MO = MI.getOperand(i);
228 if (X86InstrInfo::isX86_64ExtendedReg(MO))
236 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
238 i = isTwoAddr ? 2 : 1;
239 for (unsigned e = NumOps; i != e; ++i) {
240 const MachineOperand& MO = MI.getOperand(i);
241 if (X86InstrInfo::isX86_64ExtendedReg(MO))
252 /// emitPCRelativeBlockAddress - This method keeps track of the information
253 /// necessary to resolve the address of this block later and emits a dummy
256 template<class CodeEmitter>
257 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
258 // Remember where this reference was and where it is to so we can
259 // deal with it later.
260 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
261 X86::reloc_pcrel_word, MBB));
265 /// emitGlobalAddress - Emit the specified address to the code stream assuming
266 /// this is part of a "take the address of a global" instruction.
268 template<class CodeEmitter>
269 void Emitter<CodeEmitter>::emitGlobalAddress(const GlobalValue *GV,
271 intptr_t Disp /* = 0 */,
272 intptr_t PCAdj /* = 0 */,
273 bool Indirect /* = false */) {
274 intptr_t RelocCST = Disp;
275 if (Reloc == X86::reloc_picrel_word)
276 RelocCST = PICBaseOffset;
277 else if (Reloc == X86::reloc_pcrel_word)
279 MachineRelocation MR = Indirect
280 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
281 const_cast<GlobalValue *>(GV),
283 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
284 const_cast<GlobalValue *>(GV), RelocCST, false);
285 MCE.addRelocation(MR);
286 // The relocated value will be added to the displacement
287 if (Reloc == X86::reloc_absolute_dword)
288 MCE.emitDWordLE(Disp);
290 MCE.emitWordLE((int32_t)Disp);
293 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
294 /// be emitted to the current location in the function, and allow it to be PC
296 template<class CodeEmitter>
297 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
299 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
301 // X86 never needs stubs because instruction selection will always pick
302 // an instruction sequence that is large enough to hold any address
304 // (see X86ISelLowering.cpp, near 2039: X86TargetLowering::LowerCall)
305 bool NeedStub = false;
306 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
309 if (Reloc == X86::reloc_absolute_dword)
315 /// emitConstPoolAddress - Arrange for the address of an constant pool
316 /// to be emitted to the current location in the function, and allow it to be PC
318 template<class CodeEmitter>
319 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
320 intptr_t Disp /* = 0 */,
321 intptr_t PCAdj /* = 0 */) {
322 intptr_t RelocCST = 0;
323 if (Reloc == X86::reloc_picrel_word)
324 RelocCST = PICBaseOffset;
325 else if (Reloc == X86::reloc_pcrel_word)
327 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
328 Reloc, CPI, RelocCST));
329 // The relocated value will be added to the displacement
330 if (Reloc == X86::reloc_absolute_dword)
331 MCE.emitDWordLE(Disp);
333 MCE.emitWordLE((int32_t)Disp);
336 /// emitJumpTableAddress - Arrange for the address of a jump table to
337 /// be emitted to the current location in the function, and allow it to be PC
339 template<class CodeEmitter>
340 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
341 intptr_t PCAdj /* = 0 */) {
342 intptr_t RelocCST = 0;
343 if (Reloc == X86::reloc_picrel_word)
344 RelocCST = PICBaseOffset;
345 else if (Reloc == X86::reloc_pcrel_word)
347 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
348 Reloc, JTI, RelocCST));
349 // The relocated value will be added to the displacement
350 if (Reloc == X86::reloc_absolute_dword)
356 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
358 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
359 return RM | (RegOpcode << 3) | (Mod << 6);
362 template<class CodeEmitter>
363 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
364 unsigned RegOpcodeFld){
365 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
368 template<class CodeEmitter>
369 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
370 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
373 template<class CodeEmitter>
374 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
377 // SIB byte is in the same format as the ModRMByte...
378 MCE.emitByte(ModRMByte(SS, Index, Base));
381 template<class CodeEmitter>
382 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
383 // Output the constant in little endian byte order...
384 for (unsigned i = 0; i != Size; ++i) {
385 MCE.emitByte(Val & 255);
390 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
391 /// sign-extended field.
392 static bool isDisp8(int Value) {
393 return Value == (signed char)Value;
396 static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp,
397 const TargetMachine &TM) {
398 // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer
399 // mechanism as 32-bit mode.
400 if (TM.getSubtarget<X86Subtarget>().is64Bit() &&
401 !TM.getSubtarget<X86Subtarget>().isTargetDarwin())
404 // Return true if this is a reference to a stub containing the address of the
405 // global, not the global itself.
406 return isGlobalStubReference(GVOp.getTargetFlags());
409 template<class CodeEmitter>
410 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
412 intptr_t Adj /* = 0 */,
413 bool IsPCRel /* = true */) {
414 // If this is a simple integer displacement that doesn't require a relocation,
417 emitConstant(DispVal, 4);
421 // Otherwise, this is something that requires a relocation. Emit it as such
423 unsigned RelocType = Is64BitMode ?
424 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
425 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
426 if (RelocOp->isGlobal()) {
427 // In 64-bit static small code model, we could potentially emit absolute.
428 // But it's probably not beneficial. If the MCE supports using RIP directly
429 // do it, otherwise fallback to absolute (this is determined by IsPCRel).
430 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
431 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
432 bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
433 emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
435 } else if (RelocOp->isSymbol()) {
436 emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
437 } else if (RelocOp->isCPI()) {
438 emitConstPoolAddress(RelocOp->getIndex(), RelocType,
439 RelocOp->getOffset(), Adj);
441 assert(RelocOp->isJTI() && "Unexpected machine operand!");
442 emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
446 template<class CodeEmitter>
447 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
448 unsigned Op,unsigned RegOpcodeField,
450 const MachineOperand &Op3 = MI.getOperand(Op+3);
452 const MachineOperand *DispForReloc = 0;
454 // Figure out what sort of displacement we have to handle here.
455 if (Op3.isGlobal()) {
457 } else if (Op3.isSymbol()) {
459 } else if (Op3.isCPI()) {
460 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
463 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
464 DispVal += Op3.getOffset();
466 } else if (Op3.isJTI()) {
467 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) {
470 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
473 DispVal = Op3.getImm();
476 const MachineOperand &Base = MI.getOperand(Op);
477 const MachineOperand &Scale = MI.getOperand(Op+1);
478 const MachineOperand &IndexReg = MI.getOperand(Op+2);
480 unsigned BaseReg = Base.getReg();
482 // Handle %rip relative addressing.
483 if (BaseReg == X86::RIP ||
484 (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode
485 assert(IndexReg.getReg() == 0 && Is64BitMode &&
486 "Invalid rip-relative address");
487 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
488 emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
492 // Indicate that the displacement will use an pcrel or absolute reference
493 // by default. MCEs able to resolve addresses on-the-fly use pcrel by default
494 // while others, unless explicit asked to use RIP, use absolute references.
495 bool IsPCRel = MCE.earlyResolveAddresses() ? true : false;
497 // Is a SIB byte needed?
498 // If no BaseReg, issue a RIP relative instruction only if the MCE can
499 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
500 // 2-7) and absolute references.
501 unsigned BaseRegNo = -1U;
502 if (BaseReg != 0 && BaseReg != X86::RIP)
503 BaseRegNo = getX86RegNum(BaseReg);
505 if (// The SIB byte must be used if there is an index register.
506 IndexReg.getReg() == 0 &&
507 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
508 // encode to an R/M value of 4, which indicates that a SIB byte is
510 BaseRegNo != N86::ESP &&
511 // If there is no base register and we're in 64-bit mode, we need a SIB
512 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
513 (!Is64BitMode || BaseReg != 0)) {
514 if (BaseReg == 0 || // [disp32] in X86-32 mode
515 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
516 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
517 emitDisplacementField(DispForReloc, DispVal, PCAdj, true);
521 // If the base is not EBP/ESP and there is no displacement, use simple
522 // indirect register encoding, this handles addresses like [EAX]. The
523 // encoding for [EBP] with no displacement means [disp32] so we handle it
524 // by emitting a displacement of 0 below.
525 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
526 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
530 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
531 if (!DispForReloc && isDisp8(DispVal)) {
532 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
533 emitConstant(DispVal, 1);
537 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
538 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
539 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
543 // Otherwise we need a SIB byte, so start by outputting the ModR/M byte first.
544 assert(IndexReg.getReg() != X86::ESP &&
545 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
547 bool ForceDisp32 = false;
548 bool ForceDisp8 = false;
550 // If there is no base register, we emit the special case SIB byte with
551 // MOD=0, BASE=4, to JUST get the index, scale, and displacement.
552 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
554 } else if (DispForReloc) {
555 // Emit the normal disp32 encoding.
556 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
558 } else if (DispVal == 0 && BaseRegNo != N86::EBP) {
559 // Emit no displacement ModR/M byte
560 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
561 } else if (isDisp8(DispVal)) {
562 // Emit the disp8 encoding...
563 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
564 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
566 // Emit the normal disp32 encoding...
567 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
570 // Calculate what the SS field value should be...
571 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
572 unsigned SS = SSTable[Scale.getImm()];
575 // Handle the SIB byte for the case where there is no base, see Intel
576 // Manual 2A, table 2-7. The displacement has already been output.
578 if (IndexReg.getReg())
579 IndexRegNo = getX86RegNum(IndexReg.getReg());
580 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
582 emitSIBByte(SS, IndexRegNo, 5);
584 unsigned BaseRegNo = getX86RegNum(BaseReg);
586 if (IndexReg.getReg())
587 IndexRegNo = getX86RegNum(IndexReg.getReg());
589 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
590 emitSIBByte(SS, IndexRegNo, BaseRegNo);
593 // Do we need to output a displacement?
595 emitConstant(DispVal, 1);
596 } else if (DispVal != 0 || ForceDisp32) {
597 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel);
601 static const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II,
603 const MCInstrDesc *Desc = &II->get(Opcode);
608 /// Is16BitMemOperand - Return true if the specified instruction has
609 /// a 16-bit memory operand. Op specifies the operand # of the memoperand.
610 static bool Is16BitMemOperand(const MachineInstr &MI, unsigned Op) {
611 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
612 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
614 if ((BaseReg.getReg() != 0 &&
615 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
616 (IndexReg.getReg() != 0 &&
617 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
622 /// Is32BitMemOperand - Return true if the specified instruction has
623 /// a 32-bit memory operand. Op specifies the operand # of the memoperand.
624 static bool Is32BitMemOperand(const MachineInstr &MI, unsigned Op) {
625 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
626 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
628 if ((BaseReg.getReg() != 0 &&
629 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
630 (IndexReg.getReg() != 0 &&
631 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
636 /// Is64BitMemOperand - Return true if the specified instruction has
637 /// a 64-bit memory operand. Op specifies the operand # of the memoperand.
639 static bool Is64BitMemOperand(const MachineInstr &MI, unsigned Op) {
640 const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
641 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
643 if ((BaseReg.getReg() != 0 &&
644 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
645 (IndexReg.getReg() != 0 &&
646 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
652 template<class CodeEmitter>
653 void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
655 const MachineInstr &MI,
656 const MCInstrDesc *Desc) const {
657 // Emit the operand size opcode prefix as needed.
658 if (((TSFlags & X86II::OpSizeMask) >> X86II::OpSizeShift) == X86II::OpSize16)
661 switch (Desc->TSFlags & X86II::OpPrefixMask) {
662 case X86II::PD: // 66
665 case X86II::XS: // F3
668 case X86II::XD: // F2
673 // Handle REX prefix.
675 if (unsigned REX = determineREX(MI))
676 MCE.emitByte(0x40 | REX);
679 // 0x0F escape code must be emitted just before the opcode.
680 switch (Desc->TSFlags & X86II::OpMapMask) {
681 case X86II::TB: // Two-byte opcode map
682 case X86II::T8: // 0F 38
683 case X86II::TA: // 0F 3A
684 case X86II::A6: // 0F A6
685 case X86II::A7: // 0F A7
688 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
689 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
691 (((Desc->TSFlags & X86II::OpMapMask)-X86II::D8)
692 >> X86II::OpMapShift));
696 switch (Desc->TSFlags & X86II::OpMapMask) {
697 case X86II::T8: // 0F 38
700 case X86II::TA: // 0F 3A
703 case X86II::A6: // 0F A6
706 case X86II::A7: // 0F A7
712 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
713 // 0-7 and the difference between the 2 groups is given by the REX prefix.
714 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
715 // in 1's complement form, example:
717 // ModRM field => XMM9 => 1
718 // VEX.VVVV => XMM9 => ~9
720 // See table 4-35 of Intel AVX Programming Reference for details.
721 template<class CodeEmitter>
723 Emitter<CodeEmitter>::getVEXRegisterEncoding(const MachineInstr &MI,
724 unsigned OpNum) const {
725 unsigned SrcReg = MI.getOperand(OpNum).getReg();
726 unsigned SrcRegNum = getX86RegNum(MI.getOperand(OpNum).getReg());
727 if (X86II::isX86_64ExtendedReg(SrcReg))
730 // The registers represented through VEX_VVVV should
731 // be encoded in 1's complement form.
732 return (~SrcRegNum) & 0xf;
735 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
736 template<class CodeEmitter>
737 void Emitter<CodeEmitter>::emitSegmentOverridePrefix(uint64_t TSFlags,
739 const MachineInstr &MI) const {
741 return; // No memory operand
743 // Check for explicit segment override on memory operand.
744 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
745 default: llvm_unreachable("Unknown segment register!");
747 case X86::CS: MCE.emitByte(0x2E); break;
748 case X86::SS: MCE.emitByte(0x36); break;
749 case X86::DS: MCE.emitByte(0x3E); break;
750 case X86::ES: MCE.emitByte(0x26); break;
751 case X86::FS: MCE.emitByte(0x64); break;
752 case X86::GS: MCE.emitByte(0x65); break;
756 template<class CodeEmitter>
757 void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
759 const MachineInstr &MI,
760 const MCInstrDesc *Desc) const {
761 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
762 X86II::EncodingShift;
763 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
764 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
765 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
767 // VEX_R: opcode externsion equivalent to REX.R in
768 // 1's complement (inverted) form
770 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
771 // 0: Same as REX_R=1 (64 bit mode only)
773 unsigned char VEX_R = 0x1;
775 // VEX_X: equivalent to REX.X, only used when a
776 // register is used for index in SIB Byte.
778 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
779 // 0: Same as REX.X=1 (64-bit mode only)
780 unsigned char VEX_X = 0x1;
784 // 1: Same as REX_B=0 (ignored in 32-bit mode)
785 // 0: Same as REX_B=1 (64 bit mode only)
787 unsigned char VEX_B = 0x1;
789 // VEX_W: opcode specific (use like REX.W, or used for
790 // opcode extension, or ignored, depending on the opcode byte)
791 unsigned char VEX_W = 0;
793 // VEX_5M (VEX m-mmmmm field):
795 // 0b00000: Reserved for future use
796 // 0b00001: implied 0F leading opcode
797 // 0b00010: implied 0F 38 leading opcode bytes
798 // 0b00011: implied 0F 3A leading opcode bytes
799 // 0b00100-0b11111: Reserved for future use
800 // 0b01000: XOP map select - 08h instructions with imm byte
801 // 0b01001: XOP map select - 09h instructions with no imm byte
802 // 0b01010: XOP map select - 0Ah instructions with imm dword
803 unsigned char VEX_5M = 0;
805 // VEX_4V (VEX vvvv field): a register specifier
806 // (in 1's complement form) or 1111 if unused.
807 unsigned char VEX_4V = 0xf;
809 // VEX_L (Vector Length):
811 // 0: scalar or 128-bit vector
814 unsigned char VEX_L = 0;
816 // VEX_PP: opcode extension providing equivalent
817 // functionality of a SIMD prefix
824 unsigned char VEX_PP = 0;
826 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
829 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
832 switch (TSFlags & X86II::OpPrefixMask) {
833 default: break; // VEX_PP already correct
834 case X86II::PD: VEX_PP = 0x1; break; // 66
835 case X86II::XS: VEX_PP = 0x2; break; // F3
836 case X86II::XD: VEX_PP = 0x3; break; // F2
839 switch (TSFlags & X86II::OpMapMask) {
840 default: llvm_unreachable("Invalid prefix!");
841 case X86II::TB: VEX_5M = 0x1; break; // 0F
842 case X86II::T8: VEX_5M = 0x2; break; // 0F 38
843 case X86II::TA: VEX_5M = 0x3; break; // 0F 3A
844 case X86II::XOP8: VEX_5M = 0x8; break;
845 case X86II::XOP9: VEX_5M = 0x9; break;
846 case X86II::XOPA: VEX_5M = 0xA; break;
849 // Classify VEX_B, VEX_4V, VEX_R, VEX_X
850 unsigned NumOps = Desc->getNumOperands();
852 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) == 0)
854 else if (NumOps > 3 && Desc->getOperandConstraint(2, MCOI::TIED_TO) == 0) {
855 assert(Desc->getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
856 // Special case for GATHER with 2 TIED_TO operands
857 // Skip the first 2 operands: dst, mask_wb
861 switch (TSFlags & X86II::FormMask) {
862 default: llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");
865 case X86II::MRMDestMem: {
866 // MRMDestMem instructions forms:
867 // MemAddr, src1(ModR/M)
868 // MemAddr, src1(VEX_4V), src2(ModR/M)
869 // MemAddr, src1(ModR/M), imm8
871 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg()))
873 if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg()))
876 CurOp = X86::AddrNumOperands;
878 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
880 const MachineOperand &MO = MI.getOperand(CurOp);
881 if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg()))
885 case X86II::MRMSrcMem:
886 // MRMSrcMem instructions forms:
887 // src1(ModR/M), MemAddr
888 // src1(ModR/M), src2(VEX_4V), MemAddr
889 // src1(ModR/M), MemAddr, imm8
890 // src1(ModR/M), MemAddr, src2(VEX_I8IMM)
893 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
894 // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M),
895 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
900 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
904 if (X86II::isX86_64ExtendedReg(
905 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
907 if (X86II::isX86_64ExtendedReg(
908 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
912 VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands);
914 case X86II::MRM0m: case X86II::MRM1m:
915 case X86II::MRM2m: case X86II::MRM3m:
916 case X86II::MRM4m: case X86II::MRM5m:
917 case X86II::MRM6m: case X86II::MRM7m: {
918 // MRM[0-9]m instructions forms:
920 // src1(VEX_4V), MemAddr
922 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
924 if (X86II::isX86_64ExtendedReg(
925 MI.getOperand(MemOperand+X86::AddrBaseReg).getReg()))
927 if (X86II::isX86_64ExtendedReg(
928 MI.getOperand(MemOperand+X86::AddrIndexReg).getReg()))
932 case X86II::MRMSrcReg:
933 // MRMSrcReg instructions forms:
934 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM)
935 // dst(ModR/M), src1(ModR/M)
936 // dst(ModR/M), src1(ModR/M), imm8
938 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
943 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
945 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
948 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
952 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
954 case X86II::MRMDestReg:
955 // MRMDestReg instructions forms:
956 // dst(ModR/M), src(ModR/M)
957 // dst(ModR/M), src(ModR/M), imm8
958 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
959 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
964 VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
966 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
969 case X86II::MRM0r: case X86II::MRM1r:
970 case X86II::MRM2r: case X86II::MRM3r:
971 case X86II::MRM4r: case X86II::MRM5r:
972 case X86II::MRM6r: case X86II::MRM7r:
973 // MRM0r-MRM7r instructions forms:
974 // dst(VEX_4V), src(ModR/M), imm8
975 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
978 if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
983 // Emit segment override opcode prefix as needed.
984 emitSegmentOverridePrefix(TSFlags, MemOperand, MI);
986 // VEX opcode prefix can have 2 or 3 bytes
989 // +-----+ +--------------+ +-------------------+
990 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
991 // +-----+ +--------------+ +-------------------+
993 // +-----+ +-------------------+
994 // | C5h | | R | vvvv | L | pp |
995 // +-----+ +-------------------+
997 // XOP uses a similar prefix:
998 // +-----+ +--------------+ +-------------------+
999 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
1000 // +-----+ +--------------+ +-------------------+
1001 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
1003 // Can this use the 2 byte VEX prefix?
1004 if (Encoding == X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
1006 MCE.emitByte(LastByte | (VEX_R << 7));
1010 // 3 byte VEX prefix
1011 MCE.emitByte(Encoding == X86II::XOP ? 0x8F : 0xC4);
1012 MCE.emitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M);
1013 MCE.emitByte(LastByte | (VEX_W << 7));
1016 template<class CodeEmitter>
1017 void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
1018 const MCInstrDesc *Desc) {
1019 DEBUG(dbgs() << MI);
1021 // If this is a pseudo instruction, lower it.
1022 switch (Desc->getOpcode()) {
1023 case X86::ADD16rr_DB: Desc = UpdateOp(MI, II, X86::OR16rr); break;
1024 case X86::ADD32rr_DB: Desc = UpdateOp(MI, II, X86::OR32rr); break;
1025 case X86::ADD64rr_DB: Desc = UpdateOp(MI, II, X86::OR64rr); break;
1026 case X86::ADD16ri_DB: Desc = UpdateOp(MI, II, X86::OR16ri); break;
1027 case X86::ADD32ri_DB: Desc = UpdateOp(MI, II, X86::OR32ri); break;
1028 case X86::ADD64ri32_DB: Desc = UpdateOp(MI, II, X86::OR64ri32); break;
1029 case X86::ADD16ri8_DB: Desc = UpdateOp(MI, II, X86::OR16ri8); break;
1030 case X86::ADD32ri8_DB: Desc = UpdateOp(MI, II, X86::OR32ri8); break;
1031 case X86::ADD64ri8_DB: Desc = UpdateOp(MI, II, X86::OR64ri8); break;
1032 case X86::ACQUIRE_MOV8rm: Desc = UpdateOp(MI, II, X86::MOV8rm); break;
1033 case X86::ACQUIRE_MOV16rm: Desc = UpdateOp(MI, II, X86::MOV16rm); break;
1034 case X86::ACQUIRE_MOV32rm: Desc = UpdateOp(MI, II, X86::MOV32rm); break;
1035 case X86::ACQUIRE_MOV64rm: Desc = UpdateOp(MI, II, X86::MOV64rm); break;
1036 case X86::RELEASE_MOV8mr: Desc = UpdateOp(MI, II, X86::MOV8mr); break;
1037 case X86::RELEASE_MOV16mr: Desc = UpdateOp(MI, II, X86::MOV16mr); break;
1038 case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break;
1039 case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break;
1043 MCE.processDebugLoc(MI.getDebugLoc(), true);
1045 unsigned Opcode = Desc->Opcode;
1047 // If this is a two-address instruction, skip one of the register operands.
1048 unsigned NumOps = Desc->getNumOperands();
1050 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) == 0)
1052 else if (NumOps > 3 && Desc->getOperandConstraint(2, MCOI::TIED_TO) == 0) {
1053 assert(Desc->getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
1054 // Special case for GATHER with 2 TIED_TO operands
1055 // Skip the first 2 operands: dst, mask_wb
1059 uint64_t TSFlags = Desc->TSFlags;
1061 // Encoding type for this instruction.
1062 unsigned char Encoding = (TSFlags & X86II::EncodingMask) >>
1063 X86II::EncodingShift;
1065 // It uses the VEX.VVVV field?
1066 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
1067 bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3;
1068 bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4;
1069 const unsigned MemOp4_I8IMMOperand = 2;
1071 // Determine where the memory operand starts, if present.
1072 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
1073 if (MemoryOperand != -1) MemoryOperand += CurOp;
1075 // Emit the lock opcode prefix as needed.
1076 if (Desc->TSFlags & X86II::LOCK)
1079 // Emit segment override opcode prefix as needed.
1080 emitSegmentOverridePrefix(TSFlags, MemoryOperand, MI);
1082 // Emit the repeat opcode prefix as needed.
1083 if (Desc->TSFlags & X86II::REP)
1086 // Emit the address size opcode prefix as needed.
1087 bool need_address_override;
1088 if (TSFlags & X86II::AdSize) {
1089 need_address_override = true;
1090 } else if (MemoryOperand < 0) {
1091 need_address_override = false;
1092 } else if (Is64BitMode) {
1093 assert(!Is16BitMemOperand(MI, MemoryOperand));
1094 need_address_override = Is32BitMemOperand(MI, MemoryOperand);
1096 assert(!Is64BitMemOperand(MI, MemoryOperand));
1097 need_address_override = Is16BitMemOperand(MI, MemoryOperand);
1100 if (need_address_override)
1104 emitOpcodePrefix(TSFlags, MemoryOperand, MI, Desc);
1106 emitVEXOpcodePrefix(TSFlags, MemoryOperand, MI, Desc);
1108 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags);
1109 switch (TSFlags & X86II::FormMask) {
1111 llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
1113 // Remember the current PC offset, this is the PIC relocation
1117 llvm_unreachable("pseudo instructions should be removed before code"
1119 // Do nothing for Int_MemBarrier - it's just a comment. Add a debug
1120 // to make it slightly easier to see.
1121 case X86::Int_MemBarrier:
1122 DEBUG(dbgs() << "#MEMBARRIER\n");
1125 case TargetOpcode::INLINEASM:
1126 // We allow inline assembler nodes with empty bodies - they can
1127 // implicitly define registers, which is ok for JIT.
1128 if (MI.getOperand(0).getSymbolName()[0])
1129 report_fatal_error("JIT does not support inline asm!");
1131 case TargetOpcode::PROLOG_LABEL:
1132 case TargetOpcode::GC_LABEL:
1133 case TargetOpcode::EH_LABEL:
1134 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
1137 case TargetOpcode::IMPLICIT_DEF:
1138 case TargetOpcode::KILL:
1140 case X86::MOVPC32r: {
1141 // This emits the "call" portion of this pseudo instruction.
1142 MCE.emitByte(BaseOpcode);
1143 emitConstant(0, X86II::getSizeOfImm(Desc->TSFlags));
1144 // Remember PIC base.
1145 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
1146 X86JITInfo *JTI = TM.getJITInfo();
1147 JTI->setPICBase(MCE.getCurrentPCValue());
1153 case X86II::RawFrm: {
1154 MCE.emitByte(BaseOpcode);
1156 if (CurOp == NumOps)
1159 const MachineOperand &MO = MI.getOperand(CurOp++);
1161 DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n");
1162 DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n");
1163 DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n");
1164 DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n");
1165 DEBUG(dbgs() << "isImm " << MO.isImm() << "\n");
1168 emitPCRelativeBlockAddress(MO.getMBB());
1172 if (MO.isGlobal()) {
1173 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
1178 if (MO.isSymbol()) {
1179 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
1183 // FIXME: Only used by hackish MCCodeEmitter, remove when dead.
1185 emitJumpTableAddress(MO.getIndex(), X86::reloc_pcrel_word);
1189 assert(MO.isImm() && "Unknown RawFrm operand!");
1190 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
1191 // Fix up immediate operand for pc relative calls.
1192 intptr_t Imm = (intptr_t)MO.getImm();
1193 Imm = Imm - MCE.getCurrentPCValue() - 4;
1194 emitConstant(Imm, X86II::getSizeOfImm(Desc->TSFlags));
1196 emitConstant(MO.getImm(), X86II::getSizeOfImm(Desc->TSFlags));
1200 case X86II::AddRegFrm: {
1201 MCE.emitByte(BaseOpcode +
1202 getX86RegNum(MI.getOperand(CurOp++).getReg()));
1204 if (CurOp == NumOps)
1207 const MachineOperand &MO1 = MI.getOperand(CurOp++);
1208 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
1210 emitConstant(MO1.getImm(), Size);
1214 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
1215 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
1216 if (Opcode == X86::MOV32ri64)
1217 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
1218 // This should not occur on Darwin for relocatable objects.
1219 if (Opcode == X86::MOV64ri)
1220 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
1221 if (MO1.isGlobal()) {
1222 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
1223 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
1225 } else if (MO1.isSymbol())
1226 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
1227 else if (MO1.isCPI())
1228 emitConstPoolAddress(MO1.getIndex(), rt);
1229 else if (MO1.isJTI())
1230 emitJumpTableAddress(MO1.getIndex(), rt);
1234 case X86II::MRMDestReg: {
1235 MCE.emitByte(BaseOpcode);
1237 unsigned SrcRegNum = CurOp+1;
1238 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1241 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
1242 getX86RegNum(MI.getOperand(SrcRegNum).getReg()));
1243 CurOp = SrcRegNum + 1;
1246 case X86II::MRMDestMem: {
1247 MCE.emitByte(BaseOpcode);
1249 unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1250 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1252 emitMemModRMByte(MI, CurOp,
1253 getX86RegNum(MI.getOperand(SrcRegNum).getReg()));
1254 CurOp = SrcRegNum + 1;
1258 case X86II::MRMSrcReg: {
1259 MCE.emitByte(BaseOpcode);
1261 unsigned SrcRegNum = CurOp+1;
1262 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1265 if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM)
1268 emitRegModRMByte(MI.getOperand(SrcRegNum).getReg(),
1269 getX86RegNum(MI.getOperand(CurOp).getReg()));
1270 // 2 operands skipped with HasMemOp4, compensate accordingly
1271 CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
1276 case X86II::MRMSrcMem: {
1277 int AddrOperands = X86::AddrNumOperands;
1278 unsigned FirstMemOp = CurOp+1;
1281 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1283 if (HasMemOp4) // Skip second register source (encoded in I8IMM)
1286 MCE.emitByte(BaseOpcode);
1288 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
1289 X86II::getSizeOfImm(Desc->TSFlags) : 0;
1290 emitMemModRMByte(MI, FirstMemOp,
1291 getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
1292 CurOp += AddrOperands + 1;
1298 case X86II::MRM0r: case X86II::MRM1r:
1299 case X86II::MRM2r: case X86II::MRM3r:
1300 case X86II::MRM4r: case X86II::MRM5r:
1301 case X86II::MRM6r: case X86II::MRM7r: {
1302 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1304 MCE.emitByte(BaseOpcode);
1305 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
1306 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
1308 if (CurOp == NumOps)
1311 const MachineOperand &MO1 = MI.getOperand(CurOp++);
1312 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
1314 emitConstant(MO1.getImm(), Size);
1318 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
1319 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
1320 if (Opcode == X86::MOV64ri32)
1321 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
1322 if (MO1.isGlobal()) {
1323 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
1324 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
1326 } else if (MO1.isSymbol())
1327 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
1328 else if (MO1.isCPI())
1329 emitConstPoolAddress(MO1.getIndex(), rt);
1330 else if (MO1.isJTI())
1331 emitJumpTableAddress(MO1.getIndex(), rt);
1335 case X86II::MRM0m: case X86II::MRM1m:
1336 case X86II::MRM2m: case X86II::MRM3m:
1337 case X86II::MRM4m: case X86II::MRM5m:
1338 case X86II::MRM6m: case X86II::MRM7m: {
1339 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1341 intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ?
1342 (MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ?
1343 X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0;
1345 MCE.emitByte(BaseOpcode);
1346 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
1348 CurOp += X86::AddrNumOperands;
1350 if (CurOp == NumOps)
1353 const MachineOperand &MO = MI.getOperand(CurOp++);
1354 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
1356 emitConstant(MO.getImm(), Size);
1360 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
1361 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
1362 if (Opcode == X86::MOV64mi32)
1363 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
1364 if (MO.isGlobal()) {
1365 bool Indirect = gvNeedsNonLazyPtr(MO, TM);
1366 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
1368 } else if (MO.isSymbol())
1369 emitExternalSymbolAddress(MO.getSymbolName(), rt);
1370 else if (MO.isCPI())
1371 emitConstPoolAddress(MO.getIndex(), rt);
1372 else if (MO.isJTI())
1373 emitJumpTableAddress(MO.getIndex(), rt);
1377 case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
1378 case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
1379 case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0:
1380 case X86II::MRM_D1: case X86II::MRM_D4: case X86II::MRM_D5:
1381 case X86II::MRM_D6: case X86II::MRM_D8: case X86II::MRM_D9:
1382 case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
1383 case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
1384 case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
1385 MCE.emitByte(BaseOpcode);
1388 switch (TSFlags & X86II::FormMask) {
1389 default: llvm_unreachable("Invalid Form");
1390 case X86II::MRM_C1: MRM = 0xC1; break;
1391 case X86II::MRM_C2: MRM = 0xC2; break;
1392 case X86II::MRM_C3: MRM = 0xC3; break;
1393 case X86II::MRM_C4: MRM = 0xC4; break;
1394 case X86II::MRM_C8: MRM = 0xC8; break;
1395 case X86II::MRM_C9: MRM = 0xC9; break;
1396 case X86II::MRM_CA: MRM = 0xCA; break;
1397 case X86II::MRM_CB: MRM = 0xCB; break;
1398 case X86II::MRM_D0: MRM = 0xD0; break;
1399 case X86II::MRM_D1: MRM = 0xD1; break;
1400 case X86II::MRM_D4: MRM = 0xD4; break;
1401 case X86II::MRM_D5: MRM = 0xD5; break;
1402 case X86II::MRM_D6: MRM = 0xD6; break;
1403 case X86II::MRM_D8: MRM = 0xD8; break;
1404 case X86II::MRM_D9: MRM = 0xD9; break;
1405 case X86II::MRM_DA: MRM = 0xDA; break;
1406 case X86II::MRM_DB: MRM = 0xDB; break;
1407 case X86II::MRM_DC: MRM = 0xDC; break;
1408 case X86II::MRM_DD: MRM = 0xDD; break;
1409 case X86II::MRM_DE: MRM = 0xDE; break;
1410 case X86II::MRM_DF: MRM = 0xDF; break;
1411 case X86II::MRM_E8: MRM = 0xE8; break;
1412 case X86II::MRM_F0: MRM = 0xF0; break;
1413 case X86II::MRM_F8: MRM = 0xF8; break;
1414 case X86II::MRM_F9: MRM = 0xF9; break;
1420 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1421 // The last source register of a 4 operand instruction in AVX is encoded
1422 // in bits[7:4] of a immediate byte.
1423 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1424 const MachineOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
1427 unsigned RegNum = getX86RegNum(MO.getReg()) << 4;
1428 if (X86II::isX86_64ExtendedReg(MO.getReg()))
1430 // If there is an additional 5th operand it must be an immediate, which
1431 // is encoded in bits[3:0]
1432 if (CurOp != NumOps) {
1433 const MachineOperand &MIMM = MI.getOperand(CurOp++);
1435 unsigned Val = MIMM.getImm();
1436 assert(Val < 16 && "Immediate operand value out of range");
1440 emitConstant(RegNum, 1);
1442 emitConstant(MI.getOperand(CurOp++).getImm(),
1443 X86II::getSizeOfImm(Desc->TSFlags));
1447 if (!MI.isVariadic() && CurOp != NumOps) {
1449 dbgs() << "Cannot encode all operands of: " << MI << "\n";
1451 llvm_unreachable(0);
1454 MCE.processDebugLoc(MI.getDebugLoc(), false);