1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86TargetMachine.h"
19 #include "X86Relocations.h"
21 #include "llvm/PassManager.h"
22 #include "llvm/CodeGen/MachineCodeEmitter.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/Function.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Target/TargetOptions.h"
32 STATISTIC(NumEmitted, "Number of machine instructions emitted");
35 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
36 const X86InstrInfo *II;
39 MachineCodeEmitter &MCE;
43 explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
44 : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
45 MCE(mce), Is64BitMode(false) {}
46 Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
47 const X86InstrInfo &ii, const TargetData &td, bool is64)
48 : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
49 MCE(mce), Is64BitMode(is64) {}
51 bool runOnMachineFunction(MachineFunction &MF);
53 virtual const char *getPassName() const {
54 return "X86 Machine Code Emitter";
57 void emitInstruction(const MachineInstr &MI);
60 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
61 void emitPCRelativeValue(intptr_t Address);
62 void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
63 void emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
64 int Disp = 0, unsigned PCAdj = 0);
65 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
66 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
68 void emitJumpTableAddress(unsigned JTI, unsigned Reloc, unsigned PCAdj = 0);
70 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
73 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
74 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
75 void emitConstant(uint64_t Val, unsigned Size);
77 void emitMemModRMByte(const MachineInstr &MI,
78 unsigned Op, unsigned RegOpcodeField,
81 unsigned getX86RegNum(unsigned RegNo);
82 bool isX86_64ExtendedReg(const MachineOperand &MO);
83 unsigned determineREX(const MachineInstr &MI);
85 const int Emitter::ID = 0;
88 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
89 /// to the specified MCE object.
90 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
91 MachineCodeEmitter &MCE) {
92 return new Emitter(TM, MCE);
95 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
96 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
97 MF.getTarget().getRelocationModel() != Reloc::Static) &&
98 "JIT relocation model must be set to static or default!");
99 II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
100 TD = ((X86TargetMachine&)MF.getTarget()).getTargetData();
102 ((X86TargetMachine&)MF.getTarget()).getSubtarget<X86Subtarget>().is64Bit();
105 MCE.startFunction(MF);
106 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
108 MCE.StartMachineBasicBlock(MBB);
109 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
113 } while (MCE.finishFunction(MF));
118 /// emitPCRelativeValue - Emit a PC relative address.
120 void Emitter::emitPCRelativeValue(intptr_t Address) {
121 MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
124 /// emitPCRelativeBlockAddress - This method keeps track of the information
125 /// necessary to resolve the address of this block later and emits a dummy
128 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
129 // Remember where this reference was and where it is to so we can
130 // deal with it later.
131 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
132 X86::reloc_pcrel_word, MBB));
136 /// emitGlobalAddressForCall - Emit the specified address to the code stream
137 /// assuming this is part of a function call, which is PC relative.
139 void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
140 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
141 X86::reloc_pcrel_word, GV, 0,
146 /// emitGlobalAddress - Emit the specified address to the code stream assuming
147 /// this is part of a "take the address of a global" instruction.
149 void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
151 unsigned PCAdj /* = 0 */) {
152 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
154 if (Reloc == X86::reloc_absolute_dword)
156 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
159 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
160 /// be emitted to the current location in the function, and allow it to be PC
162 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
163 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
165 if (Reloc == X86::reloc_absolute_dword)
170 /// emitConstPoolAddress - Arrange for the address of an constant pool
171 /// to be emitted to the current location in the function, and allow it to be PC
173 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
175 unsigned PCAdj /* = 0 */) {
176 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
178 if (Reloc == X86::reloc_absolute_dword)
180 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
183 /// emitJumpTableAddress - Arrange for the address of a jump table to
184 /// be emitted to the current location in the function, and allow it to be PC
186 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
187 unsigned PCAdj /* = 0 */) {
188 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
190 if (Reloc == X86::reloc_absolute_dword)
192 MCE.emitWordLE(0); // The relocated value will be added to the displacement
195 /// N86 namespace - Native X86 Register numbers... used by X86 backend.
199 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
203 // getX86RegNum - This function maps LLVM register identifiers to their X86
204 // specific numbering, which is used in various places encoding instructions.
206 unsigned Emitter::getX86RegNum(unsigned RegNo) {
208 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
209 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
210 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
211 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
212 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
214 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
216 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
218 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
221 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
223 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
225 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
227 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
229 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
231 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
233 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
235 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
238 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
239 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
240 return RegNo-X86::ST0;
242 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
243 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
244 return II->getRegisterInfo().getDwarfRegNum(RegNo) -
245 II->getRegisterInfo().getDwarfRegNum(X86::XMM0);
246 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
247 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
248 return II->getRegisterInfo().getDwarfRegNum(RegNo) -
249 II->getRegisterInfo().getDwarfRegNum(X86::XMM8);
252 assert(MRegisterInfo::isVirtualRegister(RegNo) &&
253 "Unknown physical register!");
254 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
259 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
261 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
262 return RM | (RegOpcode << 3) | (Mod << 6);
265 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
266 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
269 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
270 // SIB byte is in the same format as the ModRMByte...
271 MCE.emitByte(ModRMByte(SS, Index, Base));
274 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
275 // Output the constant in little endian byte order...
276 for (unsigned i = 0; i != Size; ++i) {
277 MCE.emitByte(Val & 255);
282 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
283 /// sign-extended field.
284 static bool isDisp8(int Value) {
285 return Value == (signed char)Value;
288 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
289 int DispVal, unsigned PCAdj) {
290 // If this is a simple integer displacement that doesn't require a relocation,
293 emitConstant(DispVal, 4);
297 // Otherwise, this is something that requires a relocation. Emit it as such
299 if (RelocOp->isGlobalAddress()) {
300 // In 64-bit static small code model, we could potentially emit absolute.
301 // But it's probably not beneficial.
302 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
303 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
304 unsigned rt= Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
305 emitGlobalAddressForPtr(RelocOp->getGlobal(), rt,
306 RelocOp->getOffset(), PCAdj);
307 } else if (RelocOp->isConstantPoolIndex()) {
308 // Must be in 64-bit mode.
309 emitConstPoolAddress(RelocOp->getConstantPoolIndex(), X86::reloc_pcrel_word,
310 RelocOp->getOffset(), PCAdj);
311 } else if (RelocOp->isJumpTableIndex()) {
312 // Must be in 64-bit mode.
313 emitJumpTableAddress(RelocOp->getJumpTableIndex(), X86::reloc_pcrel_word,
316 assert(0 && "Unknown value to relocate!");
320 void Emitter::emitMemModRMByte(const MachineInstr &MI,
321 unsigned Op, unsigned RegOpcodeField,
323 const MachineOperand &Op3 = MI.getOperand(Op+3);
325 const MachineOperand *DispForReloc = 0;
327 // Figure out what sort of displacement we have to handle here.
328 if (Op3.isGlobalAddress()) {
330 } else if (Op3.isConstantPoolIndex()) {
334 DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
335 DispVal += Op3.getOffset();
337 } else if (Op3.isJumpTableIndex()) {
341 DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
344 DispVal = Op3.getImm();
347 const MachineOperand &Base = MI.getOperand(Op);
348 const MachineOperand &Scale = MI.getOperand(Op+1);
349 const MachineOperand &IndexReg = MI.getOperand(Op+2);
351 unsigned BaseReg = Base.getReg();
353 // Is a SIB byte needed?
354 if (IndexReg.getReg() == 0 &&
355 (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
356 if (BaseReg == 0) { // Just a displacement?
357 // Emit special case [disp32] encoding
358 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
360 emitDisplacementField(DispForReloc, DispVal, PCAdj);
362 unsigned BaseRegNo = getX86RegNum(BaseReg);
363 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
364 // Emit simple indirect register encoding... [EAX] f.e.
365 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
366 } else if (!DispForReloc && isDisp8(DispVal)) {
367 // Emit the disp8 encoding... [REG+disp8]
368 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
369 emitConstant(DispVal, 1);
371 // Emit the most general non-SIB encoding: [REG+disp32]
372 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
373 emitDisplacementField(DispForReloc, DispVal, PCAdj);
377 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
378 assert(IndexReg.getReg() != X86::ESP &&
379 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
381 bool ForceDisp32 = false;
382 bool ForceDisp8 = false;
384 // If there is no base register, we emit the special case SIB byte with
385 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
386 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
388 } else if (DispForReloc) {
389 // Emit the normal disp32 encoding.
390 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
392 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
393 // Emit no displacement ModR/M byte
394 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
395 } else if (isDisp8(DispVal)) {
396 // Emit the disp8 encoding...
397 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
398 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
400 // Emit the normal disp32 encoding...
401 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
404 // Calculate what the SS field value should be...
405 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
406 unsigned SS = SSTable[Scale.getImm()];
409 // Handle the SIB byte for the case where there is no base. The
410 // displacement has already been output.
411 assert(IndexReg.getReg() && "Index register must be specified!");
412 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
414 unsigned BaseRegNo = getX86RegNum(BaseReg);
416 if (IndexReg.getReg())
417 IndexRegNo = getX86RegNum(IndexReg.getReg());
419 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
420 emitSIBByte(SS, IndexRegNo, BaseRegNo);
423 // Do we need to output a displacement?
425 emitConstant(DispVal, 1);
426 } else if (DispVal != 0 || ForceDisp32) {
427 emitDisplacementField(DispForReloc, DispVal, PCAdj);
432 static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
433 switch (Desc->TSFlags & X86II::ImmMask) {
434 case X86II::Imm8: return 1;
435 case X86II::Imm16: return 2;
436 case X86II::Imm32: return 4;
437 case X86II::Imm64: return 8;
438 default: assert(0 && "Immediate size not set!");
443 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
444 /// e.g. r8, xmm8, etc.
445 bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
446 if (!MO.isRegister()) return false;
447 unsigned RegNo = MO.getReg();
448 int DWNum = II->getRegisterInfo().getDwarfRegNum(RegNo);
449 if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::R8) &&
450 DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::R15))
452 if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::XMM8) &&
453 DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::XMM15))
458 inline static bool isX86_64TruncToByte(unsigned oc) {
459 return (oc == X86::TRUNC_64to8 || oc == X86::TRUNC_32to8 ||
460 oc == X86::TRUNC_16to8);
464 inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
465 return (reg == X86::SPL || reg == X86::BPL ||
466 reg == X86::SIL || reg == X86::DIL);
469 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
470 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
471 /// size, and 3) use of X86-64 extended registers.
472 unsigned Emitter::determineREX(const MachineInstr &MI) {
474 const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
475 unsigned Opcode = Desc->Opcode;
477 // Pseudo instructions do not need REX prefix byte.
478 if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
480 if (Desc->TSFlags & X86II::REX_W)
483 unsigned NumOps = Desc->numOperands;
485 bool isTwoAddr = NumOps > 1 &&
486 Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
488 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
489 bool isTrunc8 = isX86_64TruncToByte(Opcode);
490 unsigned i = isTwoAddr ? 1 : 0;
491 for (unsigned e = NumOps; i != e; ++i) {
492 const MachineOperand& MO = MI.getOperand(i);
493 if (MO.isRegister()) {
494 unsigned Reg = MO.getReg();
495 // Trunc to byte are actually movb. The real source operand is the low
496 // byte of the register.
497 if (isTrunc8 && i == 1)
498 Reg = getX86SubSuperRegister(Reg, MVT::i8);
499 if (isX86_64NonExtLowByteReg(Reg))
504 switch (Desc->TSFlags & X86II::FormMask) {
505 case X86II::MRMInitReg:
506 if (isX86_64ExtendedReg(MI.getOperand(0)))
507 REX |= (1 << 0) | (1 << 2);
509 case X86II::MRMSrcReg: {
510 if (isX86_64ExtendedReg(MI.getOperand(0)))
512 i = isTwoAddr ? 2 : 1;
513 for (unsigned e = NumOps; i != e; ++i) {
514 const MachineOperand& MO = MI.getOperand(i);
515 if (isX86_64ExtendedReg(MO))
520 case X86II::MRMSrcMem: {
521 if (isX86_64ExtendedReg(MI.getOperand(0)))
524 i = isTwoAddr ? 2 : 1;
525 for (; i != NumOps; ++i) {
526 const MachineOperand& MO = MI.getOperand(i);
527 if (MO.isRegister()) {
528 if (isX86_64ExtendedReg(MO))
535 case X86II::MRM0m: case X86II::MRM1m:
536 case X86II::MRM2m: case X86II::MRM3m:
537 case X86II::MRM4m: case X86II::MRM5m:
538 case X86II::MRM6m: case X86II::MRM7m:
539 case X86II::MRMDestMem: {
540 unsigned e = isTwoAddr ? 5 : 4;
541 i = isTwoAddr ? 1 : 0;
542 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
545 for (; i != e; ++i) {
546 const MachineOperand& MO = MI.getOperand(i);
547 if (MO.isRegister()) {
548 if (isX86_64ExtendedReg(MO))
556 if (isX86_64ExtendedReg(MI.getOperand(0)))
558 i = isTwoAddr ? 2 : 1;
559 for (unsigned e = NumOps; i != e; ++i) {
560 const MachineOperand& MO = MI.getOperand(i);
561 if (isX86_64ExtendedReg(MO))
571 void Emitter::emitInstruction(const MachineInstr &MI) {
572 NumEmitted++; // Keep track of the # of mi's emitted
574 const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
575 unsigned Opcode = Desc->Opcode;
577 // Emit the repeat opcode prefix as needed.
578 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
580 // Emit the operand size opcode prefix as needed.
581 if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
583 // Emit the address size opcode prefix as needed.
584 if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
586 bool Need0FPrefix = false;
587 switch (Desc->TSFlags & X86II::Op0Mask) {
589 Need0FPrefix = true; // Two-byte opcode prefix
599 case X86II::REP: break; // already handled.
600 case X86II::XS: // F3 0F
604 case X86II::XD: // F2 0F
608 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
609 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
611 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
612 >> X86II::Op0Shift));
613 break; // Two-byte opcode prefix
614 default: assert(0 && "Invalid prefix!");
615 case 0: break; // No prefix!
620 unsigned REX = determineREX(MI);
622 MCE.emitByte(0x40 | REX);
625 // 0x0F escape code must be emitted just before the opcode.
629 // If this is a two-address instruction, skip one of the register operands.
630 unsigned NumOps = Desc->numOperands;
632 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
635 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
636 switch (Desc->TSFlags & X86II::FormMask) {
637 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
642 assert(0 && "psuedo instructions should be removed before code emission");
643 case TargetInstrInfo::INLINEASM:
644 assert(0 && "JIT does not support inline asm!\n");
645 case TargetInstrInfo::LABEL:
646 assert(0 && "JIT does not support meta labels!\n");
647 case X86::IMPLICIT_USE:
648 case X86::IMPLICIT_DEF:
649 case X86::IMPLICIT_DEF_GR8:
650 case X86::IMPLICIT_DEF_GR16:
651 case X86::IMPLICIT_DEF_GR32:
652 case X86::IMPLICIT_DEF_GR64:
653 case X86::IMPLICIT_DEF_FR32:
654 case X86::IMPLICIT_DEF_FR64:
655 case X86::IMPLICIT_DEF_VR64:
656 case X86::IMPLICIT_DEF_VR128:
657 case X86::FP_REG_KILL:
665 MCE.emitByte(BaseOpcode);
666 if (CurOp != NumOps) {
667 const MachineOperand &MO = MI.getOperand(CurOp++);
668 if (MO.isMachineBasicBlock()) {
669 emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
670 } else if (MO.isGlobalAddress()) {
671 bool NeedStub = Is64BitMode ||
672 Opcode == X86::TAILJMPd ||
673 Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
674 emitGlobalAddressForCall(MO.getGlobal(), !NeedStub);
675 } else if (MO.isExternalSymbol()) {
676 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
677 } else if (MO.isImmediate()) {
678 emitConstant(MO.getImm(), sizeOfImm(Desc));
680 assert(0 && "Unknown RawFrm operand!");
685 case X86II::AddRegFrm:
686 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
688 if (CurOp != NumOps) {
689 const MachineOperand &MO1 = MI.getOperand(CurOp++);
690 unsigned Size = sizeOfImm(Desc);
691 if (MO1.isImmediate())
692 emitConstant(MO1.getImm(), Size);
694 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
695 if (Opcode == X86::MOV64ri)
696 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
697 if (MO1.isGlobalAddress())
698 emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
699 else if (MO1.isExternalSymbol())
700 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
701 else if (MO1.isConstantPoolIndex())
702 emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
703 else if (MO1.isJumpTableIndex())
704 emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
709 case X86II::MRMDestReg: {
710 MCE.emitByte(BaseOpcode);
711 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
712 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
715 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
718 case X86II::MRMDestMem: {
719 MCE.emitByte(BaseOpcode);
720 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
723 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
727 case X86II::MRMSrcReg:
728 MCE.emitByte(BaseOpcode);
729 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
730 getX86RegNum(MI.getOperand(CurOp).getReg()));
733 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
736 case X86II::MRMSrcMem: {
737 unsigned PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0;
739 MCE.emitByte(BaseOpcode);
740 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
744 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
748 case X86II::MRM0r: case X86II::MRM1r:
749 case X86II::MRM2r: case X86II::MRM3r:
750 case X86II::MRM4r: case X86II::MRM5r:
751 case X86II::MRM6r: case X86II::MRM7r:
752 MCE.emitByte(BaseOpcode);
753 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
754 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
756 if (CurOp != NumOps) {
757 const MachineOperand &MO1 = MI.getOperand(CurOp++);
758 unsigned Size = sizeOfImm(Desc);
759 if (MO1.isImmediate())
760 emitConstant(MO1.getImm(), Size);
762 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
763 : X86::reloc_absolute_word;
764 if (Opcode == X86::MOV64ri32)
765 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
766 if (MO1.isGlobalAddress())
767 emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
768 else if (MO1.isExternalSymbol())
769 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
770 else if (MO1.isConstantPoolIndex())
771 emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
772 else if (MO1.isJumpTableIndex())
773 emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
778 case X86II::MRM0m: case X86II::MRM1m:
779 case X86II::MRM2m: case X86II::MRM3m:
780 case X86II::MRM4m: case X86II::MRM5m:
781 case X86II::MRM6m: case X86II::MRM7m: {
782 unsigned PCAdj = (CurOp+4 != NumOps) ?
783 (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
785 MCE.emitByte(BaseOpcode);
786 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
790 if (CurOp != NumOps) {
791 const MachineOperand &MO = MI.getOperand(CurOp++);
792 unsigned Size = sizeOfImm(Desc);
793 if (MO.isImmediate())
794 emitConstant(MO.getImm(), Size);
796 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
797 : X86::reloc_absolute_word;
798 if (Opcode == X86::MOV64mi32)
799 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
800 if (MO.isGlobalAddress())
801 emitGlobalAddressForPtr(MO.getGlobal(), rt, MO.getOffset());
802 else if (MO.isExternalSymbol())
803 emitExternalSymbolAddress(MO.getSymbolName(), rt);
804 else if (MO.isConstantPoolIndex())
805 emitConstPoolAddress(MO.getConstantPoolIndex(), rt);
806 else if (MO.isJumpTableIndex())
807 emitJumpTableAddress(MO.getJumpTableIndex(), rt);
813 case X86II::MRMInitReg:
814 MCE.emitByte(BaseOpcode);
815 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
816 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
817 getX86RegNum(MI.getOperand(CurOp).getReg()));
822 assert((Desc->Flags & M_VARIABLE_OPS) != 0 ||
823 CurOp == NumOps && "Unknown encoding!");