1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/Function.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Target/TargetOptions.h"
35 STATISTIC(NumEmitted, "Number of machine instructions emitted");
38 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
39 const X86InstrInfo *II;
42 MachineCodeEmitter &MCE;
43 intptr_t PICBaseOffset;
48 explicit Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
49 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
50 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
51 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
52 Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce,
53 const X86InstrInfo &ii, const TargetData &td, bool is64)
54 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
55 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
56 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
58 bool runOnMachineFunction(MachineFunction &MF);
60 virtual const char *getPassName() const {
61 return "X86 Machine Code Emitter";
64 void emitInstruction(const MachineInstr &MI,
65 const TargetInstrDesc *Desc);
67 void getAnalysisUsage(AnalysisUsage &AU) const {
68 AU.addRequired<MachineModuleInfo>();
69 MachineFunctionPass::getAnalysisUsage(AU);
73 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
74 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
75 int Disp = 0, intptr_t PCAdj = 0,
76 bool NeedStub = false, bool IsLazy = false);
77 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
78 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
80 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
83 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
86 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
87 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
88 void emitConstant(uint64_t Val, unsigned Size);
90 void emitMemModRMByte(const MachineInstr &MI,
91 unsigned Op, unsigned RegOpcodeField,
94 unsigned getX86RegNum(unsigned RegNo) const;
96 bool gvNeedsLazyPtr(const GlobalValue *GV);
101 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
102 /// to the specified MCE object.
103 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
104 MachineCodeEmitter &MCE) {
105 return new Emitter(TM, MCE);
108 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
110 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
112 II = TM.getInstrInfo();
113 TD = TM.getTargetData();
114 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
115 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
118 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
119 MCE.startFunction(MF);
120 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
122 MCE.StartMachineBasicBlock(MBB);
123 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
125 const TargetInstrDesc &Desc = I->getDesc();
126 emitInstruction(*I, &Desc);
127 // MOVPC32r is basically a call plus a pop instruction.
128 if (Desc.getOpcode() == X86::MOVPC32r)
129 emitInstruction(*I, &II->get(X86::POP32r));
130 NumEmitted++; // Keep track of the # of mi's emitted
133 } while (MCE.finishFunction(MF));
138 /// emitPCRelativeBlockAddress - This method keeps track of the information
139 /// necessary to resolve the address of this block later and emits a dummy
142 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
143 // Remember where this reference was and where it is to so we can
144 // deal with it later.
145 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
146 X86::reloc_pcrel_word, MBB));
150 /// emitGlobalAddress - Emit the specified address to the code stream assuming
151 /// this is part of a "take the address of a global" instruction.
153 void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
154 int Disp /* = 0 */, intptr_t PCAdj /* = 0 */,
155 bool NeedStub /* = false */,
156 bool isLazy /* = false */) {
157 intptr_t RelocCST = 0;
158 if (Reloc == X86::reloc_picrel_word)
159 RelocCST = PICBaseOffset;
160 else if (Reloc == X86::reloc_pcrel_word)
162 MachineRelocation MR = isLazy
163 ? MachineRelocation::getGVLazyPtr(MCE.getCurrentPCOffset(), Reloc,
164 GV, RelocCST, NeedStub)
165 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
166 GV, RelocCST, NeedStub);
167 MCE.addRelocation(MR);
168 if (Reloc == X86::reloc_absolute_dword)
170 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
173 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
174 /// be emitted to the current location in the function, and allow it to be PC
176 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
177 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
178 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
179 Reloc, ES, RelocCST));
180 if (Reloc == X86::reloc_absolute_dword)
185 /// emitConstPoolAddress - Arrange for the address of an constant pool
186 /// to be emitted to the current location in the function, and allow it to be PC
188 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
190 intptr_t PCAdj /* = 0 */) {
191 intptr_t RelocCST = 0;
192 if (Reloc == X86::reloc_picrel_word)
193 RelocCST = PICBaseOffset;
194 else if (Reloc == X86::reloc_pcrel_word)
196 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
197 Reloc, CPI, RelocCST));
198 if (Reloc == X86::reloc_absolute_dword)
200 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
203 /// emitJumpTableAddress - Arrange for the address of a jump table to
204 /// be emitted to the current location in the function, and allow it to be PC
206 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
207 intptr_t PCAdj /* = 0 */) {
208 intptr_t RelocCST = 0;
209 if (Reloc == X86::reloc_picrel_word)
210 RelocCST = PICBaseOffset;
211 else if (Reloc == X86::reloc_pcrel_word)
213 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
214 Reloc, JTI, RelocCST));
215 if (Reloc == X86::reloc_absolute_dword)
217 MCE.emitWordLE(0); // The relocated value will be added to the displacement
220 unsigned Emitter::getX86RegNum(unsigned RegNo) const {
221 return II->getRegisterInfo().getX86RegNum(RegNo);
224 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
226 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
227 return RM | (RegOpcode << 3) | (Mod << 6);
230 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
231 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
234 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
235 // SIB byte is in the same format as the ModRMByte...
236 MCE.emitByte(ModRMByte(SS, Index, Base));
239 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
240 // Output the constant in little endian byte order...
241 for (unsigned i = 0; i != Size; ++i) {
242 MCE.emitByte(Val & 255);
247 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
248 /// sign-extended field.
249 static bool isDisp8(int Value) {
250 return Value == (signed char)Value;
253 bool Emitter::gvNeedsLazyPtr(const GlobalValue *GV) {
254 // For Darwin, simulate the linktime GOT by using the same lazy-pointer
255 // mechanism as 32-bit mode.
256 return (!Is64BitMode || TM.getSubtarget<X86Subtarget>().isTargetDarwin()) &&
257 TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
260 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
261 int DispVal, intptr_t PCAdj) {
262 // If this is a simple integer displacement that doesn't require a relocation,
265 emitConstant(DispVal, 4);
269 // Otherwise, this is something that requires a relocation. Emit it as such
271 if (RelocOp->isGlobal()) {
272 // In 64-bit static small code model, we could potentially emit absolute.
273 // But it's probably not beneficial.
274 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
275 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
276 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
277 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
278 bool NeedStub = isa<Function>(RelocOp->getGlobal());
279 bool isLazy = gvNeedsLazyPtr(RelocOp->getGlobal());
280 emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
281 PCAdj, NeedStub, isLazy);
282 } else if (RelocOp->isCPI()) {
283 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
284 emitConstPoolAddress(RelocOp->getIndex(), rt,
285 RelocOp->getOffset(), PCAdj);
286 } else if (RelocOp->isJTI()) {
287 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
288 emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
290 assert(0 && "Unknown value to relocate!");
294 void Emitter::emitMemModRMByte(const MachineInstr &MI,
295 unsigned Op, unsigned RegOpcodeField,
297 const MachineOperand &Op3 = MI.getOperand(Op+3);
299 const MachineOperand *DispForReloc = 0;
301 // Figure out what sort of displacement we have to handle here.
302 if (Op3.isGlobal()) {
304 } else if (Op3.isCPI()) {
305 if (Is64BitMode || IsPIC) {
308 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
309 DispVal += Op3.getOffset();
311 } else if (Op3.isJTI()) {
312 if (Is64BitMode || IsPIC) {
315 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
318 DispVal = Op3.getImm();
321 const MachineOperand &Base = MI.getOperand(Op);
322 const MachineOperand &Scale = MI.getOperand(Op+1);
323 const MachineOperand &IndexReg = MI.getOperand(Op+2);
325 unsigned BaseReg = Base.getReg();
327 // Is a SIB byte needed?
328 if (IndexReg.getReg() == 0 &&
329 (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
330 if (BaseReg == 0) { // Just a displacement?
331 // Emit special case [disp32] encoding
332 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
334 emitDisplacementField(DispForReloc, DispVal, PCAdj);
336 unsigned BaseRegNo = getX86RegNum(BaseReg);
337 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
338 // Emit simple indirect register encoding... [EAX] f.e.
339 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
340 } else if (!DispForReloc && isDisp8(DispVal)) {
341 // Emit the disp8 encoding... [REG+disp8]
342 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
343 emitConstant(DispVal, 1);
345 // Emit the most general non-SIB encoding: [REG+disp32]
346 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
347 emitDisplacementField(DispForReloc, DispVal, PCAdj);
351 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
352 assert(IndexReg.getReg() != X86::ESP &&
353 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
355 bool ForceDisp32 = false;
356 bool ForceDisp8 = false;
358 // If there is no base register, we emit the special case SIB byte with
359 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
360 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
362 } else if (DispForReloc) {
363 // Emit the normal disp32 encoding.
364 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
366 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
367 // Emit no displacement ModR/M byte
368 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
369 } else if (isDisp8(DispVal)) {
370 // Emit the disp8 encoding...
371 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
372 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
374 // Emit the normal disp32 encoding...
375 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
378 // Calculate what the SS field value should be...
379 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
380 unsigned SS = SSTable[Scale.getImm()];
383 // Handle the SIB byte for the case where there is no base. The
384 // displacement has already been output.
385 assert(IndexReg.getReg() && "Index register must be specified!");
386 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
388 unsigned BaseRegNo = getX86RegNum(BaseReg);
390 if (IndexReg.getReg())
391 IndexRegNo = getX86RegNum(IndexReg.getReg());
393 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
394 emitSIBByte(SS, IndexRegNo, BaseRegNo);
397 // Do we need to output a displacement?
399 emitConstant(DispVal, 1);
400 } else if (DispVal != 0 || ForceDisp32) {
401 emitDisplacementField(DispForReloc, DispVal, PCAdj);
406 void Emitter::emitInstruction(const MachineInstr &MI,
407 const TargetInstrDesc *Desc) {
410 unsigned Opcode = Desc->Opcode;
412 // Emit the lock opcode prefix as needed.
413 if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
415 // Emit segment override opcode prefix as needed.
416 switch (Desc->TSFlags & X86II::SegOvrMask) {
425 // Emit the repeat opcode prefix as needed.
426 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
428 // Emit the operand size opcode prefix as needed.
429 if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
431 // Emit the address size opcode prefix as needed.
432 if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
434 bool Need0FPrefix = false;
435 switch (Desc->TSFlags & X86II::Op0Mask) {
436 case X86II::TB: // Two-byte opcode prefix
437 case X86II::T8: // 0F 38
438 case X86II::TA: // 0F 3A
441 case X86II::REP: break; // already handled.
442 case X86II::XS: // F3 0F
446 case X86II::XD: // F2 0F
450 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
451 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
453 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
454 >> X86II::Op0Shift));
455 break; // Two-byte opcode prefix
456 default: assert(0 && "Invalid prefix!");
457 case 0: break; // No prefix!
462 unsigned REX = X86InstrInfo::determineREX(MI);
464 MCE.emitByte(0x40 | REX);
467 // 0x0F escape code must be emitted just before the opcode.
471 switch (Desc->TSFlags & X86II::Op0Mask) {
472 case X86II::T8: // 0F 38
475 case X86II::TA: // 0F 3A
480 // If this is a two-address instruction, skip one of the register operands.
481 unsigned NumOps = Desc->getNumOperands();
483 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
485 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
486 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
489 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
490 switch (Desc->TSFlags & X86II::FormMask) {
491 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
493 // Remember the current PC offset, this is the PIC relocation
497 assert(0 && "psuedo instructions should be removed before code emission");
499 case TargetInstrInfo::INLINEASM: {
500 const char* Value = MI.getOperand(0).getSymbolName();
501 /* We allow inline assembler nodes with empty bodies - they can
502 implicitly define registers, which is ok for JIT. */
503 assert((Value[0] == 0) && "JIT does not support inline asm!\n");
506 case TargetInstrInfo::DBG_LABEL:
507 case TargetInstrInfo::EH_LABEL:
508 MCE.emitLabel(MI.getOperand(0).getImm());
510 case TargetInstrInfo::IMPLICIT_DEF:
511 case TargetInstrInfo::DECLARE:
513 case X86::FP_REG_KILL:
515 case X86::MOVPC32r: {
516 // This emits the "call" portion of this pseudo instruction.
517 MCE.emitByte(BaseOpcode);
518 emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
519 // Remember PIC base.
520 PICBaseOffset = MCE.getCurrentPCOffset();
521 X86JITInfo *JTI = TM.getJITInfo();
522 JTI->setPICBase(MCE.getCurrentPCValue());
529 MCE.emitByte(BaseOpcode);
531 if (CurOp != NumOps) {
532 const MachineOperand &MO = MI.getOperand(CurOp++);
534 DOUT << "RawFrm CurOp " << CurOp << "\n";
535 DOUT << "isMBB " << MO.isMBB() << "\n";
536 DOUT << "isGlobal " << MO.isGlobal() << "\n";
537 DOUT << "isSymbol " << MO.isSymbol() << "\n";
538 DOUT << "isImm " << MO.isImm() << "\n";
541 emitPCRelativeBlockAddress(MO.getMBB());
542 } else if (MO.isGlobal()) {
543 // Assume undefined functions may be outside the Small codespace.
546 (TM.getCodeModel() == CodeModel::Large ||
547 TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
548 Opcode == X86::TAILJMPd;
549 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
551 } else if (MO.isSymbol()) {
552 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
553 } else if (MO.isImm()) {
554 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
556 assert(0 && "Unknown RawFrm operand!");
561 case X86II::AddRegFrm:
562 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
564 if (CurOp != NumOps) {
565 const MachineOperand &MO1 = MI.getOperand(CurOp++);
566 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
568 emitConstant(MO1.getImm(), Size);
570 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
571 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
572 // This should not occur on Darwin for relocatable objects.
573 if (Opcode == X86::MOV64ri)
574 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
575 if (MO1.isGlobal()) {
576 bool NeedStub = isa<Function>(MO1.getGlobal());
577 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
578 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
580 } else if (MO1.isSymbol())
581 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
582 else if (MO1.isCPI())
583 emitConstPoolAddress(MO1.getIndex(), rt);
584 else if (MO1.isJTI())
585 emitJumpTableAddress(MO1.getIndex(), rt);
590 case X86II::MRMDestReg: {
591 MCE.emitByte(BaseOpcode);
592 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
593 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
596 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
599 case X86II::MRMDestMem: {
600 MCE.emitByte(BaseOpcode);
601 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
604 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
608 case X86II::MRMSrcReg:
609 MCE.emitByte(BaseOpcode);
610 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
611 getX86RegNum(MI.getOperand(CurOp).getReg()));
614 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
617 case X86II::MRMSrcMem: {
618 intptr_t PCAdj = (CurOp+5 != NumOps) ? X86InstrInfo::sizeOfImm(Desc) : 0;
620 MCE.emitByte(BaseOpcode);
621 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
625 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
629 case X86II::MRM0r: case X86II::MRM1r:
630 case X86II::MRM2r: case X86II::MRM3r:
631 case X86II::MRM4r: case X86II::MRM5r:
632 case X86II::MRM6r: case X86II::MRM7r:
633 MCE.emitByte(BaseOpcode);
634 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
635 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
637 if (CurOp != NumOps) {
638 const MachineOperand &MO1 = MI.getOperand(CurOp++);
639 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
641 emitConstant(MO1.getImm(), Size);
643 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
644 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
645 if (Opcode == X86::MOV64ri32)
646 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
647 if (MO1.isGlobal()) {
648 bool NeedStub = isa<Function>(MO1.getGlobal());
649 bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
650 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
652 } else if (MO1.isSymbol())
653 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
654 else if (MO1.isCPI())
655 emitConstPoolAddress(MO1.getIndex(), rt);
656 else if (MO1.isJTI())
657 emitJumpTableAddress(MO1.getIndex(), rt);
662 case X86II::MRM0m: case X86II::MRM1m:
663 case X86II::MRM2m: case X86II::MRM3m:
664 case X86II::MRM4m: case X86II::MRM5m:
665 case X86II::MRM6m: case X86II::MRM7m: {
666 intptr_t PCAdj = (CurOp+4 != NumOps) ?
667 (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
669 MCE.emitByte(BaseOpcode);
670 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
674 if (CurOp != NumOps) {
675 const MachineOperand &MO = MI.getOperand(CurOp++);
676 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
678 emitConstant(MO.getImm(), Size);
680 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
681 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
682 if (Opcode == X86::MOV64mi32)
683 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
685 bool NeedStub = isa<Function>(MO.getGlobal());
686 bool isLazy = gvNeedsLazyPtr(MO.getGlobal());
687 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
689 } else if (MO.isSymbol())
690 emitExternalSymbolAddress(MO.getSymbolName(), rt);
692 emitConstPoolAddress(MO.getIndex(), rt);
694 emitJumpTableAddress(MO.getIndex(), rt);
700 case X86II::MRMInitReg:
701 MCE.emitByte(BaseOpcode);
702 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
703 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
704 getX86RegNum(MI.getOperand(CurOp).getReg()));
709 if (!Desc->isVariadic() && CurOp != NumOps) {
710 cerr << "Cannot encode: ";