1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/Function.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Target/TargetOptions.h"
35 STATISTIC(NumEmitted, "Number of machine instructions emitted");
38 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
39 const X86InstrInfo *II;
42 MachineCodeEmitter &MCE;
43 intptr_t PICBaseOffset;
48 explicit Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
49 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
50 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
51 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
52 Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce,
53 const X86InstrInfo &ii, const TargetData &td, bool is64)
54 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
55 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
56 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
58 bool runOnMachineFunction(MachineFunction &MF);
60 virtual const char *getPassName() const {
61 return "X86 Machine Code Emitter";
64 void emitInstruction(const MachineInstr &MI,
65 const TargetInstrDesc *Desc);
67 void getAnalysisUsage(AnalysisUsage &AU) const {
68 AU.addRequired<MachineModuleInfo>();
69 MachineFunctionPass::getAnalysisUsage(AU);
73 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
74 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
75 intptr_t Disp = 0, intptr_t PCAdj = 0,
76 bool NeedStub = false, bool Indirect = false);
77 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
78 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
80 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
83 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
86 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
87 void emitRegModRMByte(unsigned RegOpcodeField);
88 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
89 void emitConstant(uint64_t Val, unsigned Size);
91 void emitMemModRMByte(const MachineInstr &MI,
92 unsigned Op, unsigned RegOpcodeField,
95 unsigned getX86RegNum(unsigned RegNo) const;
97 bool gvNeedsNonLazyPtr(const GlobalValue *GV);
102 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
103 /// to the specified MCE object.
104 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
105 MachineCodeEmitter &MCE) {
106 return new Emitter(TM, MCE);
109 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
111 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
113 II = TM.getInstrInfo();
114 TD = TM.getTargetData();
115 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
116 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
119 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
120 MCE.startFunction(MF);
121 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
123 MCE.StartMachineBasicBlock(MBB);
124 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
126 const TargetInstrDesc &Desc = I->getDesc();
127 emitInstruction(*I, &Desc);
128 // MOVPC32r is basically a call plus a pop instruction.
129 if (Desc.getOpcode() == X86::MOVPC32r)
130 emitInstruction(*I, &II->get(X86::POP32r));
131 NumEmitted++; // Keep track of the # of mi's emitted
134 } while (MCE.finishFunction(MF));
139 /// emitPCRelativeBlockAddress - This method keeps track of the information
140 /// necessary to resolve the address of this block later and emits a dummy
143 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
144 // Remember where this reference was and where it is to so we can
145 // deal with it later.
146 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
147 X86::reloc_pcrel_word, MBB));
151 /// emitGlobalAddress - Emit the specified address to the code stream assuming
152 /// this is part of a "take the address of a global" instruction.
154 void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
155 intptr_t Disp /* = 0 */,
156 intptr_t PCAdj /* = 0 */,
157 bool NeedStub /* = false */,
158 bool Indirect /* = false */) {
159 intptr_t RelocCST = 0;
160 if (Reloc == X86::reloc_picrel_word)
161 RelocCST = PICBaseOffset;
162 else if (Reloc == X86::reloc_pcrel_word)
164 MachineRelocation MR = Indirect
165 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
166 GV, RelocCST, NeedStub)
167 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
168 GV, RelocCST, NeedStub);
169 MCE.addRelocation(MR);
170 // The relocated value will be added to the displacement
171 if (Reloc == X86::reloc_absolute_dword)
172 MCE.emitDWordLE(Disp);
174 MCE.emitWordLE((int32_t)Disp);
177 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
178 /// be emitted to the current location in the function, and allow it to be PC
180 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
181 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
182 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
183 Reloc, ES, RelocCST));
184 if (Reloc == X86::reloc_absolute_dword)
190 /// emitConstPoolAddress - Arrange for the address of an constant pool
191 /// to be emitted to the current location in the function, and allow it to be PC
193 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
194 intptr_t Disp /* = 0 */,
195 intptr_t PCAdj /* = 0 */) {
196 intptr_t RelocCST = 0;
197 if (Reloc == X86::reloc_picrel_word)
198 RelocCST = PICBaseOffset;
199 else if (Reloc == X86::reloc_pcrel_word)
201 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
202 Reloc, CPI, RelocCST));
203 // The relocated value will be added to the displacement
204 if (Reloc == X86::reloc_absolute_dword)
205 MCE.emitDWordLE(Disp);
207 MCE.emitWordLE((int32_t)Disp);
210 /// emitJumpTableAddress - Arrange for the address of a jump table to
211 /// be emitted to the current location in the function, and allow it to be PC
213 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
214 intptr_t PCAdj /* = 0 */) {
215 intptr_t RelocCST = 0;
216 if (Reloc == X86::reloc_picrel_word)
217 RelocCST = PICBaseOffset;
218 else if (Reloc == X86::reloc_pcrel_word)
220 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
221 Reloc, JTI, RelocCST));
222 // The relocated value will be added to the displacement
223 if (Reloc == X86::reloc_absolute_dword)
229 unsigned Emitter::getX86RegNum(unsigned RegNo) const {
230 return II->getRegisterInfo().getX86RegNum(RegNo);
233 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
235 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
236 return RM | (RegOpcode << 3) | (Mod << 6);
239 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
240 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
243 void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) {
244 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
247 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
248 // SIB byte is in the same format as the ModRMByte...
249 MCE.emitByte(ModRMByte(SS, Index, Base));
252 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
253 // Output the constant in little endian byte order...
254 for (unsigned i = 0; i != Size; ++i) {
255 MCE.emitByte(Val & 255);
260 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
261 /// sign-extended field.
262 static bool isDisp8(int Value) {
263 return Value == (signed char)Value;
266 bool Emitter::gvNeedsNonLazyPtr(const GlobalValue *GV) {
267 // For Darwin, simulate the linktime GOT by using the same non-lazy-pointer
268 // mechanism as 32-bit mode.
269 return (!Is64BitMode || TM.getSubtarget<X86Subtarget>().isTargetDarwin()) &&
270 TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
273 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
274 int DispVal, intptr_t PCAdj) {
275 // If this is a simple integer displacement that doesn't require a relocation,
278 emitConstant(DispVal, 4);
282 // Otherwise, this is something that requires a relocation. Emit it as such
284 if (RelocOp->isGlobal()) {
285 // In 64-bit static small code model, we could potentially emit absolute.
286 // But it's probably not beneficial.
287 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
288 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
289 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
290 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
291 bool NeedStub = isa<Function>(RelocOp->getGlobal());
292 bool Indirect = gvNeedsNonLazyPtr(RelocOp->getGlobal());
293 emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
294 PCAdj, NeedStub, Indirect);
295 } else if (RelocOp->isCPI()) {
296 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
297 emitConstPoolAddress(RelocOp->getIndex(), rt,
298 RelocOp->getOffset(), PCAdj);
299 } else if (RelocOp->isJTI()) {
300 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
301 emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
303 assert(0 && "Unknown value to relocate!");
307 void Emitter::emitMemModRMByte(const MachineInstr &MI,
308 unsigned Op, unsigned RegOpcodeField,
310 const MachineOperand &Op3 = MI.getOperand(Op+3);
312 const MachineOperand *DispForReloc = 0;
314 // Figure out what sort of displacement we have to handle here.
315 if (Op3.isGlobal()) {
317 } else if (Op3.isCPI()) {
318 if (Is64BitMode || IsPIC) {
321 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
322 DispVal += Op3.getOffset();
324 } else if (Op3.isJTI()) {
325 if (Is64BitMode || IsPIC) {
328 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
331 DispVal = Op3.getImm();
334 const MachineOperand &Base = MI.getOperand(Op);
335 const MachineOperand &Scale = MI.getOperand(Op+1);
336 const MachineOperand &IndexReg = MI.getOperand(Op+2);
338 unsigned BaseReg = Base.getReg();
340 // Is a SIB byte needed?
341 if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 &&
342 (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
343 if (BaseReg == 0) { // Just a displacement?
344 // Emit special case [disp32] encoding
345 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
347 emitDisplacementField(DispForReloc, DispVal, PCAdj);
349 unsigned BaseRegNo = getX86RegNum(BaseReg);
350 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
351 // Emit simple indirect register encoding... [EAX] f.e.
352 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
353 } else if (!DispForReloc && isDisp8(DispVal)) {
354 // Emit the disp8 encoding... [REG+disp8]
355 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
356 emitConstant(DispVal, 1);
358 // Emit the most general non-SIB encoding: [REG+disp32]
359 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
360 emitDisplacementField(DispForReloc, DispVal, PCAdj);
364 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
365 assert(IndexReg.getReg() != X86::ESP &&
366 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
368 bool ForceDisp32 = false;
369 bool ForceDisp8 = false;
371 // If there is no base register, we emit the special case SIB byte with
372 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
373 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
375 } else if (DispForReloc) {
376 // Emit the normal disp32 encoding.
377 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
379 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
380 // Emit no displacement ModR/M byte
381 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
382 } else if (isDisp8(DispVal)) {
383 // Emit the disp8 encoding...
384 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
385 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
387 // Emit the normal disp32 encoding...
388 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
391 // Calculate what the SS field value should be...
392 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
393 unsigned SS = SSTable[Scale.getImm()];
396 // Handle the SIB byte for the case where there is no base. The
397 // displacement has already been output.
399 if (IndexReg.getReg())
400 IndexRegNo = getX86RegNum(IndexReg.getReg());
402 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
403 emitSIBByte(SS, IndexRegNo, 5);
405 unsigned BaseRegNo = getX86RegNum(BaseReg);
407 if (IndexReg.getReg())
408 IndexRegNo = getX86RegNum(IndexReg.getReg());
410 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
411 emitSIBByte(SS, IndexRegNo, BaseRegNo);
414 // Do we need to output a displacement?
416 emitConstant(DispVal, 1);
417 } else if (DispVal != 0 || ForceDisp32) {
418 emitDisplacementField(DispForReloc, DispVal, PCAdj);
423 void Emitter::emitInstruction(const MachineInstr &MI,
424 const TargetInstrDesc *Desc) {
427 unsigned Opcode = Desc->Opcode;
429 // Emit the lock opcode prefix as needed.
430 if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
432 // Emit segment override opcode prefix as needed.
433 switch (Desc->TSFlags & X86II::SegOvrMask) {
440 default: assert(0 && "Invalid segment!");
441 case 0: break; // No segment override!
444 // Emit the repeat opcode prefix as needed.
445 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
447 // Emit the operand size opcode prefix as needed.
448 if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
450 // Emit the address size opcode prefix as needed.
451 if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
453 bool Need0FPrefix = false;
454 switch (Desc->TSFlags & X86II::Op0Mask) {
455 case X86II::TB: // Two-byte opcode prefix
456 case X86II::T8: // 0F 38
457 case X86II::TA: // 0F 3A
460 case X86II::REP: break; // already handled.
461 case X86II::XS: // F3 0F
465 case X86II::XD: // F2 0F
469 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
470 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
472 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
473 >> X86II::Op0Shift));
474 break; // Two-byte opcode prefix
475 default: assert(0 && "Invalid prefix!");
476 case 0: break; // No prefix!
481 unsigned REX = X86InstrInfo::determineREX(MI);
483 MCE.emitByte(0x40 | REX);
486 // 0x0F escape code must be emitted just before the opcode.
490 switch (Desc->TSFlags & X86II::Op0Mask) {
491 case X86II::T8: // 0F 38
494 case X86II::TA: // 0F 3A
499 // If this is a two-address instruction, skip one of the register operands.
500 unsigned NumOps = Desc->getNumOperands();
502 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
504 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
505 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
508 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
509 switch (Desc->TSFlags & X86II::FormMask) {
510 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
512 // Remember the current PC offset, this is the PIC relocation
516 assert(0 && "psuedo instructions should be removed before code emission");
518 case TargetInstrInfo::INLINEASM: {
519 // We allow inline assembler nodes with empty bodies - they can
520 // implicitly define registers, which is ok for JIT.
521 if (MI.getOperand(0).getSymbolName()[0]) {
522 assert(0 && "JIT does not support inline asm!\n");
527 case TargetInstrInfo::DBG_LABEL:
528 case TargetInstrInfo::EH_LABEL:
529 MCE.emitLabel(MI.getOperand(0).getImm());
531 case TargetInstrInfo::IMPLICIT_DEF:
532 case TargetInstrInfo::DECLARE:
534 case X86::FP_REG_KILL:
537 MCE.emitByte(BaseOpcode);
538 unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
539 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
543 case X86::TLS_gs_ri: {
544 MCE.emitByte(BaseOpcode);
545 unsigned RegOpcodeField = getX86RegNum(MI.getOperand(0).getReg());
546 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
547 GlobalValue* GV = MI.getOperand(1).getGlobal();
548 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
549 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
550 emitGlobalAddress(GV, rt);
553 case X86::MOVPC32r: {
554 // This emits the "call" portion of this pseudo instruction.
555 MCE.emitByte(BaseOpcode);
556 emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
557 // Remember PIC base.
558 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
559 X86JITInfo *JTI = TM.getJITInfo();
560 JTI->setPICBase(MCE.getCurrentPCValue());
567 MCE.emitByte(BaseOpcode);
569 if (CurOp != NumOps) {
570 const MachineOperand &MO = MI.getOperand(CurOp++);
572 DOUT << "RawFrm CurOp " << CurOp << "\n";
573 DOUT << "isMBB " << MO.isMBB() << "\n";
574 DOUT << "isGlobal " << MO.isGlobal() << "\n";
575 DOUT << "isSymbol " << MO.isSymbol() << "\n";
576 DOUT << "isImm " << MO.isImm() << "\n";
579 emitPCRelativeBlockAddress(MO.getMBB());
580 } else if (MO.isGlobal()) {
581 // Assume undefined functions may be outside the Small codespace.
584 (TM.getCodeModel() == CodeModel::Large ||
585 TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
586 Opcode == X86::TAILJMPd;
587 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
588 MO.getOffset(), 0, NeedStub);
589 } else if (MO.isSymbol()) {
590 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
591 } else if (MO.isImm()) {
592 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
593 // Fix up immediate operand for pc relative calls.
594 intptr_t Imm = (intptr_t)MO.getImm();
595 Imm = Imm - MCE.getCurrentPCValue() - 4;
596 emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
598 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
600 assert(0 && "Unknown RawFrm operand!");
605 case X86II::AddRegFrm:
606 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
608 if (CurOp != NumOps) {
609 const MachineOperand &MO1 = MI.getOperand(CurOp++);
610 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
612 emitConstant(MO1.getImm(), Size);
614 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
615 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
616 // This should not occur on Darwin for relocatable objects.
617 if (Opcode == X86::MOV64ri)
618 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
619 if (MO1.isGlobal()) {
620 bool NeedStub = isa<Function>(MO1.getGlobal());
621 bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
622 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
624 } else if (MO1.isSymbol())
625 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
626 else if (MO1.isCPI())
627 emitConstPoolAddress(MO1.getIndex(), rt);
628 else if (MO1.isJTI())
629 emitJumpTableAddress(MO1.getIndex(), rt);
634 case X86II::MRMDestReg: {
635 MCE.emitByte(BaseOpcode);
636 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
637 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
640 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
643 case X86II::MRMDestMem: {
644 MCE.emitByte(BaseOpcode);
645 emitMemModRMByte(MI, CurOp,
646 getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
648 CurOp += X86AddrNumOperands + 1;
650 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
654 case X86II::MRMSrcReg:
655 MCE.emitByte(BaseOpcode);
656 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
657 getX86RegNum(MI.getOperand(CurOp).getReg()));
660 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
663 case X86II::MRMSrcMem: {
664 intptr_t PCAdj = (CurOp + X86AddrNumOperands + 1 != NumOps) ?
665 X86InstrInfo::sizeOfImm(Desc) : 0;
667 MCE.emitByte(BaseOpcode);
668 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
670 CurOp += X86AddrNumOperands + 1;
672 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
676 case X86II::MRM0r: case X86II::MRM1r:
677 case X86II::MRM2r: case X86II::MRM3r:
678 case X86II::MRM4r: case X86II::MRM5r:
679 case X86II::MRM6r: case X86II::MRM7r: {
680 MCE.emitByte(BaseOpcode);
682 // Special handling of lfence and mfence.
683 if (Desc->getOpcode() == X86::LFENCE ||
684 Desc->getOpcode() == X86::MFENCE)
685 emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
687 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
688 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
690 if (CurOp != NumOps) {
691 const MachineOperand &MO1 = MI.getOperand(CurOp++);
692 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
694 emitConstant(MO1.getImm(), Size);
696 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
697 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
698 if (Opcode == X86::MOV64ri32)
699 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
700 if (MO1.isGlobal()) {
701 bool NeedStub = isa<Function>(MO1.getGlobal());
702 bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
703 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
705 } else if (MO1.isSymbol())
706 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
707 else if (MO1.isCPI())
708 emitConstPoolAddress(MO1.getIndex(), rt);
709 else if (MO1.isJTI())
710 emitJumpTableAddress(MO1.getIndex(), rt);
716 case X86II::MRM0m: case X86II::MRM1m:
717 case X86II::MRM2m: case X86II::MRM3m:
718 case X86II::MRM4m: case X86II::MRM5m:
719 case X86II::MRM6m: case X86II::MRM7m: {
720 intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
721 (MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
723 MCE.emitByte(BaseOpcode);
724 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
726 CurOp += X86AddrNumOperands;
728 if (CurOp != NumOps) {
729 const MachineOperand &MO = MI.getOperand(CurOp++);
730 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
732 emitConstant(MO.getImm(), Size);
734 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
735 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
736 if (Opcode == X86::MOV64mi32)
737 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
739 bool NeedStub = isa<Function>(MO.getGlobal());
740 bool Indirect = gvNeedsNonLazyPtr(MO.getGlobal());
741 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
743 } else if (MO.isSymbol())
744 emitExternalSymbolAddress(MO.getSymbolName(), rt);
746 emitConstPoolAddress(MO.getIndex(), rt);
748 emitJumpTableAddress(MO.getIndex(), rt);
754 case X86II::MRMInitReg:
755 MCE.emitByte(BaseOpcode);
756 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
757 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
758 getX86RegNum(MI.getOperand(CurOp).getReg()));
763 if (!Desc->isVariadic() && CurOp != NumOps) {
764 cerr << "Cannot encode: ";