1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86TargetMachine.h"
19 #include "X86Relocations.h"
21 #include "llvm/PassManager.h"
22 #include "llvm/CodeGen/MachineCodeEmitter.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/Function.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Target/TargetOptions.h"
32 STATISTIC(NumEmitted, "Number of machine instructions emitted");
35 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
36 const X86InstrInfo *II;
39 MachineCodeEmitter &MCE;
43 explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
44 : MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
45 MCE(mce), Is64BitMode(false) {}
46 Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
47 const X86InstrInfo &ii, const TargetData &td, bool is64)
48 : MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
49 MCE(mce), Is64BitMode(is64) {}
51 bool runOnMachineFunction(MachineFunction &MF);
53 virtual const char *getPassName() const {
54 return "X86 Machine Code Emitter";
57 void emitInstruction(const MachineInstr &MI);
60 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
61 void emitPCRelativeValue(intptr_t Address);
62 void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
63 void emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
64 int Disp = 0, unsigned PCAdj = 0);
65 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
66 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
68 void emitJumpTableAddress(unsigned JTI, unsigned Reloc, unsigned PCAdj = 0);
70 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
73 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
74 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
75 void emitConstant(uint64_t Val, unsigned Size);
77 void emitMemModRMByte(const MachineInstr &MI,
78 unsigned Op, unsigned RegOpcodeField,
81 unsigned getX86RegNum(unsigned RegNo);
82 bool isX86_64ExtendedReg(const MachineOperand &MO);
83 unsigned determineREX(const MachineInstr &MI);
88 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
89 /// to the specified MCE object.
90 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
91 MachineCodeEmitter &MCE) {
92 return new Emitter(TM, MCE);
95 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
96 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
97 MF.getTarget().getRelocationModel() != Reloc::Static) &&
98 "JIT relocation model must be set to static or default!");
99 II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
100 TD = ((X86TargetMachine&)MF.getTarget()).getTargetData();
102 ((X86TargetMachine&)MF.getTarget()).getSubtarget<X86Subtarget>().is64Bit();
105 MCE.startFunction(MF);
106 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
108 MCE.StartMachineBasicBlock(MBB);
109 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
113 } while (MCE.finishFunction(MF));
118 /// emitPCRelativeValue - Emit a PC relative address.
120 void Emitter::emitPCRelativeValue(intptr_t Address) {
121 MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
124 /// emitPCRelativeBlockAddress - This method keeps track of the information
125 /// necessary to resolve the address of this block later and emits a dummy
128 void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
129 // Remember where this reference was and where it is to so we can
130 // deal with it later.
131 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
132 X86::reloc_pcrel_word, MBB));
136 /// emitGlobalAddressForCall - Emit the specified address to the code stream
137 /// assuming this is part of a function call, which is PC relative.
139 void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
140 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
141 X86::reloc_pcrel_word, GV, 0,
146 /// emitGlobalAddress - Emit the specified address to the code stream assuming
147 /// this is part of a "take the address of a global" instruction.
149 void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
151 unsigned PCAdj /* = 0 */) {
152 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
154 if (Reloc == X86::reloc_absolute_dword)
156 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
159 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
160 /// be emitted to the current location in the function, and allow it to be PC
162 void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
163 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
165 if (Reloc == X86::reloc_absolute_dword)
170 /// emitConstPoolAddress - Arrange for the address of an constant pool
171 /// to be emitted to the current location in the function, and allow it to be PC
173 void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
175 unsigned PCAdj /* = 0 */) {
176 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
178 if (Reloc == X86::reloc_absolute_dword)
180 MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
183 /// emitJumpTableAddress - Arrange for the address of a jump table to
184 /// be emitted to the current location in the function, and allow it to be PC
186 void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
187 unsigned PCAdj /* = 0 */) {
188 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
190 if (Reloc == X86::reloc_absolute_dword)
192 MCE.emitWordLE(0); // The relocated value will be added to the displacement
195 unsigned Emitter::getX86RegNum(unsigned RegNo) {
196 return ((X86RegisterInfo&)II->getRegisterInfo()).getX86RegNum(RegNo);
199 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
201 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
202 return RM | (RegOpcode << 3) | (Mod << 6);
205 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
206 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
209 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
210 // SIB byte is in the same format as the ModRMByte...
211 MCE.emitByte(ModRMByte(SS, Index, Base));
214 void Emitter::emitConstant(uint64_t Val, unsigned Size) {
215 // Output the constant in little endian byte order...
216 for (unsigned i = 0; i != Size; ++i) {
217 MCE.emitByte(Val & 255);
222 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
223 /// sign-extended field.
224 static bool isDisp8(int Value) {
225 return Value == (signed char)Value;
228 void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
229 int DispVal, unsigned PCAdj) {
230 // If this is a simple integer displacement that doesn't require a relocation,
233 emitConstant(DispVal, 4);
237 // Otherwise, this is something that requires a relocation. Emit it as such
239 if (RelocOp->isGlobalAddress()) {
240 // In 64-bit static small code model, we could potentially emit absolute.
241 // But it's probably not beneficial.
242 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
243 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
244 unsigned rt= Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
245 emitGlobalAddressForPtr(RelocOp->getGlobal(), rt,
246 RelocOp->getOffset(), PCAdj);
247 } else if (RelocOp->isConstantPoolIndex()) {
248 // Must be in 64-bit mode.
249 emitConstPoolAddress(RelocOp->getConstantPoolIndex(), X86::reloc_pcrel_word,
250 RelocOp->getOffset(), PCAdj);
251 } else if (RelocOp->isJumpTableIndex()) {
252 // Must be in 64-bit mode.
253 emitJumpTableAddress(RelocOp->getJumpTableIndex(), X86::reloc_pcrel_word,
256 assert(0 && "Unknown value to relocate!");
260 void Emitter::emitMemModRMByte(const MachineInstr &MI,
261 unsigned Op, unsigned RegOpcodeField,
263 const MachineOperand &Op3 = MI.getOperand(Op+3);
265 const MachineOperand *DispForReloc = 0;
267 // Figure out what sort of displacement we have to handle here.
268 if (Op3.isGlobalAddress()) {
270 } else if (Op3.isConstantPoolIndex()) {
274 DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
275 DispVal += Op3.getOffset();
277 } else if (Op3.isJumpTableIndex()) {
281 DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
284 DispVal = Op3.getImm();
287 const MachineOperand &Base = MI.getOperand(Op);
288 const MachineOperand &Scale = MI.getOperand(Op+1);
289 const MachineOperand &IndexReg = MI.getOperand(Op+2);
291 unsigned BaseReg = Base.getReg();
293 // Is a SIB byte needed?
294 if (IndexReg.getReg() == 0 &&
295 (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
296 if (BaseReg == 0) { // Just a displacement?
297 // Emit special case [disp32] encoding
298 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
300 emitDisplacementField(DispForReloc, DispVal, PCAdj);
302 unsigned BaseRegNo = getX86RegNum(BaseReg);
303 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
304 // Emit simple indirect register encoding... [EAX] f.e.
305 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
306 } else if (!DispForReloc && isDisp8(DispVal)) {
307 // Emit the disp8 encoding... [REG+disp8]
308 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
309 emitConstant(DispVal, 1);
311 // Emit the most general non-SIB encoding: [REG+disp32]
312 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
313 emitDisplacementField(DispForReloc, DispVal, PCAdj);
317 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
318 assert(IndexReg.getReg() != X86::ESP &&
319 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
321 bool ForceDisp32 = false;
322 bool ForceDisp8 = false;
324 // If there is no base register, we emit the special case SIB byte with
325 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
326 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
328 } else if (DispForReloc) {
329 // Emit the normal disp32 encoding.
330 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
332 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
333 // Emit no displacement ModR/M byte
334 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
335 } else if (isDisp8(DispVal)) {
336 // Emit the disp8 encoding...
337 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
338 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
340 // Emit the normal disp32 encoding...
341 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
344 // Calculate what the SS field value should be...
345 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
346 unsigned SS = SSTable[Scale.getImm()];
349 // Handle the SIB byte for the case where there is no base. The
350 // displacement has already been output.
351 assert(IndexReg.getReg() && "Index register must be specified!");
352 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
354 unsigned BaseRegNo = getX86RegNum(BaseReg);
356 if (IndexReg.getReg())
357 IndexRegNo = getX86RegNum(IndexReg.getReg());
359 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
360 emitSIBByte(SS, IndexRegNo, BaseRegNo);
363 // Do we need to output a displacement?
365 emitConstant(DispVal, 1);
366 } else if (DispVal != 0 || ForceDisp32) {
367 emitDisplacementField(DispForReloc, DispVal, PCAdj);
372 static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
373 switch (Desc->TSFlags & X86II::ImmMask) {
374 case X86II::Imm8: return 1;
375 case X86II::Imm16: return 2;
376 case X86II::Imm32: return 4;
377 case X86II::Imm64: return 8;
378 default: assert(0 && "Immediate size not set!");
383 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
384 /// e.g. r8, xmm8, etc.
385 bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
386 if (!MO.isRegister()) return false;
387 unsigned RegNo = MO.getReg();
388 switch (MO.getReg()) {
390 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
391 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
392 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
393 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
394 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
395 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
396 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
397 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
398 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
399 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
405 inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
406 return (reg == X86::SPL || reg == X86::BPL ||
407 reg == X86::SIL || reg == X86::DIL);
410 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
411 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
412 /// size, and 3) use of X86-64 extended registers.
413 unsigned Emitter::determineREX(const MachineInstr &MI) {
415 const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
417 // Pseudo instructions do not need REX prefix byte.
418 if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
420 if (Desc->TSFlags & X86II::REX_W)
423 unsigned NumOps = Desc->numOperands;
425 bool isTwoAddr = NumOps > 1 &&
426 Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
428 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
429 unsigned i = isTwoAddr ? 1 : 0;
430 for (unsigned e = NumOps; i != e; ++i) {
431 const MachineOperand& MO = MI.getOperand(i);
432 if (MO.isRegister()) {
433 unsigned Reg = MO.getReg();
434 if (isX86_64NonExtLowByteReg(Reg))
439 switch (Desc->TSFlags & X86II::FormMask) {
440 case X86II::MRMInitReg:
441 if (isX86_64ExtendedReg(MI.getOperand(0)))
442 REX |= (1 << 0) | (1 << 2);
444 case X86II::MRMSrcReg: {
445 if (isX86_64ExtendedReg(MI.getOperand(0)))
447 i = isTwoAddr ? 2 : 1;
448 for (unsigned e = NumOps; i != e; ++i) {
449 const MachineOperand& MO = MI.getOperand(i);
450 if (isX86_64ExtendedReg(MO))
455 case X86II::MRMSrcMem: {
456 if (isX86_64ExtendedReg(MI.getOperand(0)))
459 i = isTwoAddr ? 2 : 1;
460 for (; i != NumOps; ++i) {
461 const MachineOperand& MO = MI.getOperand(i);
462 if (MO.isRegister()) {
463 if (isX86_64ExtendedReg(MO))
470 case X86II::MRM0m: case X86II::MRM1m:
471 case X86II::MRM2m: case X86II::MRM3m:
472 case X86II::MRM4m: case X86II::MRM5m:
473 case X86II::MRM6m: case X86II::MRM7m:
474 case X86II::MRMDestMem: {
475 unsigned e = isTwoAddr ? 5 : 4;
476 i = isTwoAddr ? 1 : 0;
477 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
480 for (; i != e; ++i) {
481 const MachineOperand& MO = MI.getOperand(i);
482 if (MO.isRegister()) {
483 if (isX86_64ExtendedReg(MO))
491 if (isX86_64ExtendedReg(MI.getOperand(0)))
493 i = isTwoAddr ? 2 : 1;
494 for (unsigned e = NumOps; i != e; ++i) {
495 const MachineOperand& MO = MI.getOperand(i);
496 if (isX86_64ExtendedReg(MO))
506 void Emitter::emitInstruction(const MachineInstr &MI) {
507 NumEmitted++; // Keep track of the # of mi's emitted
509 const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
510 unsigned Opcode = Desc->Opcode;
512 // Emit the repeat opcode prefix as needed.
513 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
515 // Emit the operand size opcode prefix as needed.
516 if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
518 // Emit the address size opcode prefix as needed.
519 if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
521 bool Need0FPrefix = false;
522 switch (Desc->TSFlags & X86II::Op0Mask) {
524 Need0FPrefix = true; // Two-byte opcode prefix
534 case X86II::REP: break; // already handled.
535 case X86II::XS: // F3 0F
539 case X86II::XD: // F2 0F
543 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
544 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
546 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
547 >> X86II::Op0Shift));
548 break; // Two-byte opcode prefix
549 default: assert(0 && "Invalid prefix!");
550 case 0: break; // No prefix!
555 unsigned REX = determineREX(MI);
557 MCE.emitByte(0x40 | REX);
560 // 0x0F escape code must be emitted just before the opcode.
564 // If this is a two-address instruction, skip one of the register operands.
565 unsigned NumOps = Desc->numOperands;
567 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
570 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
571 switch (Desc->TSFlags & X86II::FormMask) {
572 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
577 assert(0 && "psuedo instructions should be removed before code emission");
578 case TargetInstrInfo::INLINEASM:
579 assert(0 && "JIT does not support inline asm!\n");
580 case TargetInstrInfo::LABEL:
581 assert(0 && "JIT does not support meta labels!\n");
582 case X86::IMPLICIT_USE:
583 case X86::IMPLICIT_DEF:
584 case X86::IMPLICIT_DEF_GR8:
585 case X86::IMPLICIT_DEF_GR16:
586 case X86::IMPLICIT_DEF_GR32:
587 case X86::IMPLICIT_DEF_GR64:
588 case X86::IMPLICIT_DEF_FR32:
589 case X86::IMPLICIT_DEF_FR64:
590 case X86::IMPLICIT_DEF_VR64:
591 case X86::IMPLICIT_DEF_VR128:
592 case X86::FP_REG_KILL:
600 MCE.emitByte(BaseOpcode);
601 if (CurOp != NumOps) {
602 const MachineOperand &MO = MI.getOperand(CurOp++);
603 if (MO.isMachineBasicBlock()) {
604 emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
605 } else if (MO.isGlobalAddress()) {
606 bool NeedStub = Is64BitMode ||
607 Opcode == X86::TAILJMPd ||
608 Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
609 emitGlobalAddressForCall(MO.getGlobal(), !NeedStub);
610 } else if (MO.isExternalSymbol()) {
611 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
612 } else if (MO.isImmediate()) {
613 emitConstant(MO.getImm(), sizeOfImm(Desc));
615 assert(0 && "Unknown RawFrm operand!");
620 case X86II::AddRegFrm:
621 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
623 if (CurOp != NumOps) {
624 const MachineOperand &MO1 = MI.getOperand(CurOp++);
625 unsigned Size = sizeOfImm(Desc);
626 if (MO1.isImmediate())
627 emitConstant(MO1.getImm(), Size);
629 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
630 if (Opcode == X86::MOV64ri)
631 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
632 if (MO1.isGlobalAddress())
633 emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
634 else if (MO1.isExternalSymbol())
635 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
636 else if (MO1.isConstantPoolIndex())
637 emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
638 else if (MO1.isJumpTableIndex())
639 emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
644 case X86II::MRMDestReg: {
645 MCE.emitByte(BaseOpcode);
646 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
647 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
650 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
653 case X86II::MRMDestMem: {
654 MCE.emitByte(BaseOpcode);
655 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
658 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
662 case X86II::MRMSrcReg:
663 MCE.emitByte(BaseOpcode);
664 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
665 getX86RegNum(MI.getOperand(CurOp).getReg()));
668 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
671 case X86II::MRMSrcMem: {
672 unsigned PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0;
674 MCE.emitByte(BaseOpcode);
675 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
679 emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
683 case X86II::MRM0r: case X86II::MRM1r:
684 case X86II::MRM2r: case X86II::MRM3r:
685 case X86II::MRM4r: case X86II::MRM5r:
686 case X86II::MRM6r: case X86II::MRM7r:
687 MCE.emitByte(BaseOpcode);
688 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
689 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
691 if (CurOp != NumOps) {
692 const MachineOperand &MO1 = MI.getOperand(CurOp++);
693 unsigned Size = sizeOfImm(Desc);
694 if (MO1.isImmediate())
695 emitConstant(MO1.getImm(), Size);
697 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
698 : X86::reloc_absolute_word;
699 if (Opcode == X86::MOV64ri32)
700 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
701 if (MO1.isGlobalAddress())
702 emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
703 else if (MO1.isExternalSymbol())
704 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
705 else if (MO1.isConstantPoolIndex())
706 emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
707 else if (MO1.isJumpTableIndex())
708 emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
713 case X86II::MRM0m: case X86II::MRM1m:
714 case X86II::MRM2m: case X86II::MRM3m:
715 case X86II::MRM4m: case X86II::MRM5m:
716 case X86II::MRM6m: case X86II::MRM7m: {
717 unsigned PCAdj = (CurOp+4 != NumOps) ?
718 (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
720 MCE.emitByte(BaseOpcode);
721 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
725 if (CurOp != NumOps) {
726 const MachineOperand &MO = MI.getOperand(CurOp++);
727 unsigned Size = sizeOfImm(Desc);
728 if (MO.isImmediate())
729 emitConstant(MO.getImm(), Size);
731 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
732 : X86::reloc_absolute_word;
733 if (Opcode == X86::MOV64mi32)
734 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
735 if (MO.isGlobalAddress())
736 emitGlobalAddressForPtr(MO.getGlobal(), rt, MO.getOffset());
737 else if (MO.isExternalSymbol())
738 emitExternalSymbolAddress(MO.getSymbolName(), rt);
739 else if (MO.isConstantPoolIndex())
740 emitConstPoolAddress(MO.getConstantPoolIndex(), rt);
741 else if (MO.isJumpTableIndex())
742 emitJumpTableAddress(MO.getJumpTableIndex(), rt);
748 case X86II::MRMInitReg:
749 MCE.emitByte(BaseOpcode);
750 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
751 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
752 getX86RegNum(MI.getOperand(CurOp).getReg()));
757 assert((Desc->Flags & M_VARIABLE_OPS) != 0 ||
758 CurOp == NumOps && "Unknown encoding!");