1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/Support/CallSite.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/GetElementPtrTypeIterator.h"
33 #include "llvm/Target/TargetOptions.h"
38 class X86FastISel : public FastISel {
39 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
40 /// make the right decision when generating code for different targets.
41 const X86Subtarget *Subtarget;
43 /// StackPtr - Register used as the stack pointer.
47 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
48 /// floating point ops.
49 /// When SSE is available, use it for f32 operations.
50 /// When SSE2 is available, use it for f64 operations.
55 explicit X86FastISel(MachineFunction &mf,
56 DenseMap<const Value *, unsigned> &vm,
57 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
58 DenseMap<const AllocaInst *, int> &am,
59 std::vector<std::pair<MachineInstr*, unsigned> > &pn
61 , SmallSet<const Instruction *, 8> &cil
64 : FastISel(mf, vm, bm, am, pn
69 Subtarget = &TM.getSubtarget<X86Subtarget>();
70 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
71 X86ScalarSSEf64 = Subtarget->hasSSE2();
72 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 virtual bool TargetSelectInstruction(const Instruction *I);
77 #include "X86GenFastISel.inc"
80 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
82 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
84 bool X86FastEmitStore(EVT VT, const Value *Val,
85 const X86AddressMode &AM);
86 bool X86FastEmitStore(EVT VT, unsigned Val,
87 const X86AddressMode &AM);
89 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
92 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
93 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
95 bool X86SelectLoad(const Instruction *I);
97 bool X86SelectStore(const Instruction *I);
99 bool X86SelectCmp(const Instruction *I);
101 bool X86SelectZExt(const Instruction *I);
103 bool X86SelectBranch(const Instruction *I);
105 bool X86SelectShift(const Instruction *I);
107 bool X86SelectSelect(const Instruction *I);
109 bool X86SelectTrunc(const Instruction *I);
111 bool X86SelectFPExt(const Instruction *I);
112 bool X86SelectFPTrunc(const Instruction *I);
114 bool X86SelectExtractValue(const Instruction *I);
116 bool X86VisitIntrinsicCall(const IntrinsicInst &I);
117 bool X86SelectCall(const Instruction *I);
119 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false);
121 const X86InstrInfo *getInstrInfo() const {
122 return getTargetMachine()->getInstrInfo();
124 const X86TargetMachine *getTargetMachine() const {
125 return static_cast<const X86TargetMachine *>(&TM);
128 unsigned TargetMaterializeConstant(const Constant *C);
130 unsigned TargetMaterializeAlloca(const AllocaInst *C);
132 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
133 /// computed in an SSE register, not on the X87 floating point stack.
134 bool isScalarFPTypeInSSEReg(EVT VT) const {
135 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
136 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
139 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false);
142 } // end anonymous namespace.
144 bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
145 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
146 if (VT == MVT::Other || !VT.isSimple())
147 // Unhandled type. Halt "fast" selection and bail.
150 // For now, require SSE/SSE2 for performing floating-point operations,
151 // since x87 requires additional work.
152 if (VT == MVT::f64 && !X86ScalarSSEf64)
154 if (VT == MVT::f32 && !X86ScalarSSEf32)
156 // Similarly, no f80 support yet.
159 // We only handle legal types. For example, on x86-32 the instruction
160 // selector contains all of the 64-bit instructions from x86-64,
161 // under the assumption that i64 won't be used if the target doesn't
163 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
166 #include "X86GenCallingConv.inc"
168 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
170 CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC,
172 if (Subtarget->is64Bit()) {
173 if (CC == CallingConv::GHC)
174 return CC_X86_64_GHC;
175 else if (Subtarget->isTargetWin64())
176 return CC_X86_Win64_C;
181 if (CC == CallingConv::X86_FastCall)
182 return CC_X86_32_FastCall;
183 else if (CC == CallingConv::X86_ThisCall)
184 return CC_X86_32_ThisCall;
185 else if (CC == CallingConv::Fast)
186 return CC_X86_32_FastCC;
187 else if (CC == CallingConv::GHC)
188 return CC_X86_32_GHC;
193 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
194 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
195 /// Return true and the result register by reference if it is possible.
196 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
197 unsigned &ResultReg) {
198 // Get opcode and regclass of the output for the given load instruction.
200 const TargetRegisterClass *RC = NULL;
201 switch (VT.getSimpleVT().SimpleTy) {
202 default: return false;
206 RC = X86::GR8RegisterClass;
210 RC = X86::GR16RegisterClass;
214 RC = X86::GR32RegisterClass;
217 // Must be in x86-64 mode.
219 RC = X86::GR64RegisterClass;
222 if (Subtarget->hasSSE1()) {
224 RC = X86::FR32RegisterClass;
227 RC = X86::RFP32RegisterClass;
231 if (Subtarget->hasSSE2()) {
233 RC = X86::FR64RegisterClass;
236 RC = X86::RFP64RegisterClass;
240 // No f80 support yet.
244 ResultReg = createResultReg(RC);
245 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
249 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
250 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
251 /// and a displacement offset, or a GlobalAddress,
252 /// i.e. V. Return true if it is possible.
254 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val,
255 const X86AddressMode &AM) {
256 // Get opcode and regclass of the output for the given store instruction.
258 switch (VT.getSimpleVT().SimpleTy) {
259 case MVT::f80: // No f80 support yet.
260 default: return false;
262 // Mask out all but lowest bit.
263 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
265 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
268 // FALLTHROUGH, handling i1 as i8.
269 case MVT::i8: Opc = X86::MOV8mr; break;
270 case MVT::i16: Opc = X86::MOV16mr; break;
271 case MVT::i32: Opc = X86::MOV32mr; break;
272 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
274 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
277 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
281 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
285 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
286 const X86AddressMode &AM) {
287 // Handle 'null' like i32/i64 0.
288 if (isa<ConstantPointerNull>(Val))
289 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
291 // If this is a store of a simple constant, fold the constant into the store.
292 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
295 switch (VT.getSimpleVT().SimpleTy) {
297 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
298 case MVT::i8: Opc = X86::MOV8mi; break;
299 case MVT::i16: Opc = X86::MOV16mi; break;
300 case MVT::i32: Opc = X86::MOV32mi; break;
302 // Must be a 32-bit sign extended value.
303 if ((int)CI->getSExtValue() == CI->getSExtValue())
304 Opc = X86::MOV64mi32;
309 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
310 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
316 unsigned ValReg = getRegForValue(Val);
320 return X86FastEmitStore(VT, ValReg, AM);
323 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
324 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
325 /// ISD::SIGN_EXTEND).
326 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
327 unsigned Src, EVT SrcVT,
328 unsigned &ResultReg) {
329 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
330 Src, /*TODO: Kill=*/false);
339 /// X86SelectAddress - Attempt to fill in an address from the given value.
341 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
342 const User *U = NULL;
343 unsigned Opcode = Instruction::UserOp1;
344 if (const Instruction *I = dyn_cast<Instruction>(V)) {
345 // Don't walk into other basic blocks; it's possible we haven't
346 // visited them yet, so the instructions may not yet be assigned
347 // virtual registers.
348 if (MBBMap[I->getParent()] != MBB)
351 Opcode = I->getOpcode();
353 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
354 Opcode = C->getOpcode();
358 if (const PointerType *Ty = dyn_cast<PointerType>(V->getType()))
359 if (Ty->getAddressSpace() > 255)
360 // Fast instruction selection doesn't support the special
366 case Instruction::BitCast:
367 // Look past bitcasts.
368 return X86SelectAddress(U->getOperand(0), AM);
370 case Instruction::IntToPtr:
371 // Look past no-op inttoptrs.
372 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
373 return X86SelectAddress(U->getOperand(0), AM);
376 case Instruction::PtrToInt:
377 // Look past no-op ptrtoints.
378 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
379 return X86SelectAddress(U->getOperand(0), AM);
382 case Instruction::Alloca: {
383 // Do static allocas.
384 const AllocaInst *A = cast<AllocaInst>(V);
385 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
386 if (SI != StaticAllocaMap.end()) {
387 AM.BaseType = X86AddressMode::FrameIndexBase;
388 AM.Base.FrameIndex = SI->second;
394 case Instruction::Add: {
395 // Adds of constants are common and easy enough.
396 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
397 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
398 // They have to fit in the 32-bit signed displacement field though.
399 if (isInt<32>(Disp)) {
400 AM.Disp = (uint32_t)Disp;
401 return X86SelectAddress(U->getOperand(0), AM);
407 case Instruction::GetElementPtr: {
408 X86AddressMode SavedAM = AM;
410 // Pattern-match simple GEPs.
411 uint64_t Disp = (int32_t)AM.Disp;
412 unsigned IndexReg = AM.IndexReg;
413 unsigned Scale = AM.Scale;
414 gep_type_iterator GTI = gep_type_begin(U);
415 // Iterate through the indices, folding what we can. Constants can be
416 // folded, and one dynamic index can be handled, if the scale is supported.
417 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
418 i != e; ++i, ++GTI) {
419 const Value *Op = *i;
420 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
421 const StructLayout *SL = TD.getStructLayout(STy);
422 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
423 Disp += SL->getElementOffset(Idx);
425 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
426 SmallVector<const Value *, 4> Worklist;
427 Worklist.push_back(Op);
429 Op = Worklist.pop_back_val();
430 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
431 // Constant-offset addressing.
432 Disp += CI->getSExtValue() * S;
433 } else if (isa<AddOperator>(Op) &&
434 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
435 // An add with a constant operand. Fold the constant.
437 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
438 Disp += CI->getSExtValue() * S;
439 // Add the other operand back to the work list.
440 Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
441 } else if (IndexReg == 0 &&
442 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
443 (S == 1 || S == 2 || S == 4 || S == 8)) {
444 // Scaled-index addressing.
446 IndexReg = getRegForGEPIndex(Op).first;
451 goto unsupported_gep;
452 } while (!Worklist.empty());
455 // Check for displacement overflow.
456 if (!isInt<32>(Disp))
458 // Ok, the GEP indices were covered by constant-offset and scaled-index
459 // addressing. Update the address state and move on to examining the base.
460 AM.IndexReg = IndexReg;
462 AM.Disp = (uint32_t)Disp;
463 if (X86SelectAddress(U->getOperand(0), AM))
466 // If we couldn't merge the sub value into this addr mode, revert back to
467 // our address and just match the value instead of completely failing.
471 // Ok, the GEP indices weren't all covered.
476 // Handle constant address.
477 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
478 // Can't handle alternate code models yet.
479 if (TM.getCodeModel() != CodeModel::Small)
482 // RIP-relative addresses can't have additional register operands.
483 if (Subtarget->isPICStyleRIPRel() &&
484 (AM.Base.Reg != 0 || AM.IndexReg != 0))
487 // Can't handle TLS yet.
488 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
489 if (GVar->isThreadLocal())
492 // Okay, we've committed to selecting this global. Set up the basic address.
495 // Allow the subtarget to classify the global.
496 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
498 // If this reference is relative to the pic base, set it now.
499 if (isGlobalRelativeToPICBase(GVFlags)) {
500 // FIXME: How do we know Base.Reg is free??
501 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
504 // Unless the ABI requires an extra load, return a direct reference to
506 if (!isGlobalStubReference(GVFlags)) {
507 if (Subtarget->isPICStyleRIPRel()) {
508 // Use rip-relative addressing if we can. Above we verified that the
509 // base and index registers are unused.
510 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
511 AM.Base.Reg = X86::RIP;
513 AM.GVOpFlags = GVFlags;
517 // Ok, we need to do a load from a stub. If we've already loaded from this
518 // stub, reuse the loaded pointer, otherwise emit the load now.
519 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
521 if (I != LocalValueMap.end() && I->second != 0) {
524 // Issue load from stub.
526 const TargetRegisterClass *RC = NULL;
527 X86AddressMode StubAM;
528 StubAM.Base.Reg = AM.Base.Reg;
530 StubAM.GVOpFlags = GVFlags;
532 if (TLI.getPointerTy() == MVT::i64) {
534 RC = X86::GR64RegisterClass;
536 if (Subtarget->isPICStyleRIPRel())
537 StubAM.Base.Reg = X86::RIP;
540 RC = X86::GR32RegisterClass;
543 LoadReg = createResultReg(RC);
544 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM);
546 // Prevent loading GV stub multiple times in same MBB.
547 LocalValueMap[V] = LoadReg;
550 // Now construct the final address. Note that the Disp, Scale,
551 // and Index values may already be set here.
552 AM.Base.Reg = LoadReg;
557 // If all else fails, try to materialize the value in a register.
558 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
559 if (AM.Base.Reg == 0) {
560 AM.Base.Reg = getRegForValue(V);
561 return AM.Base.Reg != 0;
563 if (AM.IndexReg == 0) {
564 assert(AM.Scale == 1 && "Scale with no index!");
565 AM.IndexReg = getRegForValue(V);
566 return AM.IndexReg != 0;
573 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
575 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
576 const User *U = NULL;
577 unsigned Opcode = Instruction::UserOp1;
578 if (const Instruction *I = dyn_cast<Instruction>(V)) {
579 Opcode = I->getOpcode();
581 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
582 Opcode = C->getOpcode();
588 case Instruction::BitCast:
589 // Look past bitcasts.
590 return X86SelectCallAddress(U->getOperand(0), AM);
592 case Instruction::IntToPtr:
593 // Look past no-op inttoptrs.
594 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
595 return X86SelectCallAddress(U->getOperand(0), AM);
598 case Instruction::PtrToInt:
599 // Look past no-op ptrtoints.
600 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
601 return X86SelectCallAddress(U->getOperand(0), AM);
605 // Handle constant address.
606 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
607 // Can't handle alternate code models yet.
608 if (TM.getCodeModel() != CodeModel::Small)
611 // RIP-relative addresses can't have additional register operands.
612 if (Subtarget->isPICStyleRIPRel() &&
613 (AM.Base.Reg != 0 || AM.IndexReg != 0))
616 // Can't handle TLS or DLLImport.
617 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
618 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage())
621 // Okay, we've committed to selecting this global. Set up the basic address.
624 // No ABI requires an extra load for anything other than DLLImport, which
625 // we rejected above. Return a direct reference to the global.
626 if (Subtarget->isPICStyleRIPRel()) {
627 // Use rip-relative addressing if we can. Above we verified that the
628 // base and index registers are unused.
629 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
630 AM.Base.Reg = X86::RIP;
631 } else if (Subtarget->isPICStyleStubPIC()) {
632 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
633 } else if (Subtarget->isPICStyleGOT()) {
634 AM.GVOpFlags = X86II::MO_GOTOFF;
640 // If all else fails, try to materialize the value in a register.
641 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
642 if (AM.Base.Reg == 0) {
643 AM.Base.Reg = getRegForValue(V);
644 return AM.Base.Reg != 0;
646 if (AM.IndexReg == 0) {
647 assert(AM.Scale == 1 && "Scale with no index!");
648 AM.IndexReg = getRegForValue(V);
649 return AM.IndexReg != 0;
657 /// X86SelectStore - Select and emit code to implement store instructions.
658 bool X86FastISel::X86SelectStore(const Instruction *I) {
660 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
664 if (!X86SelectAddress(I->getOperand(1), AM))
667 return X86FastEmitStore(VT, I->getOperand(0), AM);
670 /// X86SelectLoad - Select and emit code to implement load instructions.
672 bool X86FastISel::X86SelectLoad(const Instruction *I) {
674 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
678 if (!X86SelectAddress(I->getOperand(0), AM))
681 unsigned ResultReg = 0;
682 if (X86FastEmitLoad(VT, AM, ResultReg)) {
683 UpdateValueMap(I, ResultReg);
689 static unsigned X86ChooseCmpOpcode(EVT VT) {
690 switch (VT.getSimpleVT().SimpleTy) {
692 case MVT::i8: return X86::CMP8rr;
693 case MVT::i16: return X86::CMP16rr;
694 case MVT::i32: return X86::CMP32rr;
695 case MVT::i64: return X86::CMP64rr;
696 case MVT::f32: return X86::UCOMISSrr;
697 case MVT::f64: return X86::UCOMISDrr;
701 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
702 /// of the comparison, return an opcode that works for the compare (e.g.
703 /// CMP32ri) otherwise return 0.
704 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
705 switch (VT.getSimpleVT().SimpleTy) {
706 // Otherwise, we can't fold the immediate into this comparison.
708 case MVT::i8: return X86::CMP8ri;
709 case MVT::i16: return X86::CMP16ri;
710 case MVT::i32: return X86::CMP32ri;
712 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
714 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
715 return X86::CMP64ri32;
720 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
722 unsigned Op0Reg = getRegForValue(Op0);
723 if (Op0Reg == 0) return false;
725 // Handle 'null' like i32/i64 0.
726 if (isa<ConstantPointerNull>(Op1))
727 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
729 // We have two options: compare with register or immediate. If the RHS of
730 // the compare is an immediate that we can fold into this compare, use
731 // CMPri, otherwise use CMPrr.
732 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
733 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
734 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
735 .addImm(Op1C->getSExtValue());
740 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
741 if (CompareOpc == 0) return false;
743 unsigned Op1Reg = getRegForValue(Op1);
744 if (Op1Reg == 0) return false;
745 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
750 bool X86FastISel::X86SelectCmp(const Instruction *I) {
751 const CmpInst *CI = cast<CmpInst>(I);
754 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
757 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
759 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
760 switch (CI->getPredicate()) {
761 case CmpInst::FCMP_OEQ: {
762 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
765 unsigned EReg = createResultReg(&X86::GR8RegClass);
766 unsigned NPReg = createResultReg(&X86::GR8RegClass);
767 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
768 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
770 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
771 UpdateValueMap(I, ResultReg);
774 case CmpInst::FCMP_UNE: {
775 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
778 unsigned NEReg = createResultReg(&X86::GR8RegClass);
779 unsigned PReg = createResultReg(&X86::GR8RegClass);
780 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
781 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
782 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
783 UpdateValueMap(I, ResultReg);
786 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
787 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
788 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
789 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
790 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
791 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
792 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
793 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
794 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
795 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
796 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
797 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
799 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
800 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
801 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
802 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
803 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
804 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
805 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
806 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
807 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
808 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
813 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
817 // Emit a compare of Op0/Op1.
818 if (!X86FastEmitCompare(Op0, Op1, VT))
821 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
822 UpdateValueMap(I, ResultReg);
826 bool X86FastISel::X86SelectZExt(const Instruction *I) {
827 // Handle zero-extension from i1 to i8, which is common.
828 if (I->getType()->isIntegerTy(8) &&
829 I->getOperand(0)->getType()->isIntegerTy(1)) {
830 unsigned ResultReg = getRegForValue(I->getOperand(0));
831 if (ResultReg == 0) return false;
832 // Set the high bits to zero.
833 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
834 if (ResultReg == 0) return false;
835 UpdateValueMap(I, ResultReg);
843 bool X86FastISel::X86SelectBranch(const Instruction *I) {
844 // Unconditional branches are selected by tablegen-generated code.
845 // Handle a conditional branch.
846 const BranchInst *BI = cast<BranchInst>(I);
847 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
848 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
850 // Fold the common case of a conditional branch with a comparison.
851 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
852 if (CI->hasOneUse()) {
853 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
855 // Try to take advantage of fallthrough opportunities.
856 CmpInst::Predicate Predicate = CI->getPredicate();
857 if (MBB->isLayoutSuccessor(TrueMBB)) {
858 std::swap(TrueMBB, FalseMBB);
859 Predicate = CmpInst::getInversePredicate(Predicate);
862 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
863 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
866 case CmpInst::FCMP_OEQ:
867 std::swap(TrueMBB, FalseMBB);
868 Predicate = CmpInst::FCMP_UNE;
870 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
871 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
872 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
873 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
874 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
875 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
876 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
877 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
878 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
879 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
880 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
881 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
882 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
884 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
885 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
886 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
887 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
888 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
889 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
890 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
891 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
892 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
893 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
898 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
902 // Emit a compare of the LHS and RHS, setting the flags.
903 if (!X86FastEmitCompare(Op0, Op1, VT))
906 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
908 if (Predicate == CmpInst::FCMP_UNE) {
909 // X86 requires a second branch to handle UNE (and OEQ,
910 // which is mapped to UNE above).
911 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
914 FastEmitBranch(FalseMBB, DL);
915 MBB->addSuccessor(TrueMBB);
918 } else if (ExtractValueInst *EI =
919 dyn_cast<ExtractValueInst>(BI->getCondition())) {
920 // Check to see if the branch instruction is from an "arithmetic with
921 // overflow" intrinsic. The main way these intrinsics are used is:
923 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
924 // %sum = extractvalue { i32, i1 } %t, 0
925 // %obit = extractvalue { i32, i1 } %t, 1
926 // br i1 %obit, label %overflow, label %normal
928 // The %sum and %obit are converted in an ADD and a SETO/SETB before
929 // reaching the branch. Therefore, we search backwards through the MBB
930 // looking for the SETO/SETB instruction. If an instruction modifies the
931 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
932 // convert the branch into a JO/JB instruction.
933 if (const IntrinsicInst *CI =
934 dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
935 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
936 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
937 const MachineInstr *SetMI = 0;
938 unsigned Reg = lookUpRegForValue(EI);
940 for (MachineBasicBlock::const_reverse_iterator
941 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
942 const MachineInstr &MI = *RI;
944 if (MI.definesRegister(Reg)) {
945 unsigned Src, Dst, SrcSR, DstSR;
947 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
956 const TargetInstrDesc &TID = MI.getDesc();
957 if (TID.hasUnmodeledSideEffects() ||
958 TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
963 unsigned OpCode = SetMI->getOpcode();
965 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
966 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
967 X86::JO_4 : X86::JB_4))
969 FastEmitBranch(FalseMBB, DL);
970 MBB->addSuccessor(TrueMBB);
978 // Otherwise do a clumsy setcc and re-test it.
979 unsigned OpReg = getRegForValue(BI->getCondition());
980 if (OpReg == 0) return false;
982 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
983 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
984 FastEmitBranch(FalseMBB, DL);
985 MBB->addSuccessor(TrueMBB);
989 bool X86FastISel::X86SelectShift(const Instruction *I) {
990 unsigned CReg = 0, OpReg = 0, OpImm = 0;
991 const TargetRegisterClass *RC = NULL;
992 if (I->getType()->isIntegerTy(8)) {
994 RC = &X86::GR8RegClass;
995 switch (I->getOpcode()) {
996 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
997 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
998 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
999 default: return false;
1001 } else if (I->getType()->isIntegerTy(16)) {
1003 RC = &X86::GR16RegClass;
1004 switch (I->getOpcode()) {
1005 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
1006 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
1007 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
1008 default: return false;
1010 } else if (I->getType()->isIntegerTy(32)) {
1012 RC = &X86::GR32RegClass;
1013 switch (I->getOpcode()) {
1014 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
1015 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
1016 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
1017 default: return false;
1019 } else if (I->getType()->isIntegerTy(64)) {
1021 RC = &X86::GR64RegClass;
1022 switch (I->getOpcode()) {
1023 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
1024 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
1025 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
1026 default: return false;
1032 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1033 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1036 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1037 if (Op0Reg == 0) return false;
1039 // Fold immediate in shl(x,3).
1040 if (const ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
1041 unsigned ResultReg = createResultReg(RC);
1042 BuildMI(MBB, DL, TII.get(OpImm),
1043 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
1044 UpdateValueMap(I, ResultReg);
1048 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1049 if (Op1Reg == 0) return false;
1050 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC, DL);
1052 // The shift instruction uses X86::CL. If we defined a super-register
1053 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
1054 // we're doing here.
1055 if (CReg != X86::CL)
1056 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL)
1057 .addReg(CReg).addImm(X86::sub_8bit);
1059 unsigned ResultReg = createResultReg(RC);
1060 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
1061 UpdateValueMap(I, ResultReg);
1065 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1066 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1067 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1071 const TargetRegisterClass *RC = NULL;
1072 if (VT.getSimpleVT() == MVT::i16) {
1073 Opc = X86::CMOVE16rr;
1074 RC = &X86::GR16RegClass;
1075 } else if (VT.getSimpleVT() == MVT::i32) {
1076 Opc = X86::CMOVE32rr;
1077 RC = &X86::GR32RegClass;
1078 } else if (VT.getSimpleVT() == MVT::i64) {
1079 Opc = X86::CMOVE64rr;
1080 RC = &X86::GR64RegClass;
1085 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1086 if (Op0Reg == 0) return false;
1087 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1088 if (Op1Reg == 0) return false;
1089 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1090 if (Op2Reg == 0) return false;
1092 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
1093 unsigned ResultReg = createResultReg(RC);
1094 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
1095 UpdateValueMap(I, ResultReg);
1099 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
1100 // fpext from float to double.
1101 if (Subtarget->hasSSE2() &&
1102 I->getType()->isDoubleTy()) {
1103 const Value *V = I->getOperand(0);
1104 if (V->getType()->isFloatTy()) {
1105 unsigned OpReg = getRegForValue(V);
1106 if (OpReg == 0) return false;
1107 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1108 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
1109 UpdateValueMap(I, ResultReg);
1117 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
1118 if (Subtarget->hasSSE2()) {
1119 if (I->getType()->isFloatTy()) {
1120 const Value *V = I->getOperand(0);
1121 if (V->getType()->isDoubleTy()) {
1122 unsigned OpReg = getRegForValue(V);
1123 if (OpReg == 0) return false;
1124 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1125 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
1126 UpdateValueMap(I, ResultReg);
1135 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
1136 if (Subtarget->is64Bit())
1137 // All other cases should be handled by the tblgen generated code.
1139 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1140 EVT DstVT = TLI.getValueType(I->getType());
1142 // This code only handles truncation to byte right now.
1143 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1144 // All other cases should be handled by the tblgen generated code.
1146 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
1147 // All other cases should be handled by the tblgen generated code.
1150 unsigned InputReg = getRegForValue(I->getOperand(0));
1152 // Unhandled operand. Halt "fast" selection and bail.
1155 // First issue a copy to GR16_ABCD or GR32_ABCD.
1156 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
1157 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1158 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1159 unsigned CopyReg = createResultReg(CopyRC);
1160 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1162 // Then issue an extract_subreg.
1163 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1164 CopyReg, /*Kill=*/true,
1169 UpdateValueMap(I, ResultReg);
1173 bool X86FastISel::X86SelectExtractValue(const Instruction *I) {
1174 const ExtractValueInst *EI = cast<ExtractValueInst>(I);
1175 const Value *Agg = EI->getAggregateOperand();
1177 if (const IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1178 switch (CI->getIntrinsicID()) {
1180 case Intrinsic::sadd_with_overflow:
1181 case Intrinsic::uadd_with_overflow:
1182 // Cheat a little. We know that the registers for "add" and "seto" are
1183 // allocated sequentially. However, we only keep track of the register
1184 // for "add" in the value map. Use extractvalue's index to get the
1185 // correct register for "seto".
1186 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1194 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
1195 // FIXME: Handle more intrinsics.
1196 switch (I.getIntrinsicID()) {
1197 default: return false;
1198 case Intrinsic::stackprotector: {
1199 // Emit code inline code to store the stack guard onto the stack.
1200 EVT PtrTy = TLI.getPointerTy();
1202 const Value *Op1 = I.getArgOperand(0); // The guard's value.
1203 const AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
1205 // Grab the frame index.
1207 if (!X86SelectAddress(Slot, AM)) return false;
1209 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
1213 case Intrinsic::objectsize: {
1214 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
1215 const Type *Ty = I.getCalledFunction()->getReturnType();
1217 assert(CI && "Non-constant type in Intrinsic::objectsize?");
1220 if (!isTypeLegal(Ty, VT))
1226 else if (VT == MVT::i64)
1231 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1232 BuildMI(MBB, DL, TII.get(OpC), ResultReg).
1233 addImm(CI->isZero() ? -1ULL : 0);
1234 UpdateValueMap(&I, ResultReg);
1237 case Intrinsic::dbg_declare: {
1238 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I);
1240 assert(DI->getAddress() && "Null address should be checked earlier!");
1241 if (!X86SelectAddress(DI->getAddress(), AM))
1243 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1244 // FIXME may need to add RegState::Debug to any registers produced,
1245 // although ESP/EBP should be the only ones at the moment.
1246 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0).
1247 addMetadata(DI->getVariable());
1250 case Intrinsic::trap: {
1251 BuildMI(MBB, DL, TII.get(X86::TRAP));
1254 case Intrinsic::sadd_with_overflow:
1255 case Intrinsic::uadd_with_overflow: {
1256 // Replace "add with overflow" intrinsics with an "add" instruction followed
1257 // by a seto/setc instruction. Later on, when the "extractvalue"
1258 // instructions are encountered, we use the fact that two registers were
1259 // created sequentially to get the correct registers for the "sum" and the
1261 const Function *Callee = I.getCalledFunction();
1263 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1266 if (!isTypeLegal(RetTy, VT))
1269 const Value *Op1 = I.getArgOperand(0);
1270 const Value *Op2 = I.getArgOperand(1);
1271 unsigned Reg1 = getRegForValue(Op1);
1272 unsigned Reg2 = getRegForValue(Op2);
1274 if (Reg1 == 0 || Reg2 == 0)
1275 // FIXME: Handle values *not* in registers.
1281 else if (VT == MVT::i64)
1286 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1287 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1288 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1290 // If the add with overflow is an intra-block value then we just want to
1291 // create temporaries for it like normal. If it is a cross-block value then
1292 // UpdateValueMap will return the cross-block register used. Since we
1293 // *really* want the value to be live in the register pair known by
1294 // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1295 // the cross block case. In the non-cross-block case, we should just make
1296 // another register for the value.
1297 if (DestReg1 != ResultReg)
1298 ResultReg = DestReg1+1;
1300 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1302 unsigned Opc = X86::SETBr;
1303 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1305 BuildMI(MBB, DL, TII.get(Opc), ResultReg);
1311 bool X86FastISel::X86SelectCall(const Instruction *I) {
1312 const CallInst *CI = cast<CallInst>(I);
1313 const Value *Callee = CI->getCalledValue();
1315 // Can't handle inline asm yet.
1316 if (isa<InlineAsm>(Callee))
1319 // Handle intrinsic calls.
1320 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1321 return X86VisitIntrinsicCall(*II);
1323 // Handle only C and fastcc calling conventions for now.
1324 ImmutableCallSite CS(CI);
1325 CallingConv::ID CC = CS.getCallingConv();
1326 if (CC != CallingConv::C &&
1327 CC != CallingConv::Fast &&
1328 CC != CallingConv::X86_FastCall)
1331 // fastcc with -tailcallopt is intended to provide a guaranteed
1332 // tail call optimization. Fastisel doesn't know how to do that.
1333 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
1336 // Let SDISel handle vararg functions.
1337 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1338 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1339 if (FTy->isVarArg())
1342 // Fast-isel doesn't know about callee-pop yet.
1343 if (Subtarget->IsCalleePop(FTy->isVarArg(), CC))
1346 // Handle *simple* calls for now.
1347 const Type *RetTy = CS.getType();
1349 if (RetTy->isVoidTy())
1350 RetVT = MVT::isVoid;
1351 else if (!isTypeLegal(RetTy, RetVT, true))
1354 // Materialize callee address in a register. FIXME: GV address can be
1355 // handled with a CALLpcrel32 instead.
1356 X86AddressMode CalleeAM;
1357 if (!X86SelectCallAddress(Callee, CalleeAM))
1359 unsigned CalleeOp = 0;
1360 const GlobalValue *GV = 0;
1361 if (CalleeAM.GV != 0) {
1363 } else if (CalleeAM.Base.Reg != 0) {
1364 CalleeOp = CalleeAM.Base.Reg;
1368 // Allow calls which produce i1 results.
1369 bool AndToI1 = false;
1370 if (RetVT == MVT::i1) {
1375 // Deal with call operands first.
1376 SmallVector<const Value *, 8> ArgVals;
1377 SmallVector<unsigned, 8> Args;
1378 SmallVector<EVT, 8> ArgVTs;
1379 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1380 Args.reserve(CS.arg_size());
1381 ArgVals.reserve(CS.arg_size());
1382 ArgVTs.reserve(CS.arg_size());
1383 ArgFlags.reserve(CS.arg_size());
1384 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1386 unsigned Arg = getRegForValue(*i);
1389 ISD::ArgFlagsTy Flags;
1390 unsigned AttrInd = i - CS.arg_begin() + 1;
1391 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1393 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1396 // FIXME: Only handle *easy* calls for now.
1397 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1398 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1399 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1400 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1403 const Type *ArgTy = (*i)->getType();
1405 if (!isTypeLegal(ArgTy, ArgVT))
1407 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1408 Flags.setOrigAlign(OriginalAlignment);
1410 Args.push_back(Arg);
1411 ArgVals.push_back(*i);
1412 ArgVTs.push_back(ArgVT);
1413 ArgFlags.push_back(Flags);
1416 // Analyze operands of the call, assigning locations to each operand.
1417 SmallVector<CCValAssign, 16> ArgLocs;
1418 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext());
1420 // Allocate shadow area for Win64
1421 if (Subtarget->isTargetWin64()) {
1422 CCInfo.AllocateStack(32, 8);
1425 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1427 // Get a count of how many bytes are to be pushed on the stack.
1428 unsigned NumBytes = CCInfo.getNextStackOffset();
1430 // Issue CALLSEQ_START
1431 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1432 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1434 // Process argument: walk the register/memloc assignments, inserting
1436 SmallVector<unsigned, 4> RegArgs;
1437 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1438 CCValAssign &VA = ArgLocs[i];
1439 unsigned Arg = Args[VA.getValNo()];
1440 EVT ArgVT = ArgVTs[VA.getValNo()];
1442 // Promote the value if needed.
1443 switch (VA.getLocInfo()) {
1444 default: llvm_unreachable("Unknown loc info!");
1445 case CCValAssign::Full: break;
1446 case CCValAssign::SExt: {
1447 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1449 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1451 ArgVT = VA.getLocVT();
1454 case CCValAssign::ZExt: {
1455 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1457 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1459 ArgVT = VA.getLocVT();
1462 case CCValAssign::AExt: {
1463 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1466 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1469 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1472 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1473 ArgVT = VA.getLocVT();
1476 case CCValAssign::BCvt: {
1477 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(),
1478 ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false);
1479 assert(BC != 0 && "Failed to emit a bitcast!");
1481 ArgVT = VA.getLocVT();
1486 if (VA.isRegLoc()) {
1487 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1488 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1490 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1492 RegArgs.push_back(VA.getLocReg());
1494 unsigned LocMemOffset = VA.getLocMemOffset();
1496 AM.Base.Reg = StackPtr;
1497 AM.Disp = LocMemOffset;
1498 const Value *ArgVal = ArgVals[VA.getValNo()];
1500 // If this is a really simple value, emit this with the Value* version of
1501 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1502 // can cause us to reevaluate the argument.
1503 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1504 X86FastEmitStore(ArgVT, ArgVal, AM);
1506 X86FastEmitStore(ArgVT, Arg, AM);
1510 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1512 if (Subtarget->isPICStyleGOT()) {
1513 TargetRegisterClass *RC = X86::GR32RegisterClass;
1514 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1515 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC,
1517 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1522 MachineInstrBuilder MIB;
1524 // Register-indirect call.
1525 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r;
1526 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp);
1530 assert(GV && "Not a direct call");
1532 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
1534 // See if we need any target-specific flags on the GV operand.
1535 unsigned char OpFlags = 0;
1537 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1538 // external symbols most go through the PLT in PIC mode. If the symbol
1539 // has hidden or protected visibility, or if it is static or local, then
1540 // we don't need to use the PLT - we can directly call it.
1541 if (Subtarget->isTargetELF() &&
1542 TM.getRelocationModel() == Reloc::PIC_ &&
1543 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1544 OpFlags = X86II::MO_PLT;
1545 } else if (Subtarget->isPICStyleStubAny() &&
1546 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1547 Subtarget->getDarwinVers() < 9) {
1548 // PC-relative references to external symbols should go through $stub,
1549 // unless we're building with the leopard linker or later, which
1550 // automatically synthesizes these stubs.
1551 OpFlags = X86II::MO_DARWIN_STUB;
1555 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags);
1558 // Add an implicit use GOT pointer in EBX.
1559 if (Subtarget->isPICStyleGOT())
1560 MIB.addReg(X86::EBX);
1562 // Add implicit physical register uses to the call.
1563 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1564 MIB.addReg(RegArgs[i]);
1566 // Issue CALLSEQ_END
1567 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1568 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1570 // Now handle call return value (if any).
1571 SmallVector<unsigned, 4> UsedRegs;
1572 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1573 SmallVector<CCValAssign, 16> RVLocs;
1574 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
1575 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1577 // Copy all of the result registers out of their specified physreg.
1578 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1579 EVT CopyVT = RVLocs[0].getValVT();
1580 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1581 TargetRegisterClass *SrcRC = DstRC;
1583 // If this is a call to a function that returns an fp value on the x87 fp
1584 // stack, but where we prefer to use the value in xmm registers, copy it
1585 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1586 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1587 RVLocs[0].getLocReg() == X86::ST1) &&
1588 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1590 SrcRC = X86::RSTRegisterClass;
1591 DstRC = X86::RFP80RegisterClass;
1594 unsigned ResultReg = createResultReg(DstRC);
1595 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1596 RVLocs[0].getLocReg(), DstRC, SrcRC, DL);
1597 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1599 UsedRegs.push_back(RVLocs[0].getLocReg());
1601 if (CopyVT != RVLocs[0].getValVT()) {
1602 // Round the F80 the right size, which also moves to the appropriate xmm
1603 // register. This is accomplished by storing the F80 value in memory and
1604 // then loading it back. Ewww...
1605 EVT ResVT = RVLocs[0].getValVT();
1606 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1607 unsigned MemSize = ResVT.getSizeInBits()/8;
1608 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
1609 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1610 DstRC = ResVT == MVT::f32
1611 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1612 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1613 ResultReg = createResultReg(DstRC);
1614 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1618 // Mask out all but lowest bit for some call which produces an i1.
1619 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1621 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1622 ResultReg = AndResult;
1625 UpdateValueMap(I, ResultReg);
1628 // Set all unused physreg defs as dead.
1629 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1636 X86FastISel::TargetSelectInstruction(const Instruction *I) {
1637 switch (I->getOpcode()) {
1639 case Instruction::Load:
1640 return X86SelectLoad(I);
1641 case Instruction::Store:
1642 return X86SelectStore(I);
1643 case Instruction::ICmp:
1644 case Instruction::FCmp:
1645 return X86SelectCmp(I);
1646 case Instruction::ZExt:
1647 return X86SelectZExt(I);
1648 case Instruction::Br:
1649 return X86SelectBranch(I);
1650 case Instruction::Call:
1651 return X86SelectCall(I);
1652 case Instruction::LShr:
1653 case Instruction::AShr:
1654 case Instruction::Shl:
1655 return X86SelectShift(I);
1656 case Instruction::Select:
1657 return X86SelectSelect(I);
1658 case Instruction::Trunc:
1659 return X86SelectTrunc(I);
1660 case Instruction::FPExt:
1661 return X86SelectFPExt(I);
1662 case Instruction::FPTrunc:
1663 return X86SelectFPTrunc(I);
1664 case Instruction::ExtractValue:
1665 return X86SelectExtractValue(I);
1666 case Instruction::IntToPtr: // Deliberate fall-through.
1667 case Instruction::PtrToInt: {
1668 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1669 EVT DstVT = TLI.getValueType(I->getType());
1670 if (DstVT.bitsGT(SrcVT))
1671 return X86SelectZExt(I);
1672 if (DstVT.bitsLT(SrcVT))
1673 return X86SelectTrunc(I);
1674 unsigned Reg = getRegForValue(I->getOperand(0));
1675 if (Reg == 0) return false;
1676 UpdateValueMap(I, Reg);
1684 unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
1686 if (!isTypeLegal(C->getType(), VT))
1689 // Get opcode and regclass of the output for the given load instruction.
1691 const TargetRegisterClass *RC = NULL;
1692 switch (VT.getSimpleVT().SimpleTy) {
1693 default: return false;
1696 RC = X86::GR8RegisterClass;
1700 RC = X86::GR16RegisterClass;
1704 RC = X86::GR32RegisterClass;
1707 // Must be in x86-64 mode.
1709 RC = X86::GR64RegisterClass;
1712 if (Subtarget->hasSSE1()) {
1714 RC = X86::FR32RegisterClass;
1716 Opc = X86::LD_Fp32m;
1717 RC = X86::RFP32RegisterClass;
1721 if (Subtarget->hasSSE2()) {
1723 RC = X86::FR64RegisterClass;
1725 Opc = X86::LD_Fp64m;
1726 RC = X86::RFP64RegisterClass;
1730 // No f80 support yet.
1734 // Materialize addresses with LEA instructions.
1735 if (isa<GlobalValue>(C)) {
1737 if (X86SelectAddress(C, AM)) {
1738 if (TLI.getPointerTy() == MVT::i32)
1742 unsigned ResultReg = createResultReg(RC);
1743 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1749 // MachineConstantPool wants an explicit alignment.
1750 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1752 // Alignment of vector types. FIXME!
1753 Align = TD.getTypeAllocSize(C->getType());
1756 // x86-32 PIC requires a PIC base register for constant pools.
1757 unsigned PICBase = 0;
1758 unsigned char OpFlag = 0;
1759 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
1760 OpFlag = X86II::MO_PIC_BASE_OFFSET;
1761 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1762 } else if (Subtarget->isPICStyleGOT()) {
1763 OpFlag = X86II::MO_GOTOFF;
1764 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1765 } else if (Subtarget->isPICStyleRIPRel() &&
1766 TM.getCodeModel() == CodeModel::Small) {
1770 // Create the load from the constant pool.
1771 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1772 unsigned ResultReg = createResultReg(RC);
1773 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg),
1774 MCPOffset, PICBase, OpFlag);
1779 unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
1780 // Fail on dynamic allocas. At this point, getRegForValue has already
1781 // checked its CSE maps, so if we're here trying to handle a dynamic
1782 // alloca, we're not going to succeed. X86SelectAddress has a
1783 // check for dynamic allocas, because it's called directly from
1784 // various places, but TargetMaterializeAlloca also needs a check
1785 // in order to avoid recursion between getRegForValue,
1786 // X86SelectAddrss, and TargetMaterializeAlloca.
1787 if (!StaticAllocaMap.count(C))
1791 if (!X86SelectAddress(C, AM))
1793 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1794 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1795 unsigned ResultReg = createResultReg(RC);
1796 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1801 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1802 DenseMap<const Value *, unsigned> &vm,
1803 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1804 DenseMap<const AllocaInst *, int> &am,
1805 std::vector<std::pair<MachineInstr*, unsigned> > &pn
1807 , SmallSet<const Instruction *, 8> &cil
1810 return new X86FastISel(mf, vm, bm, am, pn