1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/Analysis.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/FunctionLoweringInfo.h"
29 #include "llvm/CodeGen/MachineConstantPool.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Support/CallSite.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/GetElementPtrTypeIterator.h"
35 #include "llvm/Target/TargetOptions.h"
40 class X86FastISel : public FastISel {
41 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
42 /// make the right decision when generating code for different targets.
43 const X86Subtarget *Subtarget;
45 /// StackPtr - Register used as the stack pointer.
49 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
50 /// floating point ops.
51 /// When SSE is available, use it for f32 operations.
52 /// When SSE2 is available, use it for f64 operations.
57 explicit X86FastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) {
58 Subtarget = &TM.getSubtarget<X86Subtarget>();
59 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
60 X86ScalarSSEf64 = Subtarget->hasSSE2();
61 X86ScalarSSEf32 = Subtarget->hasSSE1();
64 virtual bool TargetSelectInstruction(const Instruction *I);
66 #include "X86GenFastISel.inc"
69 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
71 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
73 bool X86FastEmitStore(EVT VT, const Value *Val,
74 const X86AddressMode &AM);
75 bool X86FastEmitStore(EVT VT, unsigned Val,
76 const X86AddressMode &AM);
78 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
81 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
82 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
84 bool X86SelectLoad(const Instruction *I);
86 bool X86SelectStore(const Instruction *I);
88 bool X86SelectRet(const Instruction *I);
90 bool X86SelectCmp(const Instruction *I);
92 bool X86SelectZExt(const Instruction *I);
94 bool X86SelectBranch(const Instruction *I);
96 bool X86SelectShift(const Instruction *I);
98 bool X86SelectSelect(const Instruction *I);
100 bool X86SelectTrunc(const Instruction *I);
102 bool X86SelectFPExt(const Instruction *I);
103 bool X86SelectFPTrunc(const Instruction *I);
105 bool X86SelectExtractValue(const Instruction *I);
107 bool X86VisitIntrinsicCall(const IntrinsicInst &I);
108 bool X86SelectCall(const Instruction *I);
110 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false);
111 CCAssignFn *CCAssignFnForRet(CallingConv::ID CC, bool isTailCall = false);
113 const X86InstrInfo *getInstrInfo() const {
114 return getTargetMachine()->getInstrInfo();
116 const X86TargetMachine *getTargetMachine() const {
117 return static_cast<const X86TargetMachine *>(&TM);
120 unsigned TargetMaterializeConstant(const Constant *C);
122 unsigned TargetMaterializeAlloca(const AllocaInst *C);
124 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
125 /// computed in an SSE register, not on the X87 floating point stack.
126 bool isScalarFPTypeInSSEReg(EVT VT) const {
127 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
128 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
131 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false);
134 } // end anonymous namespace.
136 bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
137 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
138 if (VT == MVT::Other || !VT.isSimple())
139 // Unhandled type. Halt "fast" selection and bail.
142 // For now, require SSE/SSE2 for performing floating-point operations,
143 // since x87 requires additional work.
144 if (VT == MVT::f64 && !X86ScalarSSEf64)
146 if (VT == MVT::f32 && !X86ScalarSSEf32)
148 // Similarly, no f80 support yet.
151 // We only handle legal types. For example, on x86-32 the instruction
152 // selector contains all of the 64-bit instructions from x86-64,
153 // under the assumption that i64 won't be used if the target doesn't
155 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
158 #include "X86GenCallingConv.inc"
160 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
162 CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC,
164 if (Subtarget->is64Bit()) {
165 if (CC == CallingConv::GHC)
166 return CC_X86_64_GHC;
167 else if (Subtarget->isTargetWin64())
168 return CC_X86_Win64_C;
173 if (CC == CallingConv::X86_FastCall)
174 return CC_X86_32_FastCall;
175 else if (CC == CallingConv::X86_ThisCall)
176 return CC_X86_32_ThisCall;
177 else if (CC == CallingConv::Fast)
178 return CC_X86_32_FastCC;
179 else if (CC == CallingConv::GHC)
180 return CC_X86_32_GHC;
185 /// CCAssignFnForRet - Selects the correct CCAssignFn for a given calling
187 CCAssignFn *X86FastISel::CCAssignFnForRet(CallingConv::ID CC,
189 if (Subtarget->is64Bit()) {
190 if (Subtarget->isTargetWin64())
191 return RetCC_X86_Win64_C;
193 return RetCC_X86_64_C;
196 return RetCC_X86_32_C;
199 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
200 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
201 /// Return true and the result register by reference if it is possible.
202 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
203 unsigned &ResultReg) {
204 // Get opcode and regclass of the output for the given load instruction.
206 const TargetRegisterClass *RC = NULL;
207 switch (VT.getSimpleVT().SimpleTy) {
208 default: return false;
212 RC = X86::GR8RegisterClass;
216 RC = X86::GR16RegisterClass;
220 RC = X86::GR32RegisterClass;
223 // Must be in x86-64 mode.
225 RC = X86::GR64RegisterClass;
228 if (Subtarget->hasSSE1()) {
230 RC = X86::FR32RegisterClass;
233 RC = X86::RFP32RegisterClass;
237 if (Subtarget->hasSSE2()) {
239 RC = X86::FR64RegisterClass;
242 RC = X86::RFP64RegisterClass;
246 // No f80 support yet.
250 ResultReg = createResultReg(RC);
251 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
252 DL, TII.get(Opc), ResultReg), AM);
256 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
257 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
258 /// and a displacement offset, or a GlobalAddress,
259 /// i.e. V. Return true if it is possible.
261 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val,
262 const X86AddressMode &AM) {
263 // Get opcode and regclass of the output for the given store instruction.
265 switch (VT.getSimpleVT().SimpleTy) {
266 case MVT::f80: // No f80 support yet.
267 default: return false;
269 // Mask out all but lowest bit.
270 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
271 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
272 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
275 // FALLTHROUGH, handling i1 as i8.
276 case MVT::i8: Opc = X86::MOV8mr; break;
277 case MVT::i16: Opc = X86::MOV16mr; break;
278 case MVT::i32: Opc = X86::MOV32mr; break;
279 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
281 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
284 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
288 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
289 DL, TII.get(Opc)), AM).addReg(Val);
293 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
294 const X86AddressMode &AM) {
295 // Handle 'null' like i32/i64 0.
296 if (isa<ConstantPointerNull>(Val))
297 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
299 // If this is a store of a simple constant, fold the constant into the store.
300 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
303 switch (VT.getSimpleVT().SimpleTy) {
305 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
306 case MVT::i8: Opc = X86::MOV8mi; break;
307 case MVT::i16: Opc = X86::MOV16mi; break;
308 case MVT::i32: Opc = X86::MOV32mi; break;
310 // Must be a 32-bit sign extended value.
311 if ((int)CI->getSExtValue() == CI->getSExtValue())
312 Opc = X86::MOV64mi32;
317 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
318 DL, TII.get(Opc)), AM)
319 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
325 unsigned ValReg = getRegForValue(Val);
329 return X86FastEmitStore(VT, ValReg, AM);
332 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
333 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
334 /// ISD::SIGN_EXTEND).
335 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
336 unsigned Src, EVT SrcVT,
337 unsigned &ResultReg) {
338 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
339 Src, /*TODO: Kill=*/false);
348 /// X86SelectAddress - Attempt to fill in an address from the given value.
350 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
351 const User *U = NULL;
352 unsigned Opcode = Instruction::UserOp1;
353 if (const Instruction *I = dyn_cast<Instruction>(V)) {
354 // Don't walk into other basic blocks; it's possible we haven't
355 // visited them yet, so the instructions may not yet be assigned
356 // virtual registers.
357 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
360 Opcode = I->getOpcode();
362 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
363 Opcode = C->getOpcode();
367 if (const PointerType *Ty = dyn_cast<PointerType>(V->getType()))
368 if (Ty->getAddressSpace() > 255)
369 // Fast instruction selection doesn't support the special
375 case Instruction::BitCast:
376 // Look past bitcasts.
377 return X86SelectAddress(U->getOperand(0), AM);
379 case Instruction::IntToPtr:
380 // Look past no-op inttoptrs.
381 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
382 return X86SelectAddress(U->getOperand(0), AM);
385 case Instruction::PtrToInt:
386 // Look past no-op ptrtoints.
387 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
388 return X86SelectAddress(U->getOperand(0), AM);
391 case Instruction::Alloca: {
392 // Do static allocas.
393 const AllocaInst *A = cast<AllocaInst>(V);
394 DenseMap<const AllocaInst*, int>::iterator SI =
395 FuncInfo.StaticAllocaMap.find(A);
396 if (SI != FuncInfo.StaticAllocaMap.end()) {
397 AM.BaseType = X86AddressMode::FrameIndexBase;
398 AM.Base.FrameIndex = SI->second;
404 case Instruction::Add: {
405 // Adds of constants are common and easy enough.
406 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
407 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
408 // They have to fit in the 32-bit signed displacement field though.
409 if (isInt<32>(Disp)) {
410 AM.Disp = (uint32_t)Disp;
411 return X86SelectAddress(U->getOperand(0), AM);
417 case Instruction::GetElementPtr: {
418 X86AddressMode SavedAM = AM;
420 // Pattern-match simple GEPs.
421 uint64_t Disp = (int32_t)AM.Disp;
422 unsigned IndexReg = AM.IndexReg;
423 unsigned Scale = AM.Scale;
424 gep_type_iterator GTI = gep_type_begin(U);
425 // Iterate through the indices, folding what we can. Constants can be
426 // folded, and one dynamic index can be handled, if the scale is supported.
427 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
428 i != e; ++i, ++GTI) {
429 const Value *Op = *i;
430 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
431 const StructLayout *SL = TD.getStructLayout(STy);
432 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
433 Disp += SL->getElementOffset(Idx);
435 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
436 SmallVector<const Value *, 4> Worklist;
437 Worklist.push_back(Op);
439 Op = Worklist.pop_back_val();
440 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
441 // Constant-offset addressing.
442 Disp += CI->getSExtValue() * S;
443 } else if (isa<AddOperator>(Op) &&
444 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
445 // An add with a constant operand. Fold the constant.
447 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
448 Disp += CI->getSExtValue() * S;
449 // Add the other operand back to the work list.
450 Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
451 } else if (IndexReg == 0 &&
452 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
453 (S == 1 || S == 2 || S == 4 || S == 8)) {
454 // Scaled-index addressing.
456 IndexReg = getRegForGEPIndex(Op).first;
461 goto unsupported_gep;
462 } while (!Worklist.empty());
465 // Check for displacement overflow.
466 if (!isInt<32>(Disp))
468 // Ok, the GEP indices were covered by constant-offset and scaled-index
469 // addressing. Update the address state and move on to examining the base.
470 AM.IndexReg = IndexReg;
472 AM.Disp = (uint32_t)Disp;
473 if (X86SelectAddress(U->getOperand(0), AM))
476 // If we couldn't merge the sub value into this addr mode, revert back to
477 // our address and just match the value instead of completely failing.
481 // Ok, the GEP indices weren't all covered.
486 // Handle constant address.
487 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
488 // Can't handle alternate code models yet.
489 if (TM.getCodeModel() != CodeModel::Small)
492 // RIP-relative addresses can't have additional register operands.
493 if (Subtarget->isPICStyleRIPRel() &&
494 (AM.Base.Reg != 0 || AM.IndexReg != 0))
497 // Can't handle TLS yet.
498 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
499 if (GVar->isThreadLocal())
502 // Okay, we've committed to selecting this global. Set up the basic address.
505 // Allow the subtarget to classify the global.
506 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
508 // If this reference is relative to the pic base, set it now.
509 if (isGlobalRelativeToPICBase(GVFlags)) {
510 // FIXME: How do we know Base.Reg is free??
511 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
514 // Unless the ABI requires an extra load, return a direct reference to
516 if (!isGlobalStubReference(GVFlags)) {
517 if (Subtarget->isPICStyleRIPRel()) {
518 // Use rip-relative addressing if we can. Above we verified that the
519 // base and index registers are unused.
520 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
521 AM.Base.Reg = X86::RIP;
523 AM.GVOpFlags = GVFlags;
527 // Ok, we need to do a load from a stub. If we've already loaded from this
528 // stub, reuse the loaded pointer, otherwise emit the load now.
529 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
531 if (I != LocalValueMap.end() && I->second != 0) {
534 // Issue load from stub.
536 const TargetRegisterClass *RC = NULL;
537 X86AddressMode StubAM;
538 StubAM.Base.Reg = AM.Base.Reg;
540 StubAM.GVOpFlags = GVFlags;
542 // Prepare for inserting code in the local-value area.
543 SavePoint SaveInsertPt = enterLocalValueArea();
545 if (TLI.getPointerTy() == MVT::i64) {
547 RC = X86::GR64RegisterClass;
549 if (Subtarget->isPICStyleRIPRel())
550 StubAM.Base.Reg = X86::RIP;
553 RC = X86::GR32RegisterClass;
556 LoadReg = createResultReg(RC);
557 MachineInstrBuilder LoadMI =
558 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg);
559 addFullAddress(LoadMI, StubAM);
561 // Ok, back to normal mode.
562 leaveLocalValueArea(SaveInsertPt);
564 // Prevent loading GV stub multiple times in same MBB.
565 LocalValueMap[V] = LoadReg;
568 // Now construct the final address. Note that the Disp, Scale,
569 // and Index values may already be set here.
570 AM.Base.Reg = LoadReg;
575 // If all else fails, try to materialize the value in a register.
576 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
577 if (AM.Base.Reg == 0) {
578 AM.Base.Reg = getRegForValue(V);
579 return AM.Base.Reg != 0;
581 if (AM.IndexReg == 0) {
582 assert(AM.Scale == 1 && "Scale with no index!");
583 AM.IndexReg = getRegForValue(V);
584 return AM.IndexReg != 0;
591 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
593 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
594 const User *U = NULL;
595 unsigned Opcode = Instruction::UserOp1;
596 if (const Instruction *I = dyn_cast<Instruction>(V)) {
597 Opcode = I->getOpcode();
599 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
600 Opcode = C->getOpcode();
606 case Instruction::BitCast:
607 // Look past bitcasts.
608 return X86SelectCallAddress(U->getOperand(0), AM);
610 case Instruction::IntToPtr:
611 // Look past no-op inttoptrs.
612 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
613 return X86SelectCallAddress(U->getOperand(0), AM);
616 case Instruction::PtrToInt:
617 // Look past no-op ptrtoints.
618 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
619 return X86SelectCallAddress(U->getOperand(0), AM);
623 // Handle constant address.
624 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
625 // Can't handle alternate code models yet.
626 if (TM.getCodeModel() != CodeModel::Small)
629 // RIP-relative addresses can't have additional register operands.
630 if (Subtarget->isPICStyleRIPRel() &&
631 (AM.Base.Reg != 0 || AM.IndexReg != 0))
634 // Can't handle TLS or DLLImport.
635 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
636 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage())
639 // Okay, we've committed to selecting this global. Set up the basic address.
642 // No ABI requires an extra load for anything other than DLLImport, which
643 // we rejected above. Return a direct reference to the global.
644 if (Subtarget->isPICStyleRIPRel()) {
645 // Use rip-relative addressing if we can. Above we verified that the
646 // base and index registers are unused.
647 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
648 AM.Base.Reg = X86::RIP;
649 } else if (Subtarget->isPICStyleStubPIC()) {
650 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
651 } else if (Subtarget->isPICStyleGOT()) {
652 AM.GVOpFlags = X86II::MO_GOTOFF;
658 // If all else fails, try to materialize the value in a register.
659 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
660 if (AM.Base.Reg == 0) {
661 AM.Base.Reg = getRegForValue(V);
662 return AM.Base.Reg != 0;
664 if (AM.IndexReg == 0) {
665 assert(AM.Scale == 1 && "Scale with no index!");
666 AM.IndexReg = getRegForValue(V);
667 return AM.IndexReg != 0;
675 /// X86SelectStore - Select and emit code to implement store instructions.
676 bool X86FastISel::X86SelectStore(const Instruction *I) {
678 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
682 if (!X86SelectAddress(I->getOperand(1), AM))
685 return X86FastEmitStore(VT, I->getOperand(0), AM);
688 /// X86SelectRet - Select and emit code to implement ret instructions.
689 bool X86FastISel::X86SelectRet(const Instruction *I) {
690 const ReturnInst *Ret = cast<ReturnInst>(I);
691 const Function &F = *I->getParent()->getParent();
693 if (!FuncInfo.CanLowerReturn)
696 CallingConv::ID CC = F.getCallingConv();
697 if (CC != CallingConv::C &&
698 CC != CallingConv::Fast &&
699 CC != CallingConv::X86_FastCall)
702 if (Subtarget->isTargetWin64())
705 // Don't handle popping bytes on return for now.
706 if (FuncInfo.MF->getInfo<X86MachineFunctionInfo>()
707 ->getBytesToPopOnReturn() != 0)
710 // fastcc with -tailcallopt is intended to provide a guaranteed
711 // tail call optimization. Fastisel doesn't know how to do that.
712 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
715 // Let SDISel handle vararg functions.
719 if (Ret->getNumOperands() > 0) {
720 SmallVector<ISD::OutputArg, 4> Outs;
721 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
724 // Analyze operands of the call, assigning locations to each operand.
725 SmallVector<CCValAssign, 16> ValLocs;
726 CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
727 CCInfo.AnalyzeReturn(Outs, CCAssignFnForRet(CC));
729 const Value *RV = Ret->getOperand(0);
730 unsigned Reg = getRegForValue(RV);
734 // Only handle a single return value for now.
735 if (ValLocs.size() != 1)
738 CCValAssign &VA = ValLocs[0];
740 // Don't bother handling odd stuff for now.
741 if (VA.getLocInfo() != CCValAssign::Full)
743 // Only handle register returns for now.
746 // TODO: For now, don't try to handle cases where getLocInfo()
747 // says Full but the types don't match.
748 if (VA.getValVT() != TLI.getValueType(RV->getType()))
751 // The calling-convention tables for x87 returns don't tell
753 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
757 unsigned SrcReg = Reg + VA.getValNo();
758 unsigned DstReg = VA.getLocReg();
759 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
760 // Avoid a cross-class copy. This is very unlikely.
761 if (!SrcRC->contains(DstReg))
763 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
764 DstReg).addReg(SrcReg);
766 // Mark the register as live out of the function.
767 MRI.addLiveOut(VA.getLocReg());
771 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
775 /// X86SelectLoad - Select and emit code to implement load instructions.
777 bool X86FastISel::X86SelectLoad(const Instruction *I) {
779 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
783 if (!X86SelectAddress(I->getOperand(0), AM))
786 unsigned ResultReg = 0;
787 if (X86FastEmitLoad(VT, AM, ResultReg)) {
788 UpdateValueMap(I, ResultReg);
794 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) {
795 switch (VT.getSimpleVT().SimpleTy) {
797 case MVT::i8: return X86::CMP8rr;
798 case MVT::i16: return X86::CMP16rr;
799 case MVT::i32: return X86::CMP32rr;
800 case MVT::i64: return X86::CMP64rr;
801 case MVT::f32: return Subtarget->hasSSE1() ? X86::UCOMISSrr : 0;
802 case MVT::f64: return Subtarget->hasSSE2() ? X86::UCOMISDrr : 0;
806 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
807 /// of the comparison, return an opcode that works for the compare (e.g.
808 /// CMP32ri) otherwise return 0.
809 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
810 switch (VT.getSimpleVT().SimpleTy) {
811 // Otherwise, we can't fold the immediate into this comparison.
813 case MVT::i8: return X86::CMP8ri;
814 case MVT::i16: return X86::CMP16ri;
815 case MVT::i32: return X86::CMP32ri;
817 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
819 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
820 return X86::CMP64ri32;
825 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
827 unsigned Op0Reg = getRegForValue(Op0);
828 if (Op0Reg == 0) return false;
830 // Handle 'null' like i32/i64 0.
831 if (isa<ConstantPointerNull>(Op1))
832 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
834 // We have two options: compare with register or immediate. If the RHS of
835 // the compare is an immediate that we can fold into this compare, use
836 // CMPri, otherwise use CMPrr.
837 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
838 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
839 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
841 .addImm(Op1C->getSExtValue());
846 unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget);
847 if (CompareOpc == 0) return false;
849 unsigned Op1Reg = getRegForValue(Op1);
850 if (Op1Reg == 0) return false;
851 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc))
858 bool X86FastISel::X86SelectCmp(const Instruction *I) {
859 const CmpInst *CI = cast<CmpInst>(I);
862 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
865 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
867 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
868 switch (CI->getPredicate()) {
869 case CmpInst::FCMP_OEQ: {
870 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
873 unsigned EReg = createResultReg(&X86::GR8RegClass);
874 unsigned NPReg = createResultReg(&X86::GR8RegClass);
875 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
876 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
877 TII.get(X86::SETNPr), NPReg);
878 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
879 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
880 UpdateValueMap(I, ResultReg);
883 case CmpInst::FCMP_UNE: {
884 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
887 unsigned NEReg = createResultReg(&X86::GR8RegClass);
888 unsigned PReg = createResultReg(&X86::GR8RegClass);
889 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
890 TII.get(X86::SETNEr), NEReg);
891 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
892 TII.get(X86::SETPr), PReg);
893 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
894 TII.get(X86::OR8rr), ResultReg)
895 .addReg(PReg).addReg(NEReg);
896 UpdateValueMap(I, ResultReg);
899 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
900 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
901 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
902 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
903 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
904 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
905 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
906 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
907 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
908 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
909 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
910 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
912 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
913 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
914 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
915 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
916 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
917 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
918 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
919 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
920 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
921 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
926 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
930 // Emit a compare of Op0/Op1.
931 if (!X86FastEmitCompare(Op0, Op1, VT))
934 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg);
935 UpdateValueMap(I, ResultReg);
939 bool X86FastISel::X86SelectZExt(const Instruction *I) {
940 // Handle zero-extension from i1 to i8, which is common.
941 if (I->getType()->isIntegerTy(8) &&
942 I->getOperand(0)->getType()->isIntegerTy(1)) {
943 unsigned ResultReg = getRegForValue(I->getOperand(0));
944 if (ResultReg == 0) return false;
945 // Set the high bits to zero.
946 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
947 if (ResultReg == 0) return false;
948 UpdateValueMap(I, ResultReg);
956 bool X86FastISel::X86SelectBranch(const Instruction *I) {
957 // Unconditional branches are selected by tablegen-generated code.
958 // Handle a conditional branch.
959 const BranchInst *BI = cast<BranchInst>(I);
960 MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
961 MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
963 // Fold the common case of a conditional branch with a comparison.
964 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
965 if (CI->hasOneUse()) {
966 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
968 // Try to take advantage of fallthrough opportunities.
969 CmpInst::Predicate Predicate = CI->getPredicate();
970 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
971 std::swap(TrueMBB, FalseMBB);
972 Predicate = CmpInst::getInversePredicate(Predicate);
975 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
976 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
979 case CmpInst::FCMP_OEQ:
980 std::swap(TrueMBB, FalseMBB);
981 Predicate = CmpInst::FCMP_UNE;
983 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
984 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
985 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
986 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
987 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
988 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
989 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
990 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
991 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
992 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
993 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
994 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
995 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
997 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
998 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
999 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1000 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1001 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1002 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1003 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
1004 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
1005 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
1006 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
1011 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
1013 std::swap(Op0, Op1);
1015 // Emit a compare of the LHS and RHS, setting the flags.
1016 if (!X86FastEmitCompare(Op0, Op1, VT))
1019 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc))
1022 if (Predicate == CmpInst::FCMP_UNE) {
1023 // X86 requires a second branch to handle UNE (and OEQ,
1024 // which is mapped to UNE above).
1025 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
1029 FastEmitBranch(FalseMBB, DL);
1030 FuncInfo.MBB->addSuccessor(TrueMBB);
1033 } else if (ExtractValueInst *EI =
1034 dyn_cast<ExtractValueInst>(BI->getCondition())) {
1035 // Check to see if the branch instruction is from an "arithmetic with
1036 // overflow" intrinsic. The main way these intrinsics are used is:
1038 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
1039 // %sum = extractvalue { i32, i1 } %t, 0
1040 // %obit = extractvalue { i32, i1 } %t, 1
1041 // br i1 %obit, label %overflow, label %normal
1043 // The %sum and %obit are converted in an ADD and a SETO/SETB before
1044 // reaching the branch. Therefore, we search backwards through the MBB
1045 // looking for the SETO/SETB instruction. If an instruction modifies the
1046 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
1047 // convert the branch into a JO/JB instruction.
1048 if (const IntrinsicInst *CI =
1049 dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
1050 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
1051 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
1052 const MachineInstr *SetMI = 0;
1053 unsigned Reg = getRegForValue(EI);
1055 for (MachineBasicBlock::const_reverse_iterator
1056 RI = FuncInfo.MBB->rbegin(), RE = FuncInfo.MBB->rend();
1058 const MachineInstr &MI = *RI;
1060 if (MI.definesRegister(Reg)) {
1062 Reg = MI.getOperand(1).getReg();
1070 const TargetInstrDesc &TID = MI.getDesc();
1071 if (TID.hasUnmodeledSideEffects() ||
1072 TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
1077 unsigned OpCode = SetMI->getOpcode();
1079 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
1080 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1081 TII.get(OpCode == X86::SETOr ? X86::JO_4 : X86::JB_4))
1083 FastEmitBranch(FalseMBB, DL);
1084 FuncInfo.MBB->addSuccessor(TrueMBB);
1092 // Otherwise do a clumsy setcc and re-test it.
1093 unsigned OpReg = getRegForValue(BI->getCondition());
1094 if (OpReg == 0) return false;
1096 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1097 .addReg(OpReg).addReg(OpReg);
1098 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1100 FastEmitBranch(FalseMBB, DL);
1101 FuncInfo.MBB->addSuccessor(TrueMBB);
1105 bool X86FastISel::X86SelectShift(const Instruction *I) {
1106 unsigned CReg = 0, OpReg = 0, OpImm = 0;
1107 const TargetRegisterClass *RC = NULL;
1108 if (I->getType()->isIntegerTy(8)) {
1110 RC = &X86::GR8RegClass;
1111 switch (I->getOpcode()) {
1112 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
1113 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
1114 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
1115 default: return false;
1117 } else if (I->getType()->isIntegerTy(16)) {
1119 RC = &X86::GR16RegClass;
1120 switch (I->getOpcode()) {
1121 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
1122 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
1123 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
1124 default: return false;
1126 } else if (I->getType()->isIntegerTy(32)) {
1128 RC = &X86::GR32RegClass;
1129 switch (I->getOpcode()) {
1130 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
1131 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
1132 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
1133 default: return false;
1135 } else if (I->getType()->isIntegerTy(64)) {
1137 RC = &X86::GR64RegClass;
1138 switch (I->getOpcode()) {
1139 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
1140 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
1141 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
1142 default: return false;
1148 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1149 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1152 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1153 if (Op0Reg == 0) return false;
1155 // Fold immediate in shl(x,3).
1156 if (const ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
1157 unsigned ResultReg = createResultReg(RC);
1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpImm),
1159 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
1160 UpdateValueMap(I, ResultReg);
1164 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1165 if (Op1Reg == 0) return false;
1166 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1167 CReg).addReg(Op1Reg);
1169 // The shift instruction uses X86::CL. If we defined a super-register
1170 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1171 if (CReg != X86::CL)
1172 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1173 TII.get(TargetOpcode::KILL), X86::CL)
1174 .addReg(CReg, RegState::Kill);
1176 unsigned ResultReg = createResultReg(RC);
1177 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg)
1179 UpdateValueMap(I, ResultReg);
1183 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1184 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1185 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1189 const TargetRegisterClass *RC = NULL;
1190 if (VT.getSimpleVT() == MVT::i16) {
1191 Opc = X86::CMOVE16rr;
1192 RC = &X86::GR16RegClass;
1193 } else if (VT.getSimpleVT() == MVT::i32) {
1194 Opc = X86::CMOVE32rr;
1195 RC = &X86::GR32RegClass;
1196 } else if (VT.getSimpleVT() == MVT::i64) {
1197 Opc = X86::CMOVE64rr;
1198 RC = &X86::GR64RegClass;
1203 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1204 if (Op0Reg == 0) return false;
1205 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1206 if (Op1Reg == 0) return false;
1207 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1208 if (Op2Reg == 0) return false;
1210 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1211 .addReg(Op0Reg).addReg(Op0Reg);
1212 unsigned ResultReg = createResultReg(RC);
1213 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1214 .addReg(Op1Reg).addReg(Op2Reg);
1215 UpdateValueMap(I, ResultReg);
1219 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
1220 // fpext from float to double.
1221 if (Subtarget->hasSSE2() &&
1222 I->getType()->isDoubleTy()) {
1223 const Value *V = I->getOperand(0);
1224 if (V->getType()->isFloatTy()) {
1225 unsigned OpReg = getRegForValue(V);
1226 if (OpReg == 0) return false;
1227 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1228 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1229 TII.get(X86::CVTSS2SDrr), ResultReg)
1231 UpdateValueMap(I, ResultReg);
1239 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
1240 if (Subtarget->hasSSE2()) {
1241 if (I->getType()->isFloatTy()) {
1242 const Value *V = I->getOperand(0);
1243 if (V->getType()->isDoubleTy()) {
1244 unsigned OpReg = getRegForValue(V);
1245 if (OpReg == 0) return false;
1246 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1247 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1248 TII.get(X86::CVTSD2SSrr), ResultReg)
1250 UpdateValueMap(I, ResultReg);
1259 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
1260 if (Subtarget->is64Bit())
1261 // All other cases should be handled by the tblgen generated code.
1263 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1264 EVT DstVT = TLI.getValueType(I->getType());
1266 // This code only handles truncation to byte right now.
1267 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1268 // All other cases should be handled by the tblgen generated code.
1270 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
1271 // All other cases should be handled by the tblgen generated code.
1274 unsigned InputReg = getRegForValue(I->getOperand(0));
1276 // Unhandled operand. Halt "fast" selection and bail.
1279 // First issue a copy to GR16_ABCD or GR32_ABCD.
1280 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1281 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1282 unsigned CopyReg = createResultReg(CopyRC);
1283 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1284 CopyReg).addReg(InputReg);
1286 // Then issue an extract_subreg.
1287 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1288 CopyReg, /*Kill=*/true,
1293 UpdateValueMap(I, ResultReg);
1297 bool X86FastISel::X86SelectExtractValue(const Instruction *I) {
1298 const ExtractValueInst *EI = cast<ExtractValueInst>(I);
1299 const Value *Agg = EI->getAggregateOperand();
1301 if (const IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1302 switch (CI->getIntrinsicID()) {
1304 case Intrinsic::sadd_with_overflow:
1305 case Intrinsic::uadd_with_overflow: {
1306 // Cheat a little. We know that the registers for "add" and "seto" are
1307 // allocated sequentially. However, we only keep track of the register
1308 // for "add" in the value map. Use extractvalue's index to get the
1309 // correct register for "seto".
1310 unsigned OpReg = getRegForValue(Agg);
1313 UpdateValueMap(I, OpReg + *EI->idx_begin());
1322 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
1323 // FIXME: Handle more intrinsics.
1324 switch (I.getIntrinsicID()) {
1325 default: return false;
1326 case Intrinsic::stackprotector: {
1327 // Emit code inline code to store the stack guard onto the stack.
1328 EVT PtrTy = TLI.getPointerTy();
1330 const Value *Op1 = I.getArgOperand(0); // The guard's value.
1331 const AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
1333 // Grab the frame index.
1335 if (!X86SelectAddress(Slot, AM)) return false;
1337 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
1341 case Intrinsic::objectsize: {
1342 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
1343 const Type *Ty = I.getCalledFunction()->getReturnType();
1345 assert(CI && "Non-constant type in Intrinsic::objectsize?");
1348 if (!isTypeLegal(Ty, VT))
1354 else if (VT == MVT::i64)
1359 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1360 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg).
1361 addImm(CI->isZero() ? -1ULL : 0);
1362 UpdateValueMap(&I, ResultReg);
1365 case Intrinsic::dbg_declare: {
1366 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I);
1368 assert(DI->getAddress() && "Null address should be checked earlier!");
1369 if (!X86SelectAddress(DI->getAddress(), AM))
1371 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1372 // FIXME may need to add RegState::Debug to any registers produced,
1373 // although ESP/EBP should be the only ones at the moment.
1374 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM).
1375 addImm(0).addMetadata(DI->getVariable());
1378 case Intrinsic::trap: {
1379 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1382 case Intrinsic::sadd_with_overflow:
1383 case Intrinsic::uadd_with_overflow: {
1384 // Replace "add with overflow" intrinsics with an "add" instruction followed
1385 // by a seto/setc instruction. Later on, when the "extractvalue"
1386 // instructions are encountered, we use the fact that two registers were
1387 // created sequentially to get the correct registers for the "sum" and the
1389 const Function *Callee = I.getCalledFunction();
1391 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1394 if (!isTypeLegal(RetTy, VT))
1397 const Value *Op1 = I.getArgOperand(0);
1398 const Value *Op2 = I.getArgOperand(1);
1399 unsigned Reg1 = getRegForValue(Op1);
1400 unsigned Reg2 = getRegForValue(Op2);
1402 if (Reg1 == 0 || Reg2 == 0)
1403 // FIXME: Handle values *not* in registers.
1409 else if (VT == MVT::i64)
1414 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1415 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg)
1416 .addReg(Reg1).addReg(Reg2);
1417 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1419 // If the add with overflow is an intra-block value then we just want to
1420 // create temporaries for it like normal. If it is a cross-block value then
1421 // UpdateValueMap will return the cross-block register used. Since we
1422 // *really* want the value to be live in the register pair known by
1423 // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1424 // the cross block case. In the non-cross-block case, we should just make
1425 // another register for the value.
1426 if (DestReg1 != ResultReg)
1427 ResultReg = DestReg1+1;
1429 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1431 unsigned Opc = X86::SETBr;
1432 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1434 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg);
1440 bool X86FastISel::X86SelectCall(const Instruction *I) {
1441 const CallInst *CI = cast<CallInst>(I);
1442 const Value *Callee = CI->getCalledValue();
1444 // Can't handle inline asm yet.
1445 if (isa<InlineAsm>(Callee))
1448 // Handle intrinsic calls.
1449 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1450 return X86VisitIntrinsicCall(*II);
1452 // Handle only C and fastcc calling conventions for now.
1453 ImmutableCallSite CS(CI);
1454 CallingConv::ID CC = CS.getCallingConv();
1455 if (CC != CallingConv::C &&
1456 CC != CallingConv::Fast &&
1457 CC != CallingConv::X86_FastCall)
1460 // fastcc with -tailcallopt is intended to provide a guaranteed
1461 // tail call optimization. Fastisel doesn't know how to do that.
1462 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
1465 // Let SDISel handle vararg functions.
1466 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1467 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1468 if (FTy->isVarArg())
1471 // Fast-isel doesn't know about callee-pop yet.
1472 if (Subtarget->IsCalleePop(FTy->isVarArg(), CC))
1475 // Handle *simple* calls for now.
1476 const Type *RetTy = CS.getType();
1478 if (RetTy->isVoidTy())
1479 RetVT = MVT::isVoid;
1480 else if (!isTypeLegal(RetTy, RetVT, true))
1483 // Materialize callee address in a register. FIXME: GV address can be
1484 // handled with a CALLpcrel32 instead.
1485 X86AddressMode CalleeAM;
1486 if (!X86SelectCallAddress(Callee, CalleeAM))
1488 unsigned CalleeOp = 0;
1489 const GlobalValue *GV = 0;
1490 if (CalleeAM.GV != 0) {
1492 } else if (CalleeAM.Base.Reg != 0) {
1493 CalleeOp = CalleeAM.Base.Reg;
1497 // Allow calls which produce i1 results.
1498 bool AndToI1 = false;
1499 if (RetVT == MVT::i1) {
1504 // Deal with call operands first.
1505 SmallVector<const Value *, 8> ArgVals;
1506 SmallVector<unsigned, 8> Args;
1507 SmallVector<EVT, 8> ArgVTs;
1508 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1509 Args.reserve(CS.arg_size());
1510 ArgVals.reserve(CS.arg_size());
1511 ArgVTs.reserve(CS.arg_size());
1512 ArgFlags.reserve(CS.arg_size());
1513 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1515 unsigned Arg = getRegForValue(*i);
1518 ISD::ArgFlagsTy Flags;
1519 unsigned AttrInd = i - CS.arg_begin() + 1;
1520 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1522 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1525 // FIXME: Only handle *easy* calls for now.
1526 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1527 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1528 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1529 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1532 const Type *ArgTy = (*i)->getType();
1534 if (!isTypeLegal(ArgTy, ArgVT))
1536 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1537 Flags.setOrigAlign(OriginalAlignment);
1539 Args.push_back(Arg);
1540 ArgVals.push_back(*i);
1541 ArgVTs.push_back(ArgVT);
1542 ArgFlags.push_back(Flags);
1545 // Analyze operands of the call, assigning locations to each operand.
1546 SmallVector<CCValAssign, 16> ArgLocs;
1547 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext());
1549 // Allocate shadow area for Win64
1550 if (Subtarget->isTargetWin64()) {
1551 CCInfo.AllocateStack(32, 8);
1554 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1556 // Get a count of how many bytes are to be pushed on the stack.
1557 unsigned NumBytes = CCInfo.getNextStackOffset();
1559 // Issue CALLSEQ_START
1560 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1561 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
1564 // Process argument: walk the register/memloc assignments, inserting
1566 SmallVector<unsigned, 4> RegArgs;
1567 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1568 CCValAssign &VA = ArgLocs[i];
1569 unsigned Arg = Args[VA.getValNo()];
1570 EVT ArgVT = ArgVTs[VA.getValNo()];
1572 // Promote the value if needed.
1573 switch (VA.getLocInfo()) {
1574 default: llvm_unreachable("Unknown loc info!");
1575 case CCValAssign::Full: break;
1576 case CCValAssign::SExt: {
1577 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1579 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1581 ArgVT = VA.getLocVT();
1584 case CCValAssign::ZExt: {
1585 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1587 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1589 ArgVT = VA.getLocVT();
1592 case CCValAssign::AExt: {
1593 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1596 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1599 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1602 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1603 ArgVT = VA.getLocVT();
1606 case CCValAssign::BCvt: {
1607 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(),
1608 ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false);
1609 assert(BC != 0 && "Failed to emit a bitcast!");
1611 ArgVT = VA.getLocVT();
1616 if (VA.isRegLoc()) {
1617 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1618 VA.getLocReg()).addReg(Arg);
1619 RegArgs.push_back(VA.getLocReg());
1621 unsigned LocMemOffset = VA.getLocMemOffset();
1623 AM.Base.Reg = StackPtr;
1624 AM.Disp = LocMemOffset;
1625 const Value *ArgVal = ArgVals[VA.getValNo()];
1627 // If this is a really simple value, emit this with the Value* version of
1628 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1629 // can cause us to reevaluate the argument.
1630 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1631 X86FastEmitStore(ArgVT, ArgVal, AM);
1633 X86FastEmitStore(ArgVT, Arg, AM);
1637 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1639 if (Subtarget->isPICStyleGOT()) {
1640 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1641 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1642 X86::EBX).addReg(Base);
1646 MachineInstrBuilder MIB;
1648 // Register-indirect call.
1649 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r;
1650 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1655 assert(GV && "Not a direct call");
1657 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
1659 // See if we need any target-specific flags on the GV operand.
1660 unsigned char OpFlags = 0;
1662 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1663 // external symbols most go through the PLT in PIC mode. If the symbol
1664 // has hidden or protected visibility, or if it is static or local, then
1665 // we don't need to use the PLT - we can directly call it.
1666 if (Subtarget->isTargetELF() &&
1667 TM.getRelocationModel() == Reloc::PIC_ &&
1668 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1669 OpFlags = X86II::MO_PLT;
1670 } else if (Subtarget->isPICStyleStubAny() &&
1671 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1672 Subtarget->getDarwinVers() < 9) {
1673 // PC-relative references to external symbols should go through $stub,
1674 // unless we're building with the leopard linker or later, which
1675 // automatically synthesizes these stubs.
1676 OpFlags = X86II::MO_DARWIN_STUB;
1680 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1681 .addGlobalAddress(GV, 0, OpFlags);
1684 // Add an implicit use GOT pointer in EBX.
1685 if (Subtarget->isPICStyleGOT())
1686 MIB.addReg(X86::EBX);
1688 // Add implicit physical register uses to the call.
1689 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1690 MIB.addReg(RegArgs[i]);
1692 // Issue CALLSEQ_END
1693 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1694 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
1695 .addImm(NumBytes).addImm(0);
1697 // Now handle call return value (if any).
1698 SmallVector<unsigned, 4> UsedRegs;
1699 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1700 SmallVector<CCValAssign, 16> RVLocs;
1701 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
1702 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1704 // Copy all of the result registers out of their specified physreg.
1705 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1706 EVT CopyVT = RVLocs[0].getValVT();
1707 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1709 // If this is a call to a function that returns an fp value on the x87 fp
1710 // stack, but where we prefer to use the value in xmm registers, copy it
1711 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1712 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1713 RVLocs[0].getLocReg() == X86::ST1) &&
1714 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1716 DstRC = X86::RFP80RegisterClass;
1719 unsigned ResultReg = createResultReg(DstRC);
1720 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1721 ResultReg).addReg(RVLocs[0].getLocReg());
1722 UsedRegs.push_back(RVLocs[0].getLocReg());
1724 if (CopyVT != RVLocs[0].getValVT()) {
1725 // Round the F80 the right size, which also moves to the appropriate xmm
1726 // register. This is accomplished by storing the F80 value in memory and
1727 // then loading it back. Ewww...
1728 EVT ResVT = RVLocs[0].getValVT();
1729 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1730 unsigned MemSize = ResVT.getSizeInBits()/8;
1731 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
1732 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1735 DstRC = ResVT == MVT::f32
1736 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1737 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1738 ResultReg = createResultReg(DstRC);
1739 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1740 TII.get(Opc), ResultReg), FI);
1744 // Mask out all but lowest bit for some call which produces an i1.
1745 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1746 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1747 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1748 ResultReg = AndResult;
1751 UpdateValueMap(I, ResultReg);
1754 // Set all unused physreg defs as dead.
1755 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1762 X86FastISel::TargetSelectInstruction(const Instruction *I) {
1763 switch (I->getOpcode()) {
1765 case Instruction::Load:
1766 return X86SelectLoad(I);
1767 case Instruction::Store:
1768 return X86SelectStore(I);
1769 case Instruction::Ret:
1770 return X86SelectRet(I);
1771 case Instruction::ICmp:
1772 case Instruction::FCmp:
1773 return X86SelectCmp(I);
1774 case Instruction::ZExt:
1775 return X86SelectZExt(I);
1776 case Instruction::Br:
1777 return X86SelectBranch(I);
1778 case Instruction::Call:
1779 return X86SelectCall(I);
1780 case Instruction::LShr:
1781 case Instruction::AShr:
1782 case Instruction::Shl:
1783 return X86SelectShift(I);
1784 case Instruction::Select:
1785 return X86SelectSelect(I);
1786 case Instruction::Trunc:
1787 return X86SelectTrunc(I);
1788 case Instruction::FPExt:
1789 return X86SelectFPExt(I);
1790 case Instruction::FPTrunc:
1791 return X86SelectFPTrunc(I);
1792 case Instruction::ExtractValue:
1793 return X86SelectExtractValue(I);
1794 case Instruction::IntToPtr: // Deliberate fall-through.
1795 case Instruction::PtrToInt: {
1796 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1797 EVT DstVT = TLI.getValueType(I->getType());
1798 if (DstVT.bitsGT(SrcVT))
1799 return X86SelectZExt(I);
1800 if (DstVT.bitsLT(SrcVT))
1801 return X86SelectTrunc(I);
1802 unsigned Reg = getRegForValue(I->getOperand(0));
1803 if (Reg == 0) return false;
1804 UpdateValueMap(I, Reg);
1812 unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
1814 if (!isTypeLegal(C->getType(), VT))
1817 // Get opcode and regclass of the output for the given load instruction.
1819 const TargetRegisterClass *RC = NULL;
1820 switch (VT.getSimpleVT().SimpleTy) {
1821 default: return false;
1824 RC = X86::GR8RegisterClass;
1828 RC = X86::GR16RegisterClass;
1832 RC = X86::GR32RegisterClass;
1835 // Must be in x86-64 mode.
1837 RC = X86::GR64RegisterClass;
1840 if (Subtarget->hasSSE1()) {
1842 RC = X86::FR32RegisterClass;
1844 Opc = X86::LD_Fp32m;
1845 RC = X86::RFP32RegisterClass;
1849 if (Subtarget->hasSSE2()) {
1851 RC = X86::FR64RegisterClass;
1853 Opc = X86::LD_Fp64m;
1854 RC = X86::RFP64RegisterClass;
1858 // No f80 support yet.
1862 // Materialize addresses with LEA instructions.
1863 if (isa<GlobalValue>(C)) {
1865 if (X86SelectAddress(C, AM)) {
1866 if (TLI.getPointerTy() == MVT::i32)
1870 unsigned ResultReg = createResultReg(RC);
1871 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1872 TII.get(Opc), ResultReg), AM);
1878 // MachineConstantPool wants an explicit alignment.
1879 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1881 // Alignment of vector types. FIXME!
1882 Align = TD.getTypeAllocSize(C->getType());
1885 // x86-32 PIC requires a PIC base register for constant pools.
1886 unsigned PICBase = 0;
1887 unsigned char OpFlag = 0;
1888 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
1889 OpFlag = X86II::MO_PIC_BASE_OFFSET;
1890 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1891 } else if (Subtarget->isPICStyleGOT()) {
1892 OpFlag = X86II::MO_GOTOFF;
1893 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1894 } else if (Subtarget->isPICStyleRIPRel() &&
1895 TM.getCodeModel() == CodeModel::Small) {
1899 // Create the load from the constant pool.
1900 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1901 unsigned ResultReg = createResultReg(RC);
1902 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1903 TII.get(Opc), ResultReg),
1904 MCPOffset, PICBase, OpFlag);
1909 unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
1910 // Fail on dynamic allocas. At this point, getRegForValue has already
1911 // checked its CSE maps, so if we're here trying to handle a dynamic
1912 // alloca, we're not going to succeed. X86SelectAddress has a
1913 // check for dynamic allocas, because it's called directly from
1914 // various places, but TargetMaterializeAlloca also needs a check
1915 // in order to avoid recursion between getRegForValue,
1916 // X86SelectAddrss, and TargetMaterializeAlloca.
1917 if (!FuncInfo.StaticAllocaMap.count(C))
1921 if (!X86SelectAddress(C, AM))
1923 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1924 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1925 unsigned ResultReg = createResultReg(RC);
1926 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1927 TII.get(Opc), ResultReg), AM);
1932 llvm::FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo) {
1933 return new X86FastISel(funcInfo);