1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/Analysis.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/FunctionLoweringInfo.h"
29 #include "llvm/CodeGen/MachineConstantPool.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Support/CallSite.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/GetElementPtrTypeIterator.h"
35 #include "llvm/Target/TargetOptions.h"
40 class X86FastISel : public FastISel {
41 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
42 /// make the right decision when generating code for different targets.
43 const X86Subtarget *Subtarget;
45 /// StackPtr - Register used as the stack pointer.
49 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
50 /// floating point ops.
51 /// When SSE is available, use it for f32 operations.
52 /// When SSE2 is available, use it for f64 operations.
57 explicit X86FastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) {
58 Subtarget = &TM.getSubtarget<X86Subtarget>();
59 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
60 X86ScalarSSEf64 = Subtarget->hasSSE2();
61 X86ScalarSSEf32 = Subtarget->hasSSE1();
64 virtual bool TargetSelectInstruction(const Instruction *I);
66 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
67 /// vreg is being provided by the specified load instruction. If possible,
68 /// try to fold the load as an operand to the instruction, returning true if
70 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
73 #include "X86GenFastISel.inc"
76 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
78 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
80 bool X86FastEmitStore(EVT VT, const Value *Val,
81 const X86AddressMode &AM);
82 bool X86FastEmitStore(EVT VT, unsigned Val,
83 const X86AddressMode &AM);
85 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
88 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
89 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
91 bool X86SelectLoad(const Instruction *I);
93 bool X86SelectStore(const Instruction *I);
95 bool X86SelectRet(const Instruction *I);
97 bool X86SelectCmp(const Instruction *I);
99 bool X86SelectZExt(const Instruction *I);
101 bool X86SelectBranch(const Instruction *I);
103 bool X86SelectShift(const Instruction *I);
105 bool X86SelectSelect(const Instruction *I);
107 bool X86SelectTrunc(const Instruction *I);
109 bool X86SelectFPExt(const Instruction *I);
110 bool X86SelectFPTrunc(const Instruction *I);
112 bool X86SelectExtractValue(const Instruction *I);
114 bool X86VisitIntrinsicCall(const IntrinsicInst &I);
115 bool X86SelectCall(const Instruction *I);
117 const X86InstrInfo *getInstrInfo() const {
118 return getTargetMachine()->getInstrInfo();
120 const X86TargetMachine *getTargetMachine() const {
121 return static_cast<const X86TargetMachine *>(&TM);
124 unsigned TargetMaterializeConstant(const Constant *C);
126 unsigned TargetMaterializeAlloca(const AllocaInst *C);
128 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
129 /// computed in an SSE register, not on the X87 floating point stack.
130 bool isScalarFPTypeInSSEReg(EVT VT) const {
131 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
132 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
135 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false);
138 } // end anonymous namespace.
140 bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
141 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
142 if (VT == MVT::Other || !VT.isSimple())
143 // Unhandled type. Halt "fast" selection and bail.
146 // For now, require SSE/SSE2 for performing floating-point operations,
147 // since x87 requires additional work.
148 if (VT == MVT::f64 && !X86ScalarSSEf64)
150 if (VT == MVT::f32 && !X86ScalarSSEf32)
152 // Similarly, no f80 support yet.
155 // We only handle legal types. For example, on x86-32 the instruction
156 // selector contains all of the 64-bit instructions from x86-64,
157 // under the assumption that i64 won't be used if the target doesn't
159 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
162 #include "X86GenCallingConv.inc"
164 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
165 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
166 /// Return true and the result register by reference if it is possible.
167 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
168 unsigned &ResultReg) {
169 // Get opcode and regclass of the output for the given load instruction.
171 const TargetRegisterClass *RC = NULL;
172 switch (VT.getSimpleVT().SimpleTy) {
173 default: return false;
177 RC = X86::GR8RegisterClass;
181 RC = X86::GR16RegisterClass;
185 RC = X86::GR32RegisterClass;
188 // Must be in x86-64 mode.
190 RC = X86::GR64RegisterClass;
193 if (Subtarget->hasSSE1()) {
195 RC = X86::FR32RegisterClass;
198 RC = X86::RFP32RegisterClass;
202 if (Subtarget->hasSSE2()) {
204 RC = X86::FR64RegisterClass;
207 RC = X86::RFP64RegisterClass;
211 // No f80 support yet.
215 ResultReg = createResultReg(RC);
216 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
217 DL, TII.get(Opc), ResultReg), AM);
221 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
222 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
223 /// and a displacement offset, or a GlobalAddress,
224 /// i.e. V. Return true if it is possible.
226 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val,
227 const X86AddressMode &AM) {
228 // Get opcode and regclass of the output for the given store instruction.
230 switch (VT.getSimpleVT().SimpleTy) {
231 case MVT::f80: // No f80 support yet.
232 default: return false;
234 // Mask out all but lowest bit.
235 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
237 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
240 // FALLTHROUGH, handling i1 as i8.
241 case MVT::i8: Opc = X86::MOV8mr; break;
242 case MVT::i16: Opc = X86::MOV16mr; break;
243 case MVT::i32: Opc = X86::MOV32mr; break;
244 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
246 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
249 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
253 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
254 DL, TII.get(Opc)), AM).addReg(Val);
258 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
259 const X86AddressMode &AM) {
260 // Handle 'null' like i32/i64 0.
261 if (isa<ConstantPointerNull>(Val))
262 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
264 // If this is a store of a simple constant, fold the constant into the store.
265 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
268 switch (VT.getSimpleVT().SimpleTy) {
270 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
271 case MVT::i8: Opc = X86::MOV8mi; break;
272 case MVT::i16: Opc = X86::MOV16mi; break;
273 case MVT::i32: Opc = X86::MOV32mi; break;
275 // Must be a 32-bit sign extended value.
276 if ((int)CI->getSExtValue() == CI->getSExtValue())
277 Opc = X86::MOV64mi32;
282 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
283 DL, TII.get(Opc)), AM)
284 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
290 unsigned ValReg = getRegForValue(Val);
294 return X86FastEmitStore(VT, ValReg, AM);
297 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
298 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
299 /// ISD::SIGN_EXTEND).
300 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
301 unsigned Src, EVT SrcVT,
302 unsigned &ResultReg) {
303 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
304 Src, /*TODO: Kill=*/false);
313 /// X86SelectAddress - Attempt to fill in an address from the given value.
315 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
316 const User *U = NULL;
317 unsigned Opcode = Instruction::UserOp1;
318 if (const Instruction *I = dyn_cast<Instruction>(V)) {
319 // Don't walk into other basic blocks; it's possible we haven't
320 // visited them yet, so the instructions may not yet be assigned
321 // virtual registers.
322 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
325 Opcode = I->getOpcode();
327 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
328 Opcode = C->getOpcode();
332 if (const PointerType *Ty = dyn_cast<PointerType>(V->getType()))
333 if (Ty->getAddressSpace() > 255)
334 // Fast instruction selection doesn't support the special
340 case Instruction::BitCast:
341 // Look past bitcasts.
342 return X86SelectAddress(U->getOperand(0), AM);
344 case Instruction::IntToPtr:
345 // Look past no-op inttoptrs.
346 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
347 return X86SelectAddress(U->getOperand(0), AM);
350 case Instruction::PtrToInt:
351 // Look past no-op ptrtoints.
352 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
353 return X86SelectAddress(U->getOperand(0), AM);
356 case Instruction::Alloca: {
357 // Do static allocas.
358 const AllocaInst *A = cast<AllocaInst>(V);
359 DenseMap<const AllocaInst*, int>::iterator SI =
360 FuncInfo.StaticAllocaMap.find(A);
361 if (SI != FuncInfo.StaticAllocaMap.end()) {
362 AM.BaseType = X86AddressMode::FrameIndexBase;
363 AM.Base.FrameIndex = SI->second;
369 case Instruction::Add: {
370 // Adds of constants are common and easy enough.
371 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
372 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
373 // They have to fit in the 32-bit signed displacement field though.
374 if (isInt<32>(Disp)) {
375 AM.Disp = (uint32_t)Disp;
376 return X86SelectAddress(U->getOperand(0), AM);
382 case Instruction::GetElementPtr: {
383 X86AddressMode SavedAM = AM;
385 // Pattern-match simple GEPs.
386 uint64_t Disp = (int32_t)AM.Disp;
387 unsigned IndexReg = AM.IndexReg;
388 unsigned Scale = AM.Scale;
389 gep_type_iterator GTI = gep_type_begin(U);
390 // Iterate through the indices, folding what we can. Constants can be
391 // folded, and one dynamic index can be handled, if the scale is supported.
392 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
393 i != e; ++i, ++GTI) {
394 const Value *Op = *i;
395 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
396 const StructLayout *SL = TD.getStructLayout(STy);
397 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
398 Disp += SL->getElementOffset(Idx);
400 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
401 SmallVector<const Value *, 4> Worklist;
402 Worklist.push_back(Op);
404 Op = Worklist.pop_back_val();
405 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
406 // Constant-offset addressing.
407 Disp += CI->getSExtValue() * S;
408 } else if (isa<AddOperator>(Op) &&
409 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
410 // An add with a constant operand. Fold the constant.
412 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
413 Disp += CI->getSExtValue() * S;
414 // Add the other operand back to the work list.
415 Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
416 } else if (IndexReg == 0 &&
417 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
418 (S == 1 || S == 2 || S == 4 || S == 8)) {
419 // Scaled-index addressing.
421 IndexReg = getRegForGEPIndex(Op).first;
426 goto unsupported_gep;
427 } while (!Worklist.empty());
430 // Check for displacement overflow.
431 if (!isInt<32>(Disp))
433 // Ok, the GEP indices were covered by constant-offset and scaled-index
434 // addressing. Update the address state and move on to examining the base.
435 AM.IndexReg = IndexReg;
437 AM.Disp = (uint32_t)Disp;
438 if (X86SelectAddress(U->getOperand(0), AM))
441 // If we couldn't merge the sub value into this addr mode, revert back to
442 // our address and just match the value instead of completely failing.
446 // Ok, the GEP indices weren't all covered.
451 // Handle constant address.
452 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
453 // Can't handle alternate code models yet.
454 if (TM.getCodeModel() != CodeModel::Small)
457 // RIP-relative addresses can't have additional register operands.
458 if (Subtarget->isPICStyleRIPRel() &&
459 (AM.Base.Reg != 0 || AM.IndexReg != 0))
462 // Can't handle TLS yet.
463 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
464 if (GVar->isThreadLocal())
467 // Okay, we've committed to selecting this global. Set up the basic address.
470 // Allow the subtarget to classify the global.
471 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
473 // If this reference is relative to the pic base, set it now.
474 if (isGlobalRelativeToPICBase(GVFlags)) {
475 // FIXME: How do we know Base.Reg is free??
476 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
479 // Unless the ABI requires an extra load, return a direct reference to
481 if (!isGlobalStubReference(GVFlags)) {
482 if (Subtarget->isPICStyleRIPRel()) {
483 // Use rip-relative addressing if we can. Above we verified that the
484 // base and index registers are unused.
485 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
486 AM.Base.Reg = X86::RIP;
488 AM.GVOpFlags = GVFlags;
492 // Ok, we need to do a load from a stub. If we've already loaded from this
493 // stub, reuse the loaded pointer, otherwise emit the load now.
494 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
496 if (I != LocalValueMap.end() && I->second != 0) {
499 // Issue load from stub.
501 const TargetRegisterClass *RC = NULL;
502 X86AddressMode StubAM;
503 StubAM.Base.Reg = AM.Base.Reg;
505 StubAM.GVOpFlags = GVFlags;
507 // Prepare for inserting code in the local-value area.
508 SavePoint SaveInsertPt = enterLocalValueArea();
510 if (TLI.getPointerTy() == MVT::i64) {
512 RC = X86::GR64RegisterClass;
514 if (Subtarget->isPICStyleRIPRel())
515 StubAM.Base.Reg = X86::RIP;
518 RC = X86::GR32RegisterClass;
521 LoadReg = createResultReg(RC);
522 MachineInstrBuilder LoadMI =
523 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg);
524 addFullAddress(LoadMI, StubAM);
526 // Ok, back to normal mode.
527 leaveLocalValueArea(SaveInsertPt);
529 // Prevent loading GV stub multiple times in same MBB.
530 LocalValueMap[V] = LoadReg;
533 // Now construct the final address. Note that the Disp, Scale,
534 // and Index values may already be set here.
535 AM.Base.Reg = LoadReg;
540 // If all else fails, try to materialize the value in a register.
541 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
542 if (AM.Base.Reg == 0) {
543 AM.Base.Reg = getRegForValue(V);
544 return AM.Base.Reg != 0;
546 if (AM.IndexReg == 0) {
547 assert(AM.Scale == 1 && "Scale with no index!");
548 AM.IndexReg = getRegForValue(V);
549 return AM.IndexReg != 0;
556 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
558 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
559 const User *U = NULL;
560 unsigned Opcode = Instruction::UserOp1;
561 if (const Instruction *I = dyn_cast<Instruction>(V)) {
562 Opcode = I->getOpcode();
564 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
565 Opcode = C->getOpcode();
571 case Instruction::BitCast:
572 // Look past bitcasts.
573 return X86SelectCallAddress(U->getOperand(0), AM);
575 case Instruction::IntToPtr:
576 // Look past no-op inttoptrs.
577 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
578 return X86SelectCallAddress(U->getOperand(0), AM);
581 case Instruction::PtrToInt:
582 // Look past no-op ptrtoints.
583 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
584 return X86SelectCallAddress(U->getOperand(0), AM);
588 // Handle constant address.
589 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
590 // Can't handle alternate code models yet.
591 if (TM.getCodeModel() != CodeModel::Small)
594 // RIP-relative addresses can't have additional register operands.
595 if (Subtarget->isPICStyleRIPRel() &&
596 (AM.Base.Reg != 0 || AM.IndexReg != 0))
599 // Can't handle TLS or DLLImport.
600 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
601 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage())
604 // Okay, we've committed to selecting this global. Set up the basic address.
607 // No ABI requires an extra load for anything other than DLLImport, which
608 // we rejected above. Return a direct reference to the global.
609 if (Subtarget->isPICStyleRIPRel()) {
610 // Use rip-relative addressing if we can. Above we verified that the
611 // base and index registers are unused.
612 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
613 AM.Base.Reg = X86::RIP;
614 } else if (Subtarget->isPICStyleStubPIC()) {
615 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
616 } else if (Subtarget->isPICStyleGOT()) {
617 AM.GVOpFlags = X86II::MO_GOTOFF;
623 // If all else fails, try to materialize the value in a register.
624 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
625 if (AM.Base.Reg == 0) {
626 AM.Base.Reg = getRegForValue(V);
627 return AM.Base.Reg != 0;
629 if (AM.IndexReg == 0) {
630 assert(AM.Scale == 1 && "Scale with no index!");
631 AM.IndexReg = getRegForValue(V);
632 return AM.IndexReg != 0;
640 /// X86SelectStore - Select and emit code to implement store instructions.
641 bool X86FastISel::X86SelectStore(const Instruction *I) {
643 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
647 if (!X86SelectAddress(I->getOperand(1), AM))
650 return X86FastEmitStore(VT, I->getOperand(0), AM);
653 /// X86SelectRet - Select and emit code to implement ret instructions.
654 bool X86FastISel::X86SelectRet(const Instruction *I) {
655 const ReturnInst *Ret = cast<ReturnInst>(I);
656 const Function &F = *I->getParent()->getParent();
658 if (!FuncInfo.CanLowerReturn)
661 CallingConv::ID CC = F.getCallingConv();
662 if (CC != CallingConv::C &&
663 CC != CallingConv::Fast &&
664 CC != CallingConv::X86_FastCall)
667 if (Subtarget->isTargetWin64())
670 // Don't handle popping bytes on return for now.
671 if (FuncInfo.MF->getInfo<X86MachineFunctionInfo>()
672 ->getBytesToPopOnReturn() != 0)
675 // fastcc with -tailcallopt is intended to provide a guaranteed
676 // tail call optimization. Fastisel doesn't know how to do that.
677 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
680 // Let SDISel handle vararg functions.
684 if (Ret->getNumOperands() > 0) {
685 SmallVector<ISD::OutputArg, 4> Outs;
686 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
689 // Analyze operands of the call, assigning locations to each operand.
690 SmallVector<CCValAssign, 16> ValLocs;
691 CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
692 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
694 const Value *RV = Ret->getOperand(0);
695 unsigned Reg = getRegForValue(RV);
699 // Only handle a single return value for now.
700 if (ValLocs.size() != 1)
703 CCValAssign &VA = ValLocs[0];
705 // Don't bother handling odd stuff for now.
706 if (VA.getLocInfo() != CCValAssign::Full)
708 // Only handle register returns for now.
711 // TODO: For now, don't try to handle cases where getLocInfo()
712 // says Full but the types don't match.
713 if (VA.getValVT() != TLI.getValueType(RV->getType()))
716 // The calling-convention tables for x87 returns don't tell
718 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
722 unsigned SrcReg = Reg + VA.getValNo();
723 unsigned DstReg = VA.getLocReg();
724 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
725 // Avoid a cross-class copy. This is very unlikely.
726 if (!SrcRC->contains(DstReg))
728 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
729 DstReg).addReg(SrcReg);
731 // Mark the register as live out of the function.
732 MRI.addLiveOut(VA.getLocReg());
736 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
740 /// X86SelectLoad - Select and emit code to implement load instructions.
742 bool X86FastISel::X86SelectLoad(const Instruction *I) {
744 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
748 if (!X86SelectAddress(I->getOperand(0), AM))
751 unsigned ResultReg = 0;
752 if (X86FastEmitLoad(VT, AM, ResultReg)) {
753 UpdateValueMap(I, ResultReg);
759 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) {
760 switch (VT.getSimpleVT().SimpleTy) {
762 case MVT::i8: return X86::CMP8rr;
763 case MVT::i16: return X86::CMP16rr;
764 case MVT::i32: return X86::CMP32rr;
765 case MVT::i64: return X86::CMP64rr;
766 case MVT::f32: return Subtarget->hasSSE1() ? X86::UCOMISSrr : 0;
767 case MVT::f64: return Subtarget->hasSSE2() ? X86::UCOMISDrr : 0;
771 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
772 /// of the comparison, return an opcode that works for the compare (e.g.
773 /// CMP32ri) otherwise return 0.
774 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
775 switch (VT.getSimpleVT().SimpleTy) {
776 // Otherwise, we can't fold the immediate into this comparison.
778 case MVT::i8: return X86::CMP8ri;
779 case MVT::i16: return X86::CMP16ri;
780 case MVT::i32: return X86::CMP32ri;
782 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
784 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
785 return X86::CMP64ri32;
790 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
792 unsigned Op0Reg = getRegForValue(Op0);
793 if (Op0Reg == 0) return false;
795 // Handle 'null' like i32/i64 0.
796 if (isa<ConstantPointerNull>(Op1))
797 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
799 // We have two options: compare with register or immediate. If the RHS of
800 // the compare is an immediate that we can fold into this compare, use
801 // CMPri, otherwise use CMPrr.
802 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
803 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
804 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
806 .addImm(Op1C->getSExtValue());
811 unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget);
812 if (CompareOpc == 0) return false;
814 unsigned Op1Reg = getRegForValue(Op1);
815 if (Op1Reg == 0) return false;
816 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc))
823 bool X86FastISel::X86SelectCmp(const Instruction *I) {
824 const CmpInst *CI = cast<CmpInst>(I);
827 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
830 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
832 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
833 switch (CI->getPredicate()) {
834 case CmpInst::FCMP_OEQ: {
835 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
838 unsigned EReg = createResultReg(&X86::GR8RegClass);
839 unsigned NPReg = createResultReg(&X86::GR8RegClass);
840 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
841 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
842 TII.get(X86::SETNPr), NPReg);
843 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
844 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
845 UpdateValueMap(I, ResultReg);
848 case CmpInst::FCMP_UNE: {
849 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
852 unsigned NEReg = createResultReg(&X86::GR8RegClass);
853 unsigned PReg = createResultReg(&X86::GR8RegClass);
854 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
855 TII.get(X86::SETNEr), NEReg);
856 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
857 TII.get(X86::SETPr), PReg);
858 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
859 TII.get(X86::OR8rr), ResultReg)
860 .addReg(PReg).addReg(NEReg);
861 UpdateValueMap(I, ResultReg);
864 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
865 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
866 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
867 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
868 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
869 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
870 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
871 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
872 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
873 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
874 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
875 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
877 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
878 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
879 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
880 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
881 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
882 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
883 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
884 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
885 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
886 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
891 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
895 // Emit a compare of Op0/Op1.
896 if (!X86FastEmitCompare(Op0, Op1, VT))
899 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg);
900 UpdateValueMap(I, ResultReg);
904 bool X86FastISel::X86SelectZExt(const Instruction *I) {
905 // Handle zero-extension from i1 to i8, which is common.
906 if (I->getType()->isIntegerTy(8) &&
907 I->getOperand(0)->getType()->isIntegerTy(1)) {
908 unsigned ResultReg = getRegForValue(I->getOperand(0));
909 if (ResultReg == 0) return false;
910 // Set the high bits to zero.
911 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
912 if (ResultReg == 0) return false;
913 UpdateValueMap(I, ResultReg);
921 bool X86FastISel::X86SelectBranch(const Instruction *I) {
922 // Unconditional branches are selected by tablegen-generated code.
923 // Handle a conditional branch.
924 const BranchInst *BI = cast<BranchInst>(I);
925 MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
926 MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
928 // Fold the common case of a conditional branch with a comparison
929 // in the same block (values defined on other blocks may not have
930 // initialized registers).
931 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
932 if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
933 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
935 // Try to take advantage of fallthrough opportunities.
936 CmpInst::Predicate Predicate = CI->getPredicate();
937 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
938 std::swap(TrueMBB, FalseMBB);
939 Predicate = CmpInst::getInversePredicate(Predicate);
942 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
943 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
946 case CmpInst::FCMP_OEQ:
947 std::swap(TrueMBB, FalseMBB);
948 Predicate = CmpInst::FCMP_UNE;
950 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
951 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
952 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
953 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
954 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
955 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
956 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
957 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
958 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
959 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
960 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
961 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
962 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
964 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
965 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
966 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
967 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
968 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
969 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
970 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
971 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
972 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
973 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
978 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
982 // Emit a compare of the LHS and RHS, setting the flags.
983 if (!X86FastEmitCompare(Op0, Op1, VT))
986 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc))
989 if (Predicate == CmpInst::FCMP_UNE) {
990 // X86 requires a second branch to handle UNE (and OEQ,
991 // which is mapped to UNE above).
992 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
996 FastEmitBranch(FalseMBB, DL);
997 FuncInfo.MBB->addSuccessor(TrueMBB);
1000 } else if (ExtractValueInst *EI =
1001 dyn_cast<ExtractValueInst>(BI->getCondition())) {
1002 // Check to see if the branch instruction is from an "arithmetic with
1003 // overflow" intrinsic. The main way these intrinsics are used is:
1005 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
1006 // %sum = extractvalue { i32, i1 } %t, 0
1007 // %obit = extractvalue { i32, i1 } %t, 1
1008 // br i1 %obit, label %overflow, label %normal
1010 // The %sum and %obit are converted in an ADD and a SETO/SETB before
1011 // reaching the branch. Therefore, we search backwards through the MBB
1012 // looking for the SETO/SETB instruction. If an instruction modifies the
1013 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
1014 // convert the branch into a JO/JB instruction.
1015 if (const IntrinsicInst *CI =
1016 dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
1017 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
1018 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
1019 const MachineInstr *SetMI = 0;
1020 unsigned Reg = getRegForValue(EI);
1022 for (MachineBasicBlock::const_reverse_iterator
1023 RI = FuncInfo.MBB->rbegin(), RE = FuncInfo.MBB->rend();
1025 const MachineInstr &MI = *RI;
1027 if (MI.definesRegister(Reg)) {
1029 Reg = MI.getOperand(1).getReg();
1037 const TargetInstrDesc &TID = MI.getDesc();
1038 if (TID.hasUnmodeledSideEffects() ||
1039 TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
1044 unsigned OpCode = SetMI->getOpcode();
1046 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
1047 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1048 TII.get(OpCode == X86::SETOr ? X86::JO_4 : X86::JB_4))
1050 FastEmitBranch(FalseMBB, DL);
1051 FuncInfo.MBB->addSuccessor(TrueMBB);
1059 // Otherwise do a clumsy setcc and re-test it.
1060 unsigned OpReg = getRegForValue(BI->getCondition());
1061 if (OpReg == 0) return false;
1063 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1064 .addReg(OpReg).addReg(OpReg);
1065 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1067 FastEmitBranch(FalseMBB, DL);
1068 FuncInfo.MBB->addSuccessor(TrueMBB);
1072 bool X86FastISel::X86SelectShift(const Instruction *I) {
1073 unsigned CReg = 0, OpReg = 0, OpImm = 0;
1074 const TargetRegisterClass *RC = NULL;
1075 if (I->getType()->isIntegerTy(8)) {
1077 RC = &X86::GR8RegClass;
1078 switch (I->getOpcode()) {
1079 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
1080 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
1081 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
1082 default: return false;
1084 } else if (I->getType()->isIntegerTy(16)) {
1086 RC = &X86::GR16RegClass;
1087 switch (I->getOpcode()) {
1088 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
1089 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
1090 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
1091 default: return false;
1093 } else if (I->getType()->isIntegerTy(32)) {
1095 RC = &X86::GR32RegClass;
1096 switch (I->getOpcode()) {
1097 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
1098 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
1099 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
1100 default: return false;
1102 } else if (I->getType()->isIntegerTy(64)) {
1104 RC = &X86::GR64RegClass;
1105 switch (I->getOpcode()) {
1106 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
1107 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
1108 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
1109 default: return false;
1115 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1116 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1119 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1120 if (Op0Reg == 0) return false;
1122 // Fold immediate in shl(x,3).
1123 if (const ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
1124 unsigned ResultReg = createResultReg(RC);
1125 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpImm),
1126 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
1127 UpdateValueMap(I, ResultReg);
1131 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1132 if (Op1Reg == 0) return false;
1133 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1134 CReg).addReg(Op1Reg);
1136 // The shift instruction uses X86::CL. If we defined a super-register
1137 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1138 if (CReg != X86::CL)
1139 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1140 TII.get(TargetOpcode::KILL), X86::CL)
1141 .addReg(CReg, RegState::Kill);
1143 unsigned ResultReg = createResultReg(RC);
1144 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg)
1146 UpdateValueMap(I, ResultReg);
1150 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1151 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1152 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1155 // We only use cmov here, if we don't have a cmov instruction bail.
1156 if (!Subtarget->hasCMov()) return false;
1159 const TargetRegisterClass *RC = NULL;
1160 if (VT.getSimpleVT() == MVT::i16) {
1161 Opc = X86::CMOVE16rr;
1162 RC = &X86::GR16RegClass;
1163 } else if (VT.getSimpleVT() == MVT::i32) {
1164 Opc = X86::CMOVE32rr;
1165 RC = &X86::GR32RegClass;
1166 } else if (VT.getSimpleVT() == MVT::i64) {
1167 Opc = X86::CMOVE64rr;
1168 RC = &X86::GR64RegClass;
1173 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1174 if (Op0Reg == 0) return false;
1175 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1176 if (Op1Reg == 0) return false;
1177 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1178 if (Op2Reg == 0) return false;
1180 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1181 .addReg(Op0Reg).addReg(Op0Reg);
1182 unsigned ResultReg = createResultReg(RC);
1183 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1184 .addReg(Op1Reg).addReg(Op2Reg);
1185 UpdateValueMap(I, ResultReg);
1189 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
1190 // fpext from float to double.
1191 if (Subtarget->hasSSE2() &&
1192 I->getType()->isDoubleTy()) {
1193 const Value *V = I->getOperand(0);
1194 if (V->getType()->isFloatTy()) {
1195 unsigned OpReg = getRegForValue(V);
1196 if (OpReg == 0) return false;
1197 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1198 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1199 TII.get(X86::CVTSS2SDrr), ResultReg)
1201 UpdateValueMap(I, ResultReg);
1209 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
1210 if (Subtarget->hasSSE2()) {
1211 if (I->getType()->isFloatTy()) {
1212 const Value *V = I->getOperand(0);
1213 if (V->getType()->isDoubleTy()) {
1214 unsigned OpReg = getRegForValue(V);
1215 if (OpReg == 0) return false;
1216 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1217 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1218 TII.get(X86::CVTSD2SSrr), ResultReg)
1220 UpdateValueMap(I, ResultReg);
1229 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
1230 if (Subtarget->is64Bit())
1231 // All other cases should be handled by the tblgen generated code.
1233 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1234 EVT DstVT = TLI.getValueType(I->getType());
1236 // This code only handles truncation to byte right now.
1237 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1238 // All other cases should be handled by the tblgen generated code.
1240 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
1241 // All other cases should be handled by the tblgen generated code.
1244 unsigned InputReg = getRegForValue(I->getOperand(0));
1246 // Unhandled operand. Halt "fast" selection and bail.
1249 // First issue a copy to GR16_ABCD or GR32_ABCD.
1250 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1251 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1252 unsigned CopyReg = createResultReg(CopyRC);
1253 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1254 CopyReg).addReg(InputReg);
1256 // Then issue an extract_subreg.
1257 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1258 CopyReg, /*Kill=*/true,
1263 UpdateValueMap(I, ResultReg);
1267 bool X86FastISel::X86SelectExtractValue(const Instruction *I) {
1268 const ExtractValueInst *EI = cast<ExtractValueInst>(I);
1269 const Value *Agg = EI->getAggregateOperand();
1271 if (const IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1272 switch (CI->getIntrinsicID()) {
1274 case Intrinsic::sadd_with_overflow:
1275 case Intrinsic::uadd_with_overflow: {
1276 // Cheat a little. We know that the registers for "add" and "seto" are
1277 // allocated sequentially. However, we only keep track of the register
1278 // for "add" in the value map. Use extractvalue's index to get the
1279 // correct register for "seto".
1280 unsigned OpReg = getRegForValue(Agg);
1283 UpdateValueMap(I, OpReg + *EI->idx_begin());
1292 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
1293 // FIXME: Handle more intrinsics.
1294 switch (I.getIntrinsicID()) {
1295 default: return false;
1296 case Intrinsic::stackprotector: {
1297 // Emit code inline code to store the stack guard onto the stack.
1298 EVT PtrTy = TLI.getPointerTy();
1300 const Value *Op1 = I.getArgOperand(0); // The guard's value.
1301 const AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
1303 // Grab the frame index.
1305 if (!X86SelectAddress(Slot, AM)) return false;
1307 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
1311 case Intrinsic::objectsize: {
1312 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
1313 const Type *Ty = I.getCalledFunction()->getReturnType();
1315 assert(CI && "Non-constant type in Intrinsic::objectsize?");
1318 if (!isTypeLegal(Ty, VT))
1324 else if (VT == MVT::i64)
1329 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1330 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg).
1331 addImm(CI->isZero() ? -1ULL : 0);
1332 UpdateValueMap(&I, ResultReg);
1335 case Intrinsic::dbg_declare: {
1336 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I);
1338 assert(DI->getAddress() && "Null address should be checked earlier!");
1339 if (!X86SelectAddress(DI->getAddress(), AM))
1341 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1342 // FIXME may need to add RegState::Debug to any registers produced,
1343 // although ESP/EBP should be the only ones at the moment.
1344 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM).
1345 addImm(0).addMetadata(DI->getVariable());
1348 case Intrinsic::trap: {
1349 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1352 case Intrinsic::sadd_with_overflow:
1353 case Intrinsic::uadd_with_overflow: {
1354 // Replace "add with overflow" intrinsics with an "add" instruction followed
1355 // by a seto/setc instruction. Later on, when the "extractvalue"
1356 // instructions are encountered, we use the fact that two registers were
1357 // created sequentially to get the correct registers for the "sum" and the
1359 const Function *Callee = I.getCalledFunction();
1361 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1364 if (!isTypeLegal(RetTy, VT))
1367 const Value *Op1 = I.getArgOperand(0);
1368 const Value *Op2 = I.getArgOperand(1);
1369 unsigned Reg1 = getRegForValue(Op1);
1370 unsigned Reg2 = getRegForValue(Op2);
1372 if (Reg1 == 0 || Reg2 == 0)
1373 // FIXME: Handle values *not* in registers.
1379 else if (VT == MVT::i64)
1384 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1385 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg)
1386 .addReg(Reg1).addReg(Reg2);
1387 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1389 // If the add with overflow is an intra-block value then we just want to
1390 // create temporaries for it like normal. If it is a cross-block value then
1391 // UpdateValueMap will return the cross-block register used. Since we
1392 // *really* want the value to be live in the register pair known by
1393 // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1394 // the cross block case. In the non-cross-block case, we should just make
1395 // another register for the value.
1396 if (DestReg1 != ResultReg)
1397 ResultReg = DestReg1+1;
1399 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1401 unsigned Opc = X86::SETBr;
1402 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1404 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg);
1410 bool X86FastISel::X86SelectCall(const Instruction *I) {
1411 const CallInst *CI = cast<CallInst>(I);
1412 const Value *Callee = CI->getCalledValue();
1414 // Can't handle inline asm yet.
1415 if (isa<InlineAsm>(Callee))
1418 // Handle intrinsic calls.
1419 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1420 return X86VisitIntrinsicCall(*II);
1422 // Handle only C and fastcc calling conventions for now.
1423 ImmutableCallSite CS(CI);
1424 CallingConv::ID CC = CS.getCallingConv();
1425 if (CC != CallingConv::C &&
1426 CC != CallingConv::Fast &&
1427 CC != CallingConv::X86_FastCall)
1430 // fastcc with -tailcallopt is intended to provide a guaranteed
1431 // tail call optimization. Fastisel doesn't know how to do that.
1432 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
1435 // Let SDISel handle vararg functions.
1436 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1437 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1438 if (FTy->isVarArg())
1441 // Fast-isel doesn't know about callee-pop yet.
1442 if (Subtarget->IsCalleePop(FTy->isVarArg(), CC))
1445 // Handle *simple* calls for now.
1446 const Type *RetTy = CS.getType();
1448 if (RetTy->isVoidTy())
1449 RetVT = MVT::isVoid;
1450 else if (!isTypeLegal(RetTy, RetVT, true))
1453 // Materialize callee address in a register. FIXME: GV address can be
1454 // handled with a CALLpcrel32 instead.
1455 X86AddressMode CalleeAM;
1456 if (!X86SelectCallAddress(Callee, CalleeAM))
1458 unsigned CalleeOp = 0;
1459 const GlobalValue *GV = 0;
1460 if (CalleeAM.GV != 0) {
1462 } else if (CalleeAM.Base.Reg != 0) {
1463 CalleeOp = CalleeAM.Base.Reg;
1467 // Allow calls which produce i1 results.
1468 bool AndToI1 = false;
1469 if (RetVT == MVT::i1) {
1474 // Deal with call operands first.
1475 SmallVector<const Value *, 8> ArgVals;
1476 SmallVector<unsigned, 8> Args;
1477 SmallVector<EVT, 8> ArgVTs;
1478 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1479 Args.reserve(CS.arg_size());
1480 ArgVals.reserve(CS.arg_size());
1481 ArgVTs.reserve(CS.arg_size());
1482 ArgFlags.reserve(CS.arg_size());
1483 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1485 unsigned Arg = getRegForValue(*i);
1488 ISD::ArgFlagsTy Flags;
1489 unsigned AttrInd = i - CS.arg_begin() + 1;
1490 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1492 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1495 // FIXME: Only handle *easy* calls for now.
1496 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1497 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1498 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1499 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1502 const Type *ArgTy = (*i)->getType();
1504 if (!isTypeLegal(ArgTy, ArgVT))
1506 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1507 Flags.setOrigAlign(OriginalAlignment);
1509 Args.push_back(Arg);
1510 ArgVals.push_back(*i);
1511 ArgVTs.push_back(ArgVT);
1512 ArgFlags.push_back(Flags);
1515 // Analyze operands of the call, assigning locations to each operand.
1516 SmallVector<CCValAssign, 16> ArgLocs;
1517 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext());
1519 // Allocate shadow area for Win64
1520 if (Subtarget->isTargetWin64()) {
1521 CCInfo.AllocateStack(32, 8);
1524 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_X86);
1526 // Get a count of how many bytes are to be pushed on the stack.
1527 unsigned NumBytes = CCInfo.getNextStackOffset();
1529 // Issue CALLSEQ_START
1530 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1531 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
1534 // Process argument: walk the register/memloc assignments, inserting
1536 SmallVector<unsigned, 4> RegArgs;
1537 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1538 CCValAssign &VA = ArgLocs[i];
1539 unsigned Arg = Args[VA.getValNo()];
1540 EVT ArgVT = ArgVTs[VA.getValNo()];
1542 // Promote the value if needed.
1543 switch (VA.getLocInfo()) {
1544 default: llvm_unreachable("Unknown loc info!");
1545 case CCValAssign::Full: break;
1546 case CCValAssign::SExt: {
1547 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1549 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1551 ArgVT = VA.getLocVT();
1554 case CCValAssign::ZExt: {
1555 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1557 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1559 ArgVT = VA.getLocVT();
1562 case CCValAssign::AExt: {
1563 // We don't handle MMX parameters yet.
1564 if (VA.getLocVT().isVector() && VA.getLocVT().getSizeInBits() == 128)
1566 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1569 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1572 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1575 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1576 ArgVT = VA.getLocVT();
1579 case CCValAssign::BCvt: {
1580 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(),
1581 ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false);
1582 assert(BC != 0 && "Failed to emit a bitcast!");
1584 ArgVT = VA.getLocVT();
1589 if (VA.isRegLoc()) {
1590 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1591 VA.getLocReg()).addReg(Arg);
1592 RegArgs.push_back(VA.getLocReg());
1594 unsigned LocMemOffset = VA.getLocMemOffset();
1596 AM.Base.Reg = StackPtr;
1597 AM.Disp = LocMemOffset;
1598 const Value *ArgVal = ArgVals[VA.getValNo()];
1600 // If this is a really simple value, emit this with the Value* version of
1601 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1602 // can cause us to reevaluate the argument.
1603 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1604 X86FastEmitStore(ArgVT, ArgVal, AM);
1606 X86FastEmitStore(ArgVT, Arg, AM);
1610 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1612 if (Subtarget->isPICStyleGOT()) {
1613 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1614 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1615 X86::EBX).addReg(Base);
1619 MachineInstrBuilder MIB;
1621 // Register-indirect call.
1623 if (Subtarget->isTargetWin64())
1624 CallOpc = X86::WINCALL64r;
1625 else if (Subtarget->is64Bit())
1626 CallOpc = X86::CALL64r;
1628 CallOpc = X86::CALL32r;
1629 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1634 assert(GV && "Not a direct call");
1636 if (Subtarget->isTargetWin64())
1637 CallOpc = X86::WINCALL64pcrel32;
1638 else if (Subtarget->is64Bit())
1639 CallOpc = X86::CALL64pcrel32;
1641 CallOpc = X86::CALLpcrel32;
1643 // See if we need any target-specific flags on the GV operand.
1644 unsigned char OpFlags = 0;
1646 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1647 // external symbols most go through the PLT in PIC mode. If the symbol
1648 // has hidden or protected visibility, or if it is static or local, then
1649 // we don't need to use the PLT - we can directly call it.
1650 if (Subtarget->isTargetELF() &&
1651 TM.getRelocationModel() == Reloc::PIC_ &&
1652 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1653 OpFlags = X86II::MO_PLT;
1654 } else if (Subtarget->isPICStyleStubAny() &&
1655 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1656 Subtarget->getDarwinVers() < 9) {
1657 // PC-relative references to external symbols should go through $stub,
1658 // unless we're building with the leopard linker or later, which
1659 // automatically synthesizes these stubs.
1660 OpFlags = X86II::MO_DARWIN_STUB;
1664 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1665 .addGlobalAddress(GV, 0, OpFlags);
1668 // Add an implicit use GOT pointer in EBX.
1669 if (Subtarget->isPICStyleGOT())
1670 MIB.addReg(X86::EBX);
1672 // Add implicit physical register uses to the call.
1673 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1674 MIB.addReg(RegArgs[i]);
1676 // Issue CALLSEQ_END
1677 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1678 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
1679 .addImm(NumBytes).addImm(0);
1681 // Now handle call return value (if any).
1682 SmallVector<unsigned, 4> UsedRegs;
1683 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1684 SmallVector<CCValAssign, 16> RVLocs;
1685 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
1686 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1688 // Copy all of the result registers out of their specified physreg.
1689 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1690 EVT CopyVT = RVLocs[0].getValVT();
1691 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1693 // If this is a call to a function that returns an fp value on the x87 fp
1694 // stack, but where we prefer to use the value in xmm registers, copy it
1695 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1696 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1697 RVLocs[0].getLocReg() == X86::ST1) &&
1698 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1700 DstRC = X86::RFP80RegisterClass;
1703 unsigned ResultReg = createResultReg(DstRC);
1704 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1705 ResultReg).addReg(RVLocs[0].getLocReg());
1706 UsedRegs.push_back(RVLocs[0].getLocReg());
1708 if (CopyVT != RVLocs[0].getValVT()) {
1709 // Round the F80 the right size, which also moves to the appropriate xmm
1710 // register. This is accomplished by storing the F80 value in memory and
1711 // then loading it back. Ewww...
1712 EVT ResVT = RVLocs[0].getValVT();
1713 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1714 unsigned MemSize = ResVT.getSizeInBits()/8;
1715 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
1716 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1719 DstRC = ResVT == MVT::f32
1720 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1721 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1722 ResultReg = createResultReg(DstRC);
1723 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1724 TII.get(Opc), ResultReg), FI);
1728 // Mask out all but lowest bit for some call which produces an i1.
1729 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1730 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1731 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1732 ResultReg = AndResult;
1735 UpdateValueMap(I, ResultReg);
1738 // Set all unused physreg defs as dead.
1739 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1746 X86FastISel::TargetSelectInstruction(const Instruction *I) {
1747 switch (I->getOpcode()) {
1749 case Instruction::Load:
1750 return X86SelectLoad(I);
1751 case Instruction::Store:
1752 return X86SelectStore(I);
1753 case Instruction::Ret:
1754 return X86SelectRet(I);
1755 case Instruction::ICmp:
1756 case Instruction::FCmp:
1757 return X86SelectCmp(I);
1758 case Instruction::ZExt:
1759 return X86SelectZExt(I);
1760 case Instruction::Br:
1761 return X86SelectBranch(I);
1762 case Instruction::Call:
1763 return X86SelectCall(I);
1764 case Instruction::LShr:
1765 case Instruction::AShr:
1766 case Instruction::Shl:
1767 return X86SelectShift(I);
1768 case Instruction::Select:
1769 return X86SelectSelect(I);
1770 case Instruction::Trunc:
1771 return X86SelectTrunc(I);
1772 case Instruction::FPExt:
1773 return X86SelectFPExt(I);
1774 case Instruction::FPTrunc:
1775 return X86SelectFPTrunc(I);
1776 case Instruction::ExtractValue:
1777 return X86SelectExtractValue(I);
1778 case Instruction::IntToPtr: // Deliberate fall-through.
1779 case Instruction::PtrToInt: {
1780 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1781 EVT DstVT = TLI.getValueType(I->getType());
1782 if (DstVT.bitsGT(SrcVT))
1783 return X86SelectZExt(I);
1784 if (DstVT.bitsLT(SrcVT))
1785 return X86SelectTrunc(I);
1786 unsigned Reg = getRegForValue(I->getOperand(0));
1787 if (Reg == 0) return false;
1788 UpdateValueMap(I, Reg);
1796 unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
1798 if (!isTypeLegal(C->getType(), VT))
1801 // Get opcode and regclass of the output for the given load instruction.
1803 const TargetRegisterClass *RC = NULL;
1804 switch (VT.getSimpleVT().SimpleTy) {
1805 default: return false;
1808 RC = X86::GR8RegisterClass;
1812 RC = X86::GR16RegisterClass;
1816 RC = X86::GR32RegisterClass;
1819 // Must be in x86-64 mode.
1821 RC = X86::GR64RegisterClass;
1824 if (Subtarget->hasSSE1()) {
1826 RC = X86::FR32RegisterClass;
1828 Opc = X86::LD_Fp32m;
1829 RC = X86::RFP32RegisterClass;
1833 if (Subtarget->hasSSE2()) {
1835 RC = X86::FR64RegisterClass;
1837 Opc = X86::LD_Fp64m;
1838 RC = X86::RFP64RegisterClass;
1842 // No f80 support yet.
1846 // Materialize addresses with LEA instructions.
1847 if (isa<GlobalValue>(C)) {
1849 if (X86SelectAddress(C, AM)) {
1850 if (TLI.getPointerTy() == MVT::i32)
1854 unsigned ResultReg = createResultReg(RC);
1855 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1856 TII.get(Opc), ResultReg), AM);
1862 // MachineConstantPool wants an explicit alignment.
1863 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1865 // Alignment of vector types. FIXME!
1866 Align = TD.getTypeAllocSize(C->getType());
1869 // x86-32 PIC requires a PIC base register for constant pools.
1870 unsigned PICBase = 0;
1871 unsigned char OpFlag = 0;
1872 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
1873 OpFlag = X86II::MO_PIC_BASE_OFFSET;
1874 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1875 } else if (Subtarget->isPICStyleGOT()) {
1876 OpFlag = X86II::MO_GOTOFF;
1877 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1878 } else if (Subtarget->isPICStyleRIPRel() &&
1879 TM.getCodeModel() == CodeModel::Small) {
1883 // Create the load from the constant pool.
1884 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1885 unsigned ResultReg = createResultReg(RC);
1886 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1887 TII.get(Opc), ResultReg),
1888 MCPOffset, PICBase, OpFlag);
1893 unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
1894 // Fail on dynamic allocas. At this point, getRegForValue has already
1895 // checked its CSE maps, so if we're here trying to handle a dynamic
1896 // alloca, we're not going to succeed. X86SelectAddress has a
1897 // check for dynamic allocas, because it's called directly from
1898 // various places, but TargetMaterializeAlloca also needs a check
1899 // in order to avoid recursion between getRegForValue,
1900 // X86SelectAddrss, and TargetMaterializeAlloca.
1901 if (!FuncInfo.StaticAllocaMap.count(C))
1905 if (!X86SelectAddress(C, AM))
1907 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1908 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1909 unsigned ResultReg = createResultReg(RC);
1910 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1911 TII.get(Opc), ResultReg), AM);
1915 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
1916 /// vreg is being provided by the specified load instruction. If possible,
1917 /// try to fold the load as an operand to the instruction, returning true if
1919 bool X86FastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
1920 const LoadInst *LI) {
1922 if (!X86SelectAddress(LI->getOperand(0), AM))
1925 X86InstrInfo &XII = (X86InstrInfo&)TII;
1927 unsigned Size = TD.getTypeAllocSize(LI->getType());
1928 unsigned Alignment = LI->getAlignment();
1930 SmallVector<MachineOperand, 8> AddrOps;
1931 AM.getFullAddress(AddrOps);
1933 MachineInstr *Result =
1934 XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment);
1935 if (Result == 0) return false;
1937 MI->getParent()->insert(MI, Result);
1938 MI->eraseFromParent();
1944 llvm::FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo) {
1945 return new X86FastISel(funcInfo);