1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/Support/CallSite.h"
30 #include "llvm/Support/GetElementPtrTypeIterator.h"
34 class X86FastISel : public FastISel {
35 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
36 /// make the right decision when generating code for different targets.
37 const X86Subtarget *Subtarget;
39 /// StackPtr - Register used as the stack pointer.
43 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
44 /// floating point ops.
45 /// When SSE is available, use it for f32 operations.
46 /// When SSE2 is available, use it for f64 operations.
51 explicit X86FastISel(MachineFunction &mf,
52 MachineModuleInfo *mmi,
53 DenseMap<const Value *, unsigned> &vm,
54 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
55 DenseMap<const AllocaInst *, int> &am
57 , SmallSet<Instruction*, 8> &cil
60 : FastISel(mf, mmi, vm, bm, am
65 Subtarget = &TM.getSubtarget<X86Subtarget>();
66 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
67 X86ScalarSSEf64 = Subtarget->hasSSE2();
68 X86ScalarSSEf32 = Subtarget->hasSSE1();
71 virtual bool TargetSelectInstruction(Instruction *I);
73 #include "X86GenFastISel.inc"
76 bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
78 bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
80 bool X86FastEmitStore(MVT VT, Value *Val,
81 const X86AddressMode &AM);
82 bool X86FastEmitStore(MVT VT, unsigned Val,
83 const X86AddressMode &AM);
85 bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
88 bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
90 bool X86SelectLoad(Instruction *I);
92 bool X86SelectStore(Instruction *I);
94 bool X86SelectCmp(Instruction *I);
96 bool X86SelectZExt(Instruction *I);
98 bool X86SelectBranch(Instruction *I);
100 bool X86SelectShift(Instruction *I);
102 bool X86SelectSelect(Instruction *I);
104 bool X86SelectTrunc(Instruction *I);
106 bool X86SelectFPExt(Instruction *I);
107 bool X86SelectFPTrunc(Instruction *I);
109 bool X86SelectCall(Instruction *I);
111 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
113 const X86InstrInfo *getInstrInfo() const {
114 return getTargetMachine()->getInstrInfo();
116 const X86TargetMachine *getTargetMachine() const {
117 return static_cast<const X86TargetMachine *>(&TM);
120 unsigned TargetMaterializeConstant(Constant *C);
122 unsigned TargetMaterializeAlloca(AllocaInst *C);
124 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
125 /// computed in an SSE register, not on the X87 floating point stack.
126 bool isScalarFPTypeInSSEReg(MVT VT) const {
127 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
128 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
131 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
134 bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
135 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
136 if (VT == MVT::Other || !VT.isSimple())
137 // Unhandled type. Halt "fast" selection and bail.
140 // For now, require SSE/SSE2 for performing floating-point operations,
141 // since x87 requires additional work.
142 if (VT == MVT::f64 && !X86ScalarSSEf64)
144 if (VT == MVT::f32 && !X86ScalarSSEf32)
146 // Similarly, no f80 support yet.
149 // We only handle legal types. For example, on x86-32 the instruction
150 // selector contains all of the 64-bit instructions from x86-64,
151 // under the assumption that i64 won't be used if the target doesn't
153 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
156 #include "X86GenCallingConv.inc"
158 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
160 CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
161 if (Subtarget->is64Bit()) {
162 if (Subtarget->isTargetWin64())
163 return CC_X86_Win64_C;
164 else if (CC == CallingConv::Fast && isTaillCall)
165 return CC_X86_64_TailCall;
170 if (CC == CallingConv::X86_FastCall)
171 return CC_X86_32_FastCall;
172 else if (CC == CallingConv::Fast)
173 return CC_X86_32_FastCC;
178 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
179 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
180 /// Return true and the result register by reference if it is possible.
181 bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
182 unsigned &ResultReg) {
183 // Get opcode and regclass of the output for the given load instruction.
185 const TargetRegisterClass *RC = NULL;
186 switch (VT.getSimpleVT()) {
187 default: return false;
190 RC = X86::GR8RegisterClass;
194 RC = X86::GR16RegisterClass;
198 RC = X86::GR32RegisterClass;
201 // Must be in x86-64 mode.
203 RC = X86::GR64RegisterClass;
206 if (Subtarget->hasSSE1()) {
208 RC = X86::FR32RegisterClass;
211 RC = X86::RFP32RegisterClass;
215 if (Subtarget->hasSSE2()) {
217 RC = X86::FR64RegisterClass;
220 RC = X86::RFP64RegisterClass;
224 // No f80 support yet.
228 ResultReg = createResultReg(RC);
229 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
233 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
234 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
235 /// and a displacement offset, or a GlobalAddress,
236 /// i.e. V. Return true if it is possible.
238 X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
239 const X86AddressMode &AM) {
240 // Get opcode and regclass of the output for the given store instruction.
242 switch (VT.getSimpleVT()) {
243 case MVT::f80: // No f80 support yet.
244 default: return false;
245 case MVT::i8: Opc = X86::MOV8mr; break;
246 case MVT::i16: Opc = X86::MOV16mr; break;
247 case MVT::i32: Opc = X86::MOV32mr; break;
248 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
250 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
253 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
257 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Val);
261 bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val,
262 const X86AddressMode &AM) {
263 // Handle 'null' like i32/i64 0.
264 if (isa<ConstantPointerNull>(Val))
265 Val = Constant::getNullValue(TD.getIntPtrType());
267 // If this is a store of a simple constant, fold the constant into the store.
268 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
270 switch (VT.getSimpleVT()) {
272 case MVT::i8: Opc = X86::MOV8mi; break;
273 case MVT::i16: Opc = X86::MOV16mi; break;
274 case MVT::i32: Opc = X86::MOV32mi; break;
276 // Must be a 32-bit sign extended value.
277 if ((int)CI->getSExtValue() == CI->getSExtValue())
278 Opc = X86::MOV64mi32;
283 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addImm(CI->getSExtValue());
288 unsigned ValReg = getRegForValue(Val);
292 return X86FastEmitStore(VT, ValReg, AM);
297 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
298 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
299 /// ISD::SIGN_EXTEND).
300 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
301 unsigned Src, MVT SrcVT,
302 unsigned &ResultReg) {
303 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
312 /// X86SelectAddress - Attempt to fill in an address from the given value.
314 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
316 unsigned Opcode = Instruction::UserOp1;
317 if (Instruction *I = dyn_cast<Instruction>(V)) {
318 Opcode = I->getOpcode();
320 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
321 Opcode = C->getOpcode();
327 case Instruction::BitCast:
328 // Look past bitcasts.
329 return X86SelectAddress(U->getOperand(0), AM, isCall);
331 case Instruction::IntToPtr:
332 // Look past no-op inttoptrs.
333 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
334 return X86SelectAddress(U->getOperand(0), AM, isCall);
336 case Instruction::PtrToInt:
337 // Look past no-op ptrtoints.
338 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
339 return X86SelectAddress(U->getOperand(0), AM, isCall);
341 case Instruction::Alloca: {
343 // Do static allocas.
344 const AllocaInst *A = cast<AllocaInst>(V);
345 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
346 if (SI != StaticAllocaMap.end()) {
347 AM.BaseType = X86AddressMode::FrameIndexBase;
348 AM.Base.FrameIndex = SI->second;
354 case Instruction::Add: {
356 // Adds of constants are common and easy enough.
357 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
358 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
359 // They have to fit in the 32-bit signed displacement field though.
361 AM.Disp = (uint32_t)Disp;
362 return X86SelectAddress(U->getOperand(0), AM, isCall);
368 case Instruction::GetElementPtr: {
370 // Pattern-match simple GEPs.
371 uint64_t Disp = (int32_t)AM.Disp;
372 unsigned IndexReg = AM.IndexReg;
373 unsigned Scale = AM.Scale;
374 gep_type_iterator GTI = gep_type_begin(U);
375 // Look at all but the last index. Constants can be folded,
376 // and one dynamic index can be handled, if the scale is supported.
377 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
378 i != e; ++i, ++GTI) {
380 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
381 const StructLayout *SL = TD.getStructLayout(STy);
382 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
383 Disp += SL->getElementOffset(Idx);
385 uint64_t S = TD.getABITypeSize(GTI.getIndexedType());
386 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
387 // Constant-offset addressing.
388 Disp += CI->getSExtValue() * S;
389 } else if (IndexReg == 0 &&
391 !getTargetMachine()->symbolicAddressesAreRIPRel()) &&
392 (S == 1 || S == 2 || S == 4 || S == 8)) {
393 // Scaled-index addressing.
395 IndexReg = getRegForValue(Op);
400 goto unsupported_gep;
403 // Check for displacement overflow.
406 // Ok, the GEP indices were covered by constant-offset and scaled-index
407 // addressing. Update the address state and move on to examining the base.
408 AM.IndexReg = IndexReg;
410 AM.Disp = (uint32_t)Disp;
411 return X86SelectAddress(U->getOperand(0), AM, isCall);
413 // Ok, the GEP indices weren't all covered.
418 // Handle constant address.
419 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
420 // Can't handle alternate code models yet.
421 if (TM.getCodeModel() != CodeModel::Default &&
422 TM.getCodeModel() != CodeModel::Small)
425 // RIP-relative addresses can't have additional register operands.
426 if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
427 (AM.Base.Reg != 0 || AM.IndexReg != 0))
430 // Set up the basic address.
433 TM.getRelocationModel() == Reloc::PIC_ &&
434 !Subtarget->is64Bit())
435 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
437 // Emit an extra load if the ABI requires it.
438 if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
439 // Check to see if we've already materialized this
440 // value in a register in this block.
441 if (unsigned Reg = LocalValueMap[V]) {
446 // Issue load from stub if necessary.
448 const TargetRegisterClass *RC = NULL;
449 if (TLI.getPointerTy() == MVT::i32) {
451 RC = X86::GR32RegisterClass;
454 RC = X86::GR64RegisterClass;
457 X86AddressMode StubAM;
458 StubAM.Base.Reg = AM.Base.Reg;
460 unsigned ResultReg = createResultReg(RC);
461 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), StubAM);
463 // Now construct the final address. Note that the Disp, Scale,
464 // and Index values may already be set here.
465 AM.Base.Reg = ResultReg;
468 // Prevent loading GV stub multiple times in same MBB.
469 LocalValueMap[V] = AM.Base.Reg;
474 // If all else fails, try to materialize the value in a register.
475 if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
476 if (AM.Base.Reg == 0) {
477 AM.Base.Reg = getRegForValue(V);
478 return AM.Base.Reg != 0;
480 if (AM.IndexReg == 0) {
481 assert(AM.Scale == 1 && "Scale with no index!");
482 AM.IndexReg = getRegForValue(V);
483 return AM.IndexReg != 0;
490 /// X86SelectStore - Select and emit code to implement store instructions.
491 bool X86FastISel::X86SelectStore(Instruction* I) {
493 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
497 if (!X86SelectAddress(I->getOperand(1), AM, false))
500 return X86FastEmitStore(VT, I->getOperand(0), AM);
503 /// X86SelectLoad - Select and emit code to implement load instructions.
505 bool X86FastISel::X86SelectLoad(Instruction *I) {
507 if (!isTypeLegal(I->getType(), VT))
511 if (!X86SelectAddress(I->getOperand(0), AM, false))
514 unsigned ResultReg = 0;
515 if (X86FastEmitLoad(VT, AM, ResultReg)) {
516 UpdateValueMap(I, ResultReg);
522 static unsigned X86ChooseCmpOpcode(MVT VT) {
523 switch (VT.getSimpleVT()) {
525 case MVT::i8: return X86::CMP8rr;
526 case MVT::i16: return X86::CMP16rr;
527 case MVT::i32: return X86::CMP32rr;
528 case MVT::i64: return X86::CMP64rr;
529 case MVT::f32: return X86::UCOMISSrr;
530 case MVT::f64: return X86::UCOMISDrr;
534 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
535 /// of the comparison, return an opcode that works for the compare (e.g.
536 /// CMP32ri) otherwise return 0.
537 static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
538 switch (VT.getSimpleVT()) {
539 // Otherwise, we can't fold the immediate into this comparison.
541 case MVT::i8: return X86::CMP8ri;
542 case MVT::i16: return X86::CMP16ri;
543 case MVT::i32: return X86::CMP32ri;
545 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
547 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
548 return X86::CMP64ri32;
553 bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
554 unsigned Op0Reg = getRegForValue(Op0);
555 if (Op0Reg == 0) return false;
557 // Handle 'null' like i32/i64 0.
558 if (isa<ConstantPointerNull>(Op1))
559 Op1 = Constant::getNullValue(TD.getIntPtrType());
561 // We have two options: compare with register or immediate. If the RHS of
562 // the compare is an immediate that we can fold into this compare, use
563 // CMPri, otherwise use CMPrr.
564 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
565 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
566 BuildMI(MBB, TII.get(CompareImmOpc)).addReg(Op0Reg)
567 .addImm(Op1C->getSExtValue());
572 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
573 if (CompareOpc == 0) return false;
575 unsigned Op1Reg = getRegForValue(Op1);
576 if (Op1Reg == 0) return false;
577 BuildMI(MBB, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
582 bool X86FastISel::X86SelectCmp(Instruction *I) {
583 CmpInst *CI = cast<CmpInst>(I);
586 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
589 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
591 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
592 switch (CI->getPredicate()) {
593 case CmpInst::FCMP_OEQ: {
594 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
597 unsigned EReg = createResultReg(&X86::GR8RegClass);
598 unsigned NPReg = createResultReg(&X86::GR8RegClass);
599 BuildMI(MBB, TII.get(X86::SETEr), EReg);
600 BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
601 BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
602 UpdateValueMap(I, ResultReg);
605 case CmpInst::FCMP_UNE: {
606 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
609 unsigned NEReg = createResultReg(&X86::GR8RegClass);
610 unsigned PReg = createResultReg(&X86::GR8RegClass);
611 BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
612 BuildMI(MBB, TII.get(X86::SETPr), PReg);
613 BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
614 UpdateValueMap(I, ResultReg);
617 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
618 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
619 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
620 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
621 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
622 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
623 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
624 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
625 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
626 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
627 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
628 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
630 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
631 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
632 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
633 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
634 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
635 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
636 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
637 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
638 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
639 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
644 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
648 // Emit a compare of Op0/Op1.
649 if (!X86FastEmitCompare(Op0, Op1, VT))
652 BuildMI(MBB, TII.get(SetCCOpc), ResultReg);
653 UpdateValueMap(I, ResultReg);
657 bool X86FastISel::X86SelectZExt(Instruction *I) {
658 // Special-case hack: The only i1 values we know how to produce currently
659 // set the upper bits of an i8 value to zero.
660 if (I->getType() == Type::Int8Ty &&
661 I->getOperand(0)->getType() == Type::Int1Ty) {
662 unsigned ResultReg = getRegForValue(I->getOperand(0));
663 if (ResultReg == 0) return false;
664 UpdateValueMap(I, ResultReg);
672 bool X86FastISel::X86SelectBranch(Instruction *I) {
673 // Unconditional branches are selected by tablegen-generated code.
674 // Handle a conditional branch.
675 BranchInst *BI = cast<BranchInst>(I);
676 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
677 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
679 // Fold the common case of a conditional branch with a comparison.
680 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
681 if (CI->hasOneUse()) {
682 MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
684 // Try to take advantage of fallthrough opportunities.
685 CmpInst::Predicate Predicate = CI->getPredicate();
686 if (MBB->isLayoutSuccessor(TrueMBB)) {
687 std::swap(TrueMBB, FalseMBB);
688 Predicate = CmpInst::getInversePredicate(Predicate);
691 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
692 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
695 case CmpInst::FCMP_OEQ:
696 std::swap(TrueMBB, FalseMBB);
697 Predicate = CmpInst::FCMP_UNE;
699 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break;
700 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break;
701 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
702 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break;
703 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break;
704 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
705 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
706 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break;
707 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break;
708 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break;
709 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break;
710 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
711 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
713 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break;
714 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break;
715 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break;
716 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
717 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
718 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
719 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break;
720 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
721 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break;
722 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
727 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
731 // Emit a compare of the LHS and RHS, setting the flags.
732 if (!X86FastEmitCompare(Op0, Op1, VT))
735 BuildMI(MBB, TII.get(BranchOpc)).addMBB(TrueMBB);
737 if (Predicate == CmpInst::FCMP_UNE) {
738 // X86 requires a second branch to handle UNE (and OEQ,
739 // which is mapped to UNE above).
740 BuildMI(MBB, TII.get(X86::JP)).addMBB(TrueMBB);
743 FastEmitBranch(FalseMBB);
744 MBB->addSuccessor(TrueMBB);
749 // Otherwise do a clumsy setcc and re-test it.
750 unsigned OpReg = getRegForValue(BI->getCondition());
751 if (OpReg == 0) return false;
753 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
754 BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
755 FastEmitBranch(FalseMBB);
756 MBB->addSuccessor(TrueMBB);
760 bool X86FastISel::X86SelectShift(Instruction *I) {
761 unsigned CReg = 0, OpReg = 0, OpImm = 0;
762 const TargetRegisterClass *RC = NULL;
763 if (I->getType() == Type::Int8Ty) {
765 RC = &X86::GR8RegClass;
766 switch (I->getOpcode()) {
767 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
768 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
769 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
770 default: return false;
772 } else if (I->getType() == Type::Int16Ty) {
774 RC = &X86::GR16RegClass;
775 switch (I->getOpcode()) {
776 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
777 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
778 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
779 default: return false;
781 } else if (I->getType() == Type::Int32Ty) {
783 RC = &X86::GR32RegClass;
784 switch (I->getOpcode()) {
785 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
786 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
787 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
788 default: return false;
790 } else if (I->getType() == Type::Int64Ty) {
792 RC = &X86::GR64RegClass;
793 switch (I->getOpcode()) {
794 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
795 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
796 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
797 default: return false;
803 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
804 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
807 unsigned Op0Reg = getRegForValue(I->getOperand(0));
808 if (Op0Reg == 0) return false;
810 // Fold immediate in shl(x,3).
811 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
812 unsigned ResultReg = createResultReg(RC);
813 BuildMI(MBB, TII.get(OpImm),
814 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue());
815 UpdateValueMap(I, ResultReg);
819 unsigned Op1Reg = getRegForValue(I->getOperand(1));
820 if (Op1Reg == 0) return false;
821 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
823 // The shift instruction uses X86::CL. If we defined a super-register
824 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
827 BuildMI(MBB, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
828 .addReg(CReg).addImm(X86::SUBREG_8BIT);
830 unsigned ResultReg = createResultReg(RC);
831 BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg);
832 UpdateValueMap(I, ResultReg);
836 bool X86FastISel::X86SelectSelect(Instruction *I) {
837 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
838 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
842 const TargetRegisterClass *RC = NULL;
843 if (VT.getSimpleVT() == MVT::i16) {
844 Opc = X86::CMOVE16rr;
845 RC = &X86::GR16RegClass;
846 } else if (VT.getSimpleVT() == MVT::i32) {
847 Opc = X86::CMOVE32rr;
848 RC = &X86::GR32RegClass;
849 } else if (VT.getSimpleVT() == MVT::i64) {
850 Opc = X86::CMOVE64rr;
851 RC = &X86::GR64RegClass;
856 unsigned Op0Reg = getRegForValue(I->getOperand(0));
857 if (Op0Reg == 0) return false;
858 unsigned Op1Reg = getRegForValue(I->getOperand(1));
859 if (Op1Reg == 0) return false;
860 unsigned Op2Reg = getRegForValue(I->getOperand(2));
861 if (Op2Reg == 0) return false;
863 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
864 unsigned ResultReg = createResultReg(RC);
865 BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
866 UpdateValueMap(I, ResultReg);
870 bool X86FastISel::X86SelectFPExt(Instruction *I) {
871 // fpext from float to double.
872 if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
873 Value *V = I->getOperand(0);
874 if (V->getType() == Type::FloatTy) {
875 unsigned OpReg = getRegForValue(V);
876 if (OpReg == 0) return false;
877 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
878 BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
879 UpdateValueMap(I, ResultReg);
887 bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
888 if (Subtarget->hasSSE2()) {
889 if (I->getType() == Type::FloatTy) {
890 Value *V = I->getOperand(0);
891 if (V->getType() == Type::DoubleTy) {
892 unsigned OpReg = getRegForValue(V);
893 if (OpReg == 0) return false;
894 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
895 BuildMI(MBB, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
896 UpdateValueMap(I, ResultReg);
905 bool X86FastISel::X86SelectTrunc(Instruction *I) {
906 if (Subtarget->is64Bit())
907 // All other cases should be handled by the tblgen generated code.
909 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
910 MVT DstVT = TLI.getValueType(I->getType());
911 if (DstVT != MVT::i8)
912 // All other cases should be handled by the tblgen generated code.
914 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
915 // All other cases should be handled by the tblgen generated code.
918 unsigned InputReg = getRegForValue(I->getOperand(0));
920 // Unhandled operand. Halt "fast" selection and bail.
923 // First issue a copy to GR16_ or GR32_.
924 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16to16_ : X86::MOV32to32_;
925 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
926 ? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
927 unsigned CopyReg = createResultReg(CopyRC);
928 BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
930 // Then issue an extract_subreg.
931 unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg, X86::SUBREG_8BIT);
935 UpdateValueMap(I, ResultReg);
939 bool X86FastISel::X86SelectCall(Instruction *I) {
940 CallInst *CI = cast<CallInst>(I);
941 Value *Callee = I->getOperand(0);
943 // Can't handle inline asm yet.
944 if (isa<InlineAsm>(Callee))
947 // FIXME: Handle some intrinsics.
948 if (Function *F = CI->getCalledFunction()) {
949 if (F->isDeclaration() &&F->getIntrinsicID())
953 // Handle only C and fastcc calling conventions for now.
955 unsigned CC = CS.getCallingConv();
956 if (CC != CallingConv::C &&
957 CC != CallingConv::Fast &&
958 CC != CallingConv::X86_FastCall)
961 // Let SDISel handle vararg functions.
962 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
963 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
967 // Handle *simple* calls for now.
968 const Type *RetTy = CS.getType();
970 if (RetTy == Type::VoidTy)
972 else if (!isTypeLegal(RetTy, RetVT, true))
975 // Materialize callee address in a register. FIXME: GV address can be
976 // handled with a CALLpcrel32 instead.
977 X86AddressMode CalleeAM;
978 if (!X86SelectAddress(Callee, CalleeAM, true))
980 unsigned CalleeOp = 0;
982 if (CalleeAM.Base.Reg != 0) {
983 assert(CalleeAM.GV == 0);
984 CalleeOp = CalleeAM.Base.Reg;
985 } else if (CalleeAM.GV != 0) {
986 assert(CalleeAM.GV != 0);
991 // Allow calls which produce i1 results.
992 bool AndToI1 = false;
993 if (RetVT == MVT::i1) {
998 // Deal with call operands first.
999 SmallVector<Value*, 8> ArgVals;
1000 SmallVector<unsigned, 8> Args;
1001 SmallVector<MVT, 8> ArgVTs;
1002 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1003 Args.reserve(CS.arg_size());
1004 ArgVals.reserve(CS.arg_size());
1005 ArgVTs.reserve(CS.arg_size());
1006 ArgFlags.reserve(CS.arg_size());
1007 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1009 unsigned Arg = getRegForValue(*i);
1012 ISD::ArgFlagsTy Flags;
1013 unsigned AttrInd = i - CS.arg_begin() + 1;
1014 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1016 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1019 // FIXME: Only handle *easy* calls for now.
1020 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1021 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1022 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1023 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1026 const Type *ArgTy = (*i)->getType();
1028 if (!isTypeLegal(ArgTy, ArgVT))
1030 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1031 Flags.setOrigAlign(OriginalAlignment);
1033 Args.push_back(Arg);
1034 ArgVals.push_back(*i);
1035 ArgVTs.push_back(ArgVT);
1036 ArgFlags.push_back(Flags);
1039 // Analyze operands of the call, assigning locations to each operand.
1040 SmallVector<CCValAssign, 16> ArgLocs;
1041 CCState CCInfo(CC, false, TM, ArgLocs);
1042 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1044 // Get a count of how many bytes are to be pushed on the stack.
1045 unsigned NumBytes = CCInfo.getNextStackOffset();
1047 // Issue CALLSEQ_START
1048 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1049 BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes);
1051 // Process argument: walk the register/memloc assignments, inserting
1053 SmallVector<unsigned, 4> RegArgs;
1054 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1055 CCValAssign &VA = ArgLocs[i];
1056 unsigned Arg = Args[VA.getValNo()];
1057 MVT ArgVT = ArgVTs[VA.getValNo()];
1059 // Promote the value if needed.
1060 switch (VA.getLocInfo()) {
1061 default: assert(0 && "Unknown loc info!");
1062 case CCValAssign::Full: break;
1063 case CCValAssign::SExt: {
1064 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1066 assert(Emitted && "Failed to emit a sext!");
1067 ArgVT = VA.getLocVT();
1070 case CCValAssign::ZExt: {
1071 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1073 assert(Emitted && "Failed to emit a zext!");
1074 ArgVT = VA.getLocVT();
1077 case CCValAssign::AExt: {
1078 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1081 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1084 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1087 assert(Emitted && "Failed to emit a aext!");
1088 ArgVT = VA.getLocVT();
1093 if (VA.isRegLoc()) {
1094 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1095 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1097 assert(Emitted && "Failed to emit a copy instruction!");
1098 RegArgs.push_back(VA.getLocReg());
1100 unsigned LocMemOffset = VA.getLocMemOffset();
1102 AM.Base.Reg = StackPtr;
1103 AM.Disp = LocMemOffset;
1104 Value *ArgVal = ArgVals[VA.getValNo()];
1106 // If this is a really simple value, emit this with the Value* version of
1107 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1108 // can cause us to reevaluate the argument.
1109 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1110 X86FastEmitStore(ArgVT, ArgVal, AM);
1112 X86FastEmitStore(ArgVT, Arg, AM);
1116 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1118 if (!Subtarget->is64Bit() &&
1119 TM.getRelocationModel() == Reloc::PIC_ &&
1120 Subtarget->isPICStyleGOT()) {
1121 TargetRegisterClass *RC = X86::GR32RegisterClass;
1122 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1123 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1124 assert(Emitted && "Failed to emit a copy instruction!");
1128 unsigned CallOpc = CalleeOp
1129 ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
1130 : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
1131 MachineInstrBuilder MIB = CalleeOp
1132 ? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp)
1133 : BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(GV);
1135 // Add an implicit use GOT pointer in EBX.
1136 if (!Subtarget->is64Bit() &&
1137 TM.getRelocationModel() == Reloc::PIC_ &&
1138 Subtarget->isPICStyleGOT())
1139 MIB.addReg(X86::EBX);
1141 // Add implicit physical register uses to the call.
1142 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1143 MIB.addReg(RegArgs[i]);
1145 // Issue CALLSEQ_END
1146 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1147 BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1149 // Now handle call return value (if any).
1150 if (RetVT.getSimpleVT() != MVT::isVoid) {
1151 SmallVector<CCValAssign, 16> RVLocs;
1152 CCState CCInfo(CC, false, TM, RVLocs);
1153 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1155 // Copy all of the result registers out of their specified physreg.
1156 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1157 MVT CopyVT = RVLocs[0].getValVT();
1158 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1159 TargetRegisterClass *SrcRC = DstRC;
1161 // If this is a call to a function that returns an fp value on the x87 fp
1162 // stack, but where we prefer to use the value in xmm registers, copy it
1163 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1164 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1165 RVLocs[0].getLocReg() == X86::ST1) &&
1166 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1168 SrcRC = X86::RSTRegisterClass;
1169 DstRC = X86::RFP80RegisterClass;
1172 unsigned ResultReg = createResultReg(DstRC);
1173 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1174 RVLocs[0].getLocReg(), DstRC, SrcRC);
1175 assert(Emitted && "Failed to emit a copy instruction!");
1176 if (CopyVT != RVLocs[0].getValVT()) {
1177 // Round the F80 the right size, which also moves to the appropriate xmm
1178 // register. This is accomplished by storing the F80 value in memory and
1179 // then loading it back. Ewww...
1180 MVT ResVT = RVLocs[0].getValVT();
1181 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1182 unsigned MemSize = ResVT.getSizeInBits()/8;
1183 int FI = MFI.CreateStackObject(MemSize, MemSize);
1184 addFrameReference(BuildMI(MBB, TII.get(Opc)), FI).addReg(ResultReg);
1185 DstRC = ResVT == MVT::f32
1186 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1187 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1188 ResultReg = createResultReg(DstRC);
1189 addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI);
1193 // Mask out all but lowest bit for some call which produces an i1.
1194 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1195 BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1196 ResultReg = AndResult;
1199 UpdateValueMap(I, ResultReg);
1207 X86FastISel::TargetSelectInstruction(Instruction *I) {
1208 switch (I->getOpcode()) {
1210 case Instruction::Load:
1211 return X86SelectLoad(I);
1212 case Instruction::Store:
1213 return X86SelectStore(I);
1214 case Instruction::ICmp:
1215 case Instruction::FCmp:
1216 return X86SelectCmp(I);
1217 case Instruction::ZExt:
1218 return X86SelectZExt(I);
1219 case Instruction::Br:
1220 return X86SelectBranch(I);
1221 case Instruction::Call:
1222 return X86SelectCall(I);
1223 case Instruction::LShr:
1224 case Instruction::AShr:
1225 case Instruction::Shl:
1226 return X86SelectShift(I);
1227 case Instruction::Select:
1228 return X86SelectSelect(I);
1229 case Instruction::Trunc:
1230 return X86SelectTrunc(I);
1231 case Instruction::FPExt:
1232 return X86SelectFPExt(I);
1233 case Instruction::FPTrunc:
1234 return X86SelectFPTrunc(I);
1240 unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
1242 if (!isTypeLegal(C->getType(), VT))
1245 // Get opcode and regclass of the output for the given load instruction.
1247 const TargetRegisterClass *RC = NULL;
1248 switch (VT.getSimpleVT()) {
1249 default: return false;
1252 RC = X86::GR8RegisterClass;
1256 RC = X86::GR16RegisterClass;
1260 RC = X86::GR32RegisterClass;
1263 // Must be in x86-64 mode.
1265 RC = X86::GR64RegisterClass;
1268 if (Subtarget->hasSSE1()) {
1270 RC = X86::FR32RegisterClass;
1272 Opc = X86::LD_Fp32m;
1273 RC = X86::RFP32RegisterClass;
1277 if (Subtarget->hasSSE2()) {
1279 RC = X86::FR64RegisterClass;
1281 Opc = X86::LD_Fp64m;
1282 RC = X86::RFP64RegisterClass;
1286 // No f80 support yet.
1290 // Materialize addresses with LEA instructions.
1291 if (isa<GlobalValue>(C)) {
1293 if (X86SelectAddress(C, AM, false)) {
1294 if (TLI.getPointerTy() == MVT::i32)
1298 unsigned ResultReg = createResultReg(RC);
1299 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
1305 // MachineConstantPool wants an explicit alignment.
1306 unsigned Align = TD.getPreferredTypeAlignmentShift(C->getType());
1308 // Alignment of vector types. FIXME!
1309 Align = TD.getABITypeSize(C->getType());
1310 Align = Log2_64(Align);
1313 // x86-32 PIC requires a PIC base register for constant pools.
1314 unsigned PICBase = 0;
1315 if (TM.getRelocationModel() == Reloc::PIC_ &&
1316 !Subtarget->is64Bit())
1317 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1319 // Create the load from the constant pool.
1320 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1321 unsigned ResultReg = createResultReg(RC);
1322 addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset,
1328 unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
1329 // Fail on dynamic allocas. At this point, getRegForValue has already
1330 // checked its CSE maps, so if we're here trying to handle a dynamic
1331 // alloca, we're not going to succeed. X86SelectAddress has a
1332 // check for dynamic allocas, because it's called directly from
1333 // various places, but TargetMaterializeAlloca also needs a check
1334 // in order to avoid recursion between getRegForValue,
1335 // X86SelectAddrss, and TargetMaterializeAlloca.
1336 if (!StaticAllocaMap.count(C))
1340 if (!X86SelectAddress(C, AM, false))
1342 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1343 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1344 unsigned ResultReg = createResultReg(RC);
1345 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
1350 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1351 MachineModuleInfo *mmi,
1352 DenseMap<const Value *, unsigned> &vm,
1353 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1354 DenseMap<const AllocaInst *, int> &am
1356 , SmallSet<Instruction*, 8> &cil
1359 return new X86FastISel(mf, mmi, vm, bm, am