1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/GlobalAlias.h"
31 #include "llvm/IR/GlobalVariable.h"
32 #include "llvm/IR/Instructions.h"
33 #include "llvm/IR/IntrinsicInst.h"
34 #include "llvm/IR/Operator.h"
35 #include "llvm/Support/CallSite.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/GetElementPtrTypeIterator.h"
38 #include "llvm/Target/TargetOptions.h"
43 class X86FastISel : public FastISel {
44 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
45 /// make the right decision when generating code for different targets.
46 const X86Subtarget *Subtarget;
48 /// RegInfo - X86 register info.
50 const X86RegisterInfo *RegInfo;
52 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
53 /// floating point ops.
54 /// When SSE is available, use it for f32 operations.
55 /// When SSE2 is available, use it for f64 operations.
60 explicit X86FastISel(FunctionLoweringInfo &funcInfo,
61 const TargetLibraryInfo *libInfo)
62 : FastISel(funcInfo, libInfo) {
63 Subtarget = &TM.getSubtarget<X86Subtarget>();
64 X86ScalarSSEf64 = Subtarget->hasSSE2();
65 X86ScalarSSEf32 = Subtarget->hasSSE1();
66 RegInfo = static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
69 virtual bool TargetSelectInstruction(const Instruction *I);
71 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
72 /// vreg is being provided by the specified load instruction. If possible,
73 /// try to fold the load as an operand to the instruction, returning true if
75 virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
78 virtual bool FastLowerArguments();
80 #include "X86GenFastISel.inc"
83 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
85 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
87 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM);
88 bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM);
90 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
93 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
94 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
96 bool X86SelectLoad(const Instruction *I);
98 bool X86SelectStore(const Instruction *I);
100 bool X86SelectRet(const Instruction *I);
102 bool X86SelectCmp(const Instruction *I);
104 bool X86SelectZExt(const Instruction *I);
106 bool X86SelectBranch(const Instruction *I);
108 bool X86SelectShift(const Instruction *I);
110 bool X86SelectSelect(const Instruction *I);
112 bool X86SelectTrunc(const Instruction *I);
114 bool X86SelectFPExt(const Instruction *I);
115 bool X86SelectFPTrunc(const Instruction *I);
117 bool X86VisitIntrinsicCall(const IntrinsicInst &I);
118 bool X86SelectCall(const Instruction *I);
120 bool DoSelectCall(const Instruction *I, const char *MemIntName);
122 const X86InstrInfo *getInstrInfo() const {
123 return getTargetMachine()->getInstrInfo();
125 const X86TargetMachine *getTargetMachine() const {
126 return static_cast<const X86TargetMachine *>(&TM);
129 unsigned TargetMaterializeConstant(const Constant *C);
131 unsigned TargetMaterializeAlloca(const AllocaInst *C);
133 unsigned TargetMaterializeFloatZero(const ConstantFP *CF);
135 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
136 /// computed in an SSE register, not on the X87 floating point stack.
137 bool isScalarFPTypeInSSEReg(EVT VT) const {
138 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
139 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
142 bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false);
144 bool IsMemcpySmall(uint64_t Len);
146 bool TryEmitSmallMemcpy(X86AddressMode DestAM,
147 X86AddressMode SrcAM, uint64_t Len);
150 } // end anonymous namespace.
152 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
153 EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true);
154 if (evt == MVT::Other || !evt.isSimple())
155 // Unhandled type. Halt "fast" selection and bail.
158 VT = evt.getSimpleVT();
159 // For now, require SSE/SSE2 for performing floating-point operations,
160 // since x87 requires additional work.
161 if (VT == MVT::f64 && !X86ScalarSSEf64)
163 if (VT == MVT::f32 && !X86ScalarSSEf32)
165 // Similarly, no f80 support yet.
168 // We only handle legal types. For example, on x86-32 the instruction
169 // selector contains all of the 64-bit instructions from x86-64,
170 // under the assumption that i64 won't be used if the target doesn't
172 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
175 #include "X86GenCallingConv.inc"
177 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
178 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
179 /// Return true and the result register by reference if it is possible.
180 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
181 unsigned &ResultReg) {
182 // Get opcode and regclass of the output for the given load instruction.
184 const TargetRegisterClass *RC = NULL;
185 switch (VT.getSimpleVT().SimpleTy) {
186 default: return false;
190 RC = &X86::GR8RegClass;
194 RC = &X86::GR16RegClass;
198 RC = &X86::GR32RegClass;
201 // Must be in x86-64 mode.
203 RC = &X86::GR64RegClass;
206 if (X86ScalarSSEf32) {
207 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
208 RC = &X86::FR32RegClass;
211 RC = &X86::RFP32RegClass;
215 if (X86ScalarSSEf64) {
216 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
217 RC = &X86::FR64RegClass;
220 RC = &X86::RFP64RegClass;
224 // No f80 support yet.
228 ResultReg = createResultReg(RC);
229 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
230 DL, TII.get(Opc), ResultReg), AM);
234 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
235 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
236 /// and a displacement offset, or a GlobalAddress,
237 /// i.e. V. Return true if it is possible.
239 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) {
240 // Get opcode and regclass of the output for the given store instruction.
242 switch (VT.getSimpleVT().SimpleTy) {
243 case MVT::f80: // No f80 support yet.
244 default: return false;
246 // Mask out all but lowest bit.
247 unsigned AndResult = createResultReg(&X86::GR8RegClass);
248 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
249 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
252 // FALLTHROUGH, handling i1 as i8.
253 case MVT::i8: Opc = X86::MOV8mr; break;
254 case MVT::i16: Opc = X86::MOV16mr; break;
255 case MVT::i32: Opc = X86::MOV32mr; break;
256 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
258 Opc = X86ScalarSSEf32 ?
259 (Subtarget->hasAVX() ? X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m;
262 Opc = X86ScalarSSEf64 ?
263 (Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m;
279 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
280 DL, TII.get(Opc)), AM).addReg(Val);
284 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
285 const X86AddressMode &AM) {
286 // Handle 'null' like i32/i64 0.
287 if (isa<ConstantPointerNull>(Val))
288 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
290 // If this is a store of a simple constant, fold the constant into the store.
291 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
294 switch (VT.getSimpleVT().SimpleTy) {
296 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
297 case MVT::i8: Opc = X86::MOV8mi; break;
298 case MVT::i16: Opc = X86::MOV16mi; break;
299 case MVT::i32: Opc = X86::MOV32mi; break;
301 // Must be a 32-bit sign extended value.
302 if (isInt<32>(CI->getSExtValue()))
303 Opc = X86::MOV64mi32;
308 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
309 DL, TII.get(Opc)), AM)
310 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
316 unsigned ValReg = getRegForValue(Val);
320 return X86FastEmitStore(VT, ValReg, AM);
323 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
324 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
325 /// ISD::SIGN_EXTEND).
326 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
327 unsigned Src, EVT SrcVT,
328 unsigned &ResultReg) {
329 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
330 Src, /*TODO: Kill=*/false);
338 /// X86SelectAddress - Attempt to fill in an address from the given value.
340 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
341 const User *U = NULL;
342 unsigned Opcode = Instruction::UserOp1;
343 if (const Instruction *I = dyn_cast<Instruction>(V)) {
344 // Don't walk into other basic blocks; it's possible we haven't
345 // visited them yet, so the instructions may not yet be assigned
346 // virtual registers.
347 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(V)) ||
348 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
349 Opcode = I->getOpcode();
352 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
353 Opcode = C->getOpcode();
357 if (PointerType *Ty = dyn_cast<PointerType>(V->getType()))
358 if (Ty->getAddressSpace() > 255)
359 // Fast instruction selection doesn't support the special
365 case Instruction::BitCast:
366 // Look past bitcasts.
367 return X86SelectAddress(U->getOperand(0), AM);
369 case Instruction::IntToPtr:
370 // Look past no-op inttoptrs.
371 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
372 return X86SelectAddress(U->getOperand(0), AM);
375 case Instruction::PtrToInt:
376 // Look past no-op ptrtoints.
377 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
378 return X86SelectAddress(U->getOperand(0), AM);
381 case Instruction::Alloca: {
382 // Do static allocas.
383 const AllocaInst *A = cast<AllocaInst>(V);
384 DenseMap<const AllocaInst*, int>::iterator SI =
385 FuncInfo.StaticAllocaMap.find(A);
386 if (SI != FuncInfo.StaticAllocaMap.end()) {
387 AM.BaseType = X86AddressMode::FrameIndexBase;
388 AM.Base.FrameIndex = SI->second;
394 case Instruction::Add: {
395 // Adds of constants are common and easy enough.
396 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
397 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
398 // They have to fit in the 32-bit signed displacement field though.
399 if (isInt<32>(Disp)) {
400 AM.Disp = (uint32_t)Disp;
401 return X86SelectAddress(U->getOperand(0), AM);
407 case Instruction::GetElementPtr: {
408 X86AddressMode SavedAM = AM;
410 // Pattern-match simple GEPs.
411 uint64_t Disp = (int32_t)AM.Disp;
412 unsigned IndexReg = AM.IndexReg;
413 unsigned Scale = AM.Scale;
414 gep_type_iterator GTI = gep_type_begin(U);
415 // Iterate through the indices, folding what we can. Constants can be
416 // folded, and one dynamic index can be handled, if the scale is supported.
417 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
418 i != e; ++i, ++GTI) {
419 const Value *Op = *i;
420 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
421 const StructLayout *SL = TD.getStructLayout(STy);
422 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue());
426 // A array/variable index is always of the form i*S where S is the
427 // constant scale size. See if we can push the scale into immediates.
428 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
430 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
431 // Constant-offset addressing.
432 Disp += CI->getSExtValue() * S;
435 if (isa<AddOperator>(Op) &&
436 (!isa<Instruction>(Op) ||
437 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
439 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
440 // An add (in the same block) with a constant operand. Fold the
443 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
444 Disp += CI->getSExtValue() * S;
445 // Iterate on the other operand.
446 Op = cast<AddOperator>(Op)->getOperand(0);
450 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
451 (S == 1 || S == 2 || S == 4 || S == 8)) {
452 // Scaled-index addressing.
454 IndexReg = getRegForGEPIndex(Op).first;
460 goto unsupported_gep;
463 // Check for displacement overflow.
464 if (!isInt<32>(Disp))
466 // Ok, the GEP indices were covered by constant-offset and scaled-index
467 // addressing. Update the address state and move on to examining the base.
468 AM.IndexReg = IndexReg;
470 AM.Disp = (uint32_t)Disp;
471 if (X86SelectAddress(U->getOperand(0), AM))
474 // If we couldn't merge the gep value into this addr mode, revert back to
475 // our address and just match the value instead of completely failing.
479 // Ok, the GEP indices weren't all covered.
484 // Handle constant address.
485 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
486 // Can't handle alternate code models yet.
487 if (TM.getCodeModel() != CodeModel::Small)
490 // Can't handle TLS yet.
491 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
492 if (GVar->isThreadLocal())
495 // Can't handle TLS yet, part 2 (this is slightly crazy, but this is how
497 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
498 if (const GlobalVariable *GVar =
499 dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)))
500 if (GVar->isThreadLocal())
503 // RIP-relative addresses can't have additional register operands, so if
504 // we've already folded stuff into the addressing mode, just force the
505 // global value into its own register, which we can use as the basereg.
506 if (!Subtarget->isPICStyleRIPRel() ||
507 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
508 // Okay, we've committed to selecting this global. Set up the address.
511 // Allow the subtarget to classify the global.
512 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
514 // If this reference is relative to the pic base, set it now.
515 if (isGlobalRelativeToPICBase(GVFlags)) {
516 // FIXME: How do we know Base.Reg is free??
517 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
520 // Unless the ABI requires an extra load, return a direct reference to
522 if (!isGlobalStubReference(GVFlags)) {
523 if (Subtarget->isPICStyleRIPRel()) {
524 // Use rip-relative addressing if we can. Above we verified that the
525 // base and index registers are unused.
526 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
527 AM.Base.Reg = X86::RIP;
529 AM.GVOpFlags = GVFlags;
533 // Ok, we need to do a load from a stub. If we've already loaded from
534 // this stub, reuse the loaded pointer, otherwise emit the load now.
535 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
537 if (I != LocalValueMap.end() && I->second != 0) {
540 // Issue load from stub.
542 const TargetRegisterClass *RC = NULL;
543 X86AddressMode StubAM;
544 StubAM.Base.Reg = AM.Base.Reg;
546 StubAM.GVOpFlags = GVFlags;
548 // Prepare for inserting code in the local-value area.
549 SavePoint SaveInsertPt = enterLocalValueArea();
551 if (TLI.getPointerTy() == MVT::i64) {
553 RC = &X86::GR64RegClass;
555 if (Subtarget->isPICStyleRIPRel())
556 StubAM.Base.Reg = X86::RIP;
559 RC = &X86::GR32RegClass;
562 LoadReg = createResultReg(RC);
563 MachineInstrBuilder LoadMI =
564 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg);
565 addFullAddress(LoadMI, StubAM);
567 // Ok, back to normal mode.
568 leaveLocalValueArea(SaveInsertPt);
570 // Prevent loading GV stub multiple times in same MBB.
571 LocalValueMap[V] = LoadReg;
574 // Now construct the final address. Note that the Disp, Scale,
575 // and Index values may already be set here.
576 AM.Base.Reg = LoadReg;
582 // If all else fails, try to materialize the value in a register.
583 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
584 if (AM.Base.Reg == 0) {
585 AM.Base.Reg = getRegForValue(V);
586 return AM.Base.Reg != 0;
588 if (AM.IndexReg == 0) {
589 assert(AM.Scale == 1 && "Scale with no index!");
590 AM.IndexReg = getRegForValue(V);
591 return AM.IndexReg != 0;
598 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
600 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
601 const User *U = NULL;
602 unsigned Opcode = Instruction::UserOp1;
603 if (const Instruction *I = dyn_cast<Instruction>(V)) {
604 Opcode = I->getOpcode();
606 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
607 Opcode = C->getOpcode();
613 case Instruction::BitCast:
614 // Look past bitcasts.
615 return X86SelectCallAddress(U->getOperand(0), AM);
617 case Instruction::IntToPtr:
618 // Look past no-op inttoptrs.
619 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
620 return X86SelectCallAddress(U->getOperand(0), AM);
623 case Instruction::PtrToInt:
624 // Look past no-op ptrtoints.
625 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
626 return X86SelectCallAddress(U->getOperand(0), AM);
630 // Handle constant address.
631 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
632 // Can't handle alternate code models yet.
633 if (TM.getCodeModel() != CodeModel::Small)
636 // RIP-relative addresses can't have additional register operands.
637 if (Subtarget->isPICStyleRIPRel() &&
638 (AM.Base.Reg != 0 || AM.IndexReg != 0))
641 // Can't handle DLLImport.
642 if (GV->hasDLLImportLinkage())
646 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
647 if (GVar->isThreadLocal())
650 // Okay, we've committed to selecting this global. Set up the basic address.
653 // No ABI requires an extra load for anything other than DLLImport, which
654 // we rejected above. Return a direct reference to the global.
655 if (Subtarget->isPICStyleRIPRel()) {
656 // Use rip-relative addressing if we can. Above we verified that the
657 // base and index registers are unused.
658 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
659 AM.Base.Reg = X86::RIP;
660 } else if (Subtarget->isPICStyleStubPIC()) {
661 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
662 } else if (Subtarget->isPICStyleGOT()) {
663 AM.GVOpFlags = X86II::MO_GOTOFF;
669 // If all else fails, try to materialize the value in a register.
670 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
671 if (AM.Base.Reg == 0) {
672 AM.Base.Reg = getRegForValue(V);
673 return AM.Base.Reg != 0;
675 if (AM.IndexReg == 0) {
676 assert(AM.Scale == 1 && "Scale with no index!");
677 AM.IndexReg = getRegForValue(V);
678 return AM.IndexReg != 0;
686 /// X86SelectStore - Select and emit code to implement store instructions.
687 bool X86FastISel::X86SelectStore(const Instruction *I) {
688 // Atomic stores need special handling.
689 const StoreInst *S = cast<StoreInst>(I);
694 unsigned SABIAlignment =
695 TD.getABITypeAlignment(S->getValueOperand()->getType());
696 if (S->getAlignment() != 0 && S->getAlignment() < SABIAlignment)
700 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
704 if (!X86SelectAddress(I->getOperand(1), AM))
707 return X86FastEmitStore(VT, I->getOperand(0), AM);
710 /// X86SelectRet - Select and emit code to implement ret instructions.
711 bool X86FastISel::X86SelectRet(const Instruction *I) {
712 const ReturnInst *Ret = cast<ReturnInst>(I);
713 const Function &F = *I->getParent()->getParent();
714 const X86MachineFunctionInfo *X86MFInfo =
715 FuncInfo.MF->getInfo<X86MachineFunctionInfo>();
717 if (!FuncInfo.CanLowerReturn)
720 CallingConv::ID CC = F.getCallingConv();
721 if (CC != CallingConv::C &&
722 CC != CallingConv::Fast &&
723 CC != CallingConv::X86_FastCall)
726 if (Subtarget->isTargetWin64())
729 // Don't handle popping bytes on return for now.
730 if (X86MFInfo->getBytesToPopOnReturn() != 0)
733 // fastcc with -tailcallopt is intended to provide a guaranteed
734 // tail call optimization. Fastisel doesn't know how to do that.
735 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt)
738 // Let SDISel handle vararg functions.
742 // Build a list of return value registers.
743 SmallVector<unsigned, 4> RetRegs;
745 if (Ret->getNumOperands() > 0) {
746 SmallVector<ISD::OutputArg, 4> Outs;
747 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
749 // Analyze operands of the call, assigning locations to each operand.
750 SmallVector<CCValAssign, 16> ValLocs;
751 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,
753 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
755 const Value *RV = Ret->getOperand(0);
756 unsigned Reg = getRegForValue(RV);
760 // Only handle a single return value for now.
761 if (ValLocs.size() != 1)
764 CCValAssign &VA = ValLocs[0];
766 // Don't bother handling odd stuff for now.
767 if (VA.getLocInfo() != CCValAssign::Full)
769 // Only handle register returns for now.
773 // The calling-convention tables for x87 returns don't tell
775 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
778 unsigned SrcReg = Reg + VA.getValNo();
779 EVT SrcVT = TLI.getValueType(RV->getType());
780 EVT DstVT = VA.getValVT();
781 // Special handling for extended integers.
782 if (SrcVT != DstVT) {
783 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
786 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
789 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
791 if (SrcVT == MVT::i1) {
792 if (Outs[0].Flags.isSExt())
794 SrcReg = FastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
797 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
799 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
800 SrcReg, /*TODO: Kill=*/false);
804 unsigned DstReg = VA.getLocReg();
805 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
806 // Avoid a cross-class copy. This is very unlikely.
807 if (!SrcRC->contains(DstReg))
809 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
810 DstReg).addReg(SrcReg);
812 // Add register to return instruction.
813 RetRegs.push_back(VA.getLocReg());
816 // The x86-64 ABI for returning structs by value requires that we copy
817 // the sret argument into %rax for the return. We saved the argument into
818 // a virtual register in the entry block, so now we copy the value out
820 if (Subtarget->is64Bit() && F.hasStructRetAttr()) {
821 unsigned Reg = X86MFInfo->getSRetReturnReg();
823 "SRetReturnReg should have been set in LowerFormalArguments()!");
824 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
825 X86::RAX).addReg(Reg);
826 RetRegs.push_back(X86::RAX);
830 MachineInstrBuilder MIB =
831 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
832 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
833 MIB.addReg(RetRegs[i], RegState::Implicit);
837 /// X86SelectLoad - Select and emit code to implement load instructions.
839 bool X86FastISel::X86SelectLoad(const Instruction *I) {
840 // Atomic loads need special handling.
841 if (cast<LoadInst>(I)->isAtomic())
845 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
849 if (!X86SelectAddress(I->getOperand(0), AM))
852 unsigned ResultReg = 0;
853 if (X86FastEmitLoad(VT, AM, ResultReg)) {
854 UpdateValueMap(I, ResultReg);
860 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) {
861 bool HasAVX = Subtarget->hasAVX();
862 bool X86ScalarSSEf32 = Subtarget->hasSSE1();
863 bool X86ScalarSSEf64 = Subtarget->hasSSE2();
865 switch (VT.getSimpleVT().SimpleTy) {
867 case MVT::i8: return X86::CMP8rr;
868 case MVT::i16: return X86::CMP16rr;
869 case MVT::i32: return X86::CMP32rr;
870 case MVT::i64: return X86::CMP64rr;
872 return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0;
874 return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0;
878 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
879 /// of the comparison, return an opcode that works for the compare (e.g.
880 /// CMP32ri) otherwise return 0.
881 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
882 switch (VT.getSimpleVT().SimpleTy) {
883 // Otherwise, we can't fold the immediate into this comparison.
885 case MVT::i8: return X86::CMP8ri;
886 case MVT::i16: return X86::CMP16ri;
887 case MVT::i32: return X86::CMP32ri;
889 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
891 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
892 return X86::CMP64ri32;
897 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
899 unsigned Op0Reg = getRegForValue(Op0);
900 if (Op0Reg == 0) return false;
902 // Handle 'null' like i32/i64 0.
903 if (isa<ConstantPointerNull>(Op1))
904 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
906 // We have two options: compare with register or immediate. If the RHS of
907 // the compare is an immediate that we can fold into this compare, use
908 // CMPri, otherwise use CMPrr.
909 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
910 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
911 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
913 .addImm(Op1C->getSExtValue());
918 unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget);
919 if (CompareOpc == 0) return false;
921 unsigned Op1Reg = getRegForValue(Op1);
922 if (Op1Reg == 0) return false;
923 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc))
930 bool X86FastISel::X86SelectCmp(const Instruction *I) {
931 const CmpInst *CI = cast<CmpInst>(I);
934 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
937 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
939 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
940 switch (CI->getPredicate()) {
941 case CmpInst::FCMP_OEQ: {
942 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
945 unsigned EReg = createResultReg(&X86::GR8RegClass);
946 unsigned NPReg = createResultReg(&X86::GR8RegClass);
947 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
948 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
949 TII.get(X86::SETNPr), NPReg);
950 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
951 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
952 UpdateValueMap(I, ResultReg);
955 case CmpInst::FCMP_UNE: {
956 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
959 unsigned NEReg = createResultReg(&X86::GR8RegClass);
960 unsigned PReg = createResultReg(&X86::GR8RegClass);
961 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETNEr), NEReg);
962 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETPr), PReg);
963 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::OR8rr),ResultReg)
964 .addReg(PReg).addReg(NEReg);
965 UpdateValueMap(I, ResultReg);
968 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
969 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
970 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
971 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
972 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
973 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
974 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
975 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
976 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
977 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
978 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
979 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
981 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
982 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
983 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
984 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
985 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
986 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
987 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
988 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
989 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
990 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
995 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
999 // Emit a compare of Op0/Op1.
1000 if (!X86FastEmitCompare(Op0, Op1, VT))
1003 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg);
1004 UpdateValueMap(I, ResultReg);
1008 bool X86FastISel::X86SelectZExt(const Instruction *I) {
1009 // Handle zero-extension from i1 to i8, which is common.
1010 if (!I->getOperand(0)->getType()->isIntegerTy(1))
1013 EVT DstVT = TLI.getValueType(I->getType());
1014 if (!TLI.isTypeLegal(DstVT))
1017 unsigned ResultReg = getRegForValue(I->getOperand(0));
1021 // Set the high bits to zero.
1022 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
1026 if (DstVT != MVT::i8) {
1027 ResultReg = FastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND,
1028 ResultReg, /*Kill=*/true);
1033 UpdateValueMap(I, ResultReg);
1038 bool X86FastISel::X86SelectBranch(const Instruction *I) {
1039 // Unconditional branches are selected by tablegen-generated code.
1040 // Handle a conditional branch.
1041 const BranchInst *BI = cast<BranchInst>(I);
1042 MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1043 MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1045 // Fold the common case of a conditional branch with a comparison
1046 // in the same block (values defined on other blocks may not have
1047 // initialized registers).
1048 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1049 if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
1050 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
1052 // Try to take advantage of fallthrough opportunities.
1053 CmpInst::Predicate Predicate = CI->getPredicate();
1054 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
1055 std::swap(TrueMBB, FalseMBB);
1056 Predicate = CmpInst::getInversePredicate(Predicate);
1059 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
1060 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
1062 switch (Predicate) {
1063 case CmpInst::FCMP_OEQ:
1064 std::swap(TrueMBB, FalseMBB);
1065 Predicate = CmpInst::FCMP_UNE;
1067 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1068 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1069 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1070 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
1071 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
1072 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1073 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
1074 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
1075 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1076 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
1077 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
1078 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1079 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1081 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1082 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1083 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1084 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1085 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1086 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1087 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
1088 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
1089 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
1090 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
1095 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
1097 std::swap(Op0, Op1);
1099 // Emit a compare of the LHS and RHS, setting the flags.
1100 if (!X86FastEmitCompare(Op0, Op1, VT))
1103 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc))
1106 if (Predicate == CmpInst::FCMP_UNE) {
1107 // X86 requires a second branch to handle UNE (and OEQ,
1108 // which is mapped to UNE above).
1109 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
1113 FastEmitBranch(FalseMBB, DL);
1114 FuncInfo.MBB->addSuccessor(TrueMBB);
1117 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1118 // Handle things like "%cond = trunc i32 %X to i1 / br i1 %cond", which
1119 // typically happen for _Bool and C++ bools.
1121 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1122 isTypeLegal(TI->getOperand(0)->getType(), SourceVT)) {
1123 unsigned TestOpc = 0;
1124 switch (SourceVT.SimpleTy) {
1126 case MVT::i8: TestOpc = X86::TEST8ri; break;
1127 case MVT::i16: TestOpc = X86::TEST16ri; break;
1128 case MVT::i32: TestOpc = X86::TEST32ri; break;
1129 case MVT::i64: TestOpc = X86::TEST64ri32; break;
1132 unsigned OpReg = getRegForValue(TI->getOperand(0));
1133 if (OpReg == 0) return false;
1134 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TestOpc))
1135 .addReg(OpReg).addImm(1);
1137 unsigned JmpOpc = X86::JNE_4;
1138 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
1139 std::swap(TrueMBB, FalseMBB);
1143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(JmpOpc))
1145 FastEmitBranch(FalseMBB, DL);
1146 FuncInfo.MBB->addSuccessor(TrueMBB);
1152 // Otherwise do a clumsy setcc and re-test it.
1153 // Note that i1 essentially gets ANY_EXTEND'ed to i8 where it isn't used
1154 // in an explicit cast, so make sure to handle that correctly.
1155 unsigned OpReg = getRegForValue(BI->getCondition());
1156 if (OpReg == 0) return false;
1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
1159 .addReg(OpReg).addImm(1);
1160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1162 FastEmitBranch(FalseMBB, DL);
1163 FuncInfo.MBB->addSuccessor(TrueMBB);
1167 bool X86FastISel::X86SelectShift(const Instruction *I) {
1168 unsigned CReg = 0, OpReg = 0;
1169 const TargetRegisterClass *RC = NULL;
1170 if (I->getType()->isIntegerTy(8)) {
1172 RC = &X86::GR8RegClass;
1173 switch (I->getOpcode()) {
1174 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1175 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1176 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1177 default: return false;
1179 } else if (I->getType()->isIntegerTy(16)) {
1181 RC = &X86::GR16RegClass;
1182 switch (I->getOpcode()) {
1183 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1184 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1185 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1186 default: return false;
1188 } else if (I->getType()->isIntegerTy(32)) {
1190 RC = &X86::GR32RegClass;
1191 switch (I->getOpcode()) {
1192 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1193 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1194 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1195 default: return false;
1197 } else if (I->getType()->isIntegerTy(64)) {
1199 RC = &X86::GR64RegClass;
1200 switch (I->getOpcode()) {
1201 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1202 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1203 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1204 default: return false;
1211 if (!isTypeLegal(I->getType(), VT))
1214 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1215 if (Op0Reg == 0) return false;
1217 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1218 if (Op1Reg == 0) return false;
1219 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1220 CReg).addReg(Op1Reg);
1222 // The shift instruction uses X86::CL. If we defined a super-register
1223 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1224 if (CReg != X86::CL)
1225 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1226 TII.get(TargetOpcode::KILL), X86::CL)
1227 .addReg(CReg, RegState::Kill);
1229 unsigned ResultReg = createResultReg(RC);
1230 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg)
1232 UpdateValueMap(I, ResultReg);
1236 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1238 if (!isTypeLegal(I->getType(), VT))
1241 // We only use cmov here, if we don't have a cmov instruction bail.
1242 if (!Subtarget->hasCMov()) return false;
1245 const TargetRegisterClass *RC = NULL;
1246 if (VT == MVT::i16) {
1247 Opc = X86::CMOVE16rr;
1248 RC = &X86::GR16RegClass;
1249 } else if (VT == MVT::i32) {
1250 Opc = X86::CMOVE32rr;
1251 RC = &X86::GR32RegClass;
1252 } else if (VT == MVT::i64) {
1253 Opc = X86::CMOVE64rr;
1254 RC = &X86::GR64RegClass;
1259 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1260 if (Op0Reg == 0) return false;
1261 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1262 if (Op1Reg == 0) return false;
1263 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1264 if (Op2Reg == 0) return false;
1266 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1267 .addReg(Op0Reg).addReg(Op0Reg);
1268 unsigned ResultReg = createResultReg(RC);
1269 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1270 .addReg(Op1Reg).addReg(Op2Reg);
1271 UpdateValueMap(I, ResultReg);
1275 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
1276 // fpext from float to double.
1277 if (X86ScalarSSEf64 &&
1278 I->getType()->isDoubleTy()) {
1279 const Value *V = I->getOperand(0);
1280 if (V->getType()->isFloatTy()) {
1281 unsigned OpReg = getRegForValue(V);
1282 if (OpReg == 0) return false;
1283 unsigned ResultReg = createResultReg(&X86::FR64RegClass);
1284 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1285 TII.get(X86::CVTSS2SDrr), ResultReg)
1287 UpdateValueMap(I, ResultReg);
1295 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
1296 if (X86ScalarSSEf64) {
1297 if (I->getType()->isFloatTy()) {
1298 const Value *V = I->getOperand(0);
1299 if (V->getType()->isDoubleTy()) {
1300 unsigned OpReg = getRegForValue(V);
1301 if (OpReg == 0) return false;
1302 unsigned ResultReg = createResultReg(&X86::FR32RegClass);
1303 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1304 TII.get(X86::CVTSD2SSrr), ResultReg)
1306 UpdateValueMap(I, ResultReg);
1315 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
1316 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1317 EVT DstVT = TLI.getValueType(I->getType());
1319 // This code only handles truncation to byte.
1320 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1322 if (!TLI.isTypeLegal(SrcVT))
1325 unsigned InputReg = getRegForValue(I->getOperand(0));
1327 // Unhandled operand. Halt "fast" selection and bail.
1330 if (SrcVT == MVT::i8) {
1331 // Truncate from i8 to i1; no code needed.
1332 UpdateValueMap(I, InputReg);
1336 if (!Subtarget->is64Bit()) {
1337 // If we're on x86-32; we can't extract an i8 from a general register.
1338 // First issue a copy to GR16_ABCD or GR32_ABCD.
1339 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) ?
1340 (const TargetRegisterClass*)&X86::GR16_ABCDRegClass :
1341 (const TargetRegisterClass*)&X86::GR32_ABCDRegClass;
1342 unsigned CopyReg = createResultReg(CopyRC);
1343 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1344 CopyReg).addReg(InputReg);
1348 // Issue an extract_subreg.
1349 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1350 InputReg, /*Kill=*/true,
1355 UpdateValueMap(I, ResultReg);
1359 bool X86FastISel::IsMemcpySmall(uint64_t Len) {
1360 return Len <= (Subtarget->is64Bit() ? 32 : 16);
1363 bool X86FastISel::TryEmitSmallMemcpy(X86AddressMode DestAM,
1364 X86AddressMode SrcAM, uint64_t Len) {
1366 // Make sure we don't bloat code by inlining very large memcpy's.
1367 if (!IsMemcpySmall(Len))
1370 bool i64Legal = Subtarget->is64Bit();
1372 // We don't care about alignment here since we just emit integer accesses.
1375 if (Len >= 8 && i64Legal)
1386 bool RV = X86FastEmitLoad(VT, SrcAM, Reg);
1387 RV &= X86FastEmitStore(VT, Reg, DestAM);
1388 assert(RV && "Failed to emit load or store??");
1390 unsigned Size = VT.getSizeInBits()/8;
1392 DestAM.Disp += Size;
1399 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
1400 // FIXME: Handle more intrinsics.
1401 switch (I.getIntrinsicID()) {
1402 default: return false;
1403 case Intrinsic::memcpy: {
1404 const MemCpyInst &MCI = cast<MemCpyInst>(I);
1405 // Don't handle volatile or variable length memcpys.
1406 if (MCI.isVolatile())
1409 if (isa<ConstantInt>(MCI.getLength())) {
1410 // Small memcpy's are common enough that we want to do them
1411 // without a call if possible.
1412 uint64_t Len = cast<ConstantInt>(MCI.getLength())->getZExtValue();
1413 if (IsMemcpySmall(Len)) {
1414 X86AddressMode DestAM, SrcAM;
1415 if (!X86SelectAddress(MCI.getRawDest(), DestAM) ||
1416 !X86SelectAddress(MCI.getRawSource(), SrcAM))
1418 TryEmitSmallMemcpy(DestAM, SrcAM, Len);
1423 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32;
1424 if (!MCI.getLength()->getType()->isIntegerTy(SizeWidth))
1427 if (MCI.getSourceAddressSpace() > 255 || MCI.getDestAddressSpace() > 255)
1430 return DoSelectCall(&I, "memcpy");
1432 case Intrinsic::memset: {
1433 const MemSetInst &MSI = cast<MemSetInst>(I);
1435 if (MSI.isVolatile())
1438 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32;
1439 if (!MSI.getLength()->getType()->isIntegerTy(SizeWidth))
1442 if (MSI.getDestAddressSpace() > 255)
1445 return DoSelectCall(&I, "memset");
1447 case Intrinsic::stackprotector: {
1448 // Emit code to store the stack guard onto the stack.
1449 EVT PtrTy = TLI.getPointerTy();
1451 const Value *Op1 = I.getArgOperand(0); // The guard's value.
1452 const AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
1454 // Grab the frame index.
1456 if (!X86SelectAddress(Slot, AM)) return false;
1457 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
1460 case Intrinsic::dbg_declare: {
1461 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I);
1463 assert(DI->getAddress() && "Null address should be checked earlier!");
1464 if (!X86SelectAddress(DI->getAddress(), AM))
1466 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1467 // FIXME may need to add RegState::Debug to any registers produced,
1468 // although ESP/EBP should be the only ones at the moment.
1469 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM).
1470 addImm(0).addMetadata(DI->getVariable());
1473 case Intrinsic::trap: {
1474 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1477 case Intrinsic::sadd_with_overflow:
1478 case Intrinsic::uadd_with_overflow: {
1479 // FIXME: Should fold immediates.
1481 // Replace "add with overflow" intrinsics with an "add" instruction followed
1482 // by a seto/setc instruction.
1483 const Function *Callee = I.getCalledFunction();
1485 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1488 if (!isTypeLegal(RetTy, VT))
1491 const Value *Op1 = I.getArgOperand(0);
1492 const Value *Op2 = I.getArgOperand(1);
1493 unsigned Reg1 = getRegForValue(Op1);
1494 unsigned Reg2 = getRegForValue(Op2);
1496 if (Reg1 == 0 || Reg2 == 0)
1497 // FIXME: Handle values *not* in registers.
1503 else if (VT == MVT::i64)
1508 // The call to CreateRegs builds two sequential registers, to store the
1509 // both the returned values.
1510 unsigned ResultReg = FuncInfo.CreateRegs(I.getType());
1511 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg)
1512 .addReg(Reg1).addReg(Reg2);
1514 unsigned Opc = X86::SETBr;
1515 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1517 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg+1);
1519 UpdateValueMap(&I, ResultReg, 2);
1525 bool X86FastISel::FastLowerArguments() {
1526 if (!FuncInfo.CanLowerReturn)
1529 const Function *F = FuncInfo.Fn;
1533 CallingConv::ID CC = F->getCallingConv();
1534 if (CC != CallingConv::C)
1537 if (!Subtarget->is64Bit())
1540 // Only handle simple cases. i.e. Up to 6 i32/i64 scalar arguments.
1542 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1543 I != E; ++I, ++Idx) {
1547 if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
1548 F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
1549 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
1550 F->getAttributes().hasAttribute(Idx, Attribute::Nest))
1553 Type *ArgTy = I->getType();
1554 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
1557 EVT ArgVT = TLI.getValueType(ArgTy);
1558 if (!ArgVT.isSimple()) return false;
1559 switch (ArgVT.getSimpleVT().SimpleTy) {
1568 static const uint16_t GPR32ArgRegs[] = {
1569 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1571 static const uint16_t GPR64ArgRegs[] = {
1572 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
1576 const TargetRegisterClass *RC32 = TLI.getRegClassFor(MVT::i32);
1577 const TargetRegisterClass *RC64 = TLI.getRegClassFor(MVT::i64);
1578 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1579 I != E; ++I, ++Idx) {
1582 bool is32Bit = TLI.getValueType(I->getType()) == MVT::i32;
1583 const TargetRegisterClass *RC = is32Bit ? RC32 : RC64;
1584 unsigned SrcReg = is32Bit ? GPR32ArgRegs[Idx] : GPR64ArgRegs[Idx];
1585 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
1586 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1587 // Without this, EmitLiveInCopies may eliminate the livein if its only
1588 // use is a bitcast (which isn't turned into an instruction).
1589 unsigned ResultReg = createResultReg(RC);
1590 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1591 ResultReg).addReg(DstReg, getKillRegState(true));
1592 UpdateValueMap(I, ResultReg);
1597 bool X86FastISel::X86SelectCall(const Instruction *I) {
1598 const CallInst *CI = cast<CallInst>(I);
1599 const Value *Callee = CI->getCalledValue();
1601 // Can't handle inline asm yet.
1602 if (isa<InlineAsm>(Callee))
1605 // Handle intrinsic calls.
1606 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1607 return X86VisitIntrinsicCall(*II);
1609 // Allow SelectionDAG isel to handle tail calls.
1610 if (cast<CallInst>(I)->isTailCall())
1613 return DoSelectCall(I, 0);
1616 static unsigned computeBytesPoppedByCallee(const X86Subtarget &Subtarget,
1617 const ImmutableCallSite &CS) {
1618 if (Subtarget.is64Bit())
1620 if (Subtarget.isTargetWindows())
1622 CallingConv::ID CC = CS.getCallingConv();
1623 if (CC == CallingConv::Fast || CC == CallingConv::GHC)
1625 if (!CS.paramHasAttr(1, Attribute::StructRet))
1627 if (CS.paramHasAttr(1, Attribute::InReg))
1632 // Select either a call, or an llvm.memcpy/memmove/memset intrinsic
1633 bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
1634 const CallInst *CI = cast<CallInst>(I);
1635 const Value *Callee = CI->getCalledValue();
1637 // Handle only C and fastcc calling conventions for now.
1638 ImmutableCallSite CS(CI);
1639 CallingConv::ID CC = CS.getCallingConv();
1640 if (CC != CallingConv::C && CC != CallingConv::Fast &&
1641 CC != CallingConv::X86_FastCall)
1644 // fastcc with -tailcallopt is intended to provide a guaranteed
1645 // tail call optimization. Fastisel doesn't know how to do that.
1646 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt)
1649 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1650 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1651 bool isVarArg = FTy->isVarArg();
1653 // Don't know how to handle Win64 varargs yet. Nothing special needed for
1654 // x86-32. Special handling for x86-64 is implemented.
1655 if (isVarArg && Subtarget->isTargetWin64())
1658 // Fast-isel doesn't know about callee-pop yet.
1659 if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg,
1660 TM.Options.GuaranteedTailCallOpt))
1663 // Check whether the function can return without sret-demotion.
1664 SmallVector<ISD::OutputArg, 4> Outs;
1665 GetReturnInfo(I->getType(), CS.getAttributes(), Outs, TLI);
1666 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
1667 *FuncInfo.MF, FTy->isVarArg(),
1668 Outs, FTy->getContext());
1669 if (!CanLowerReturn)
1672 // Materialize callee address in a register. FIXME: GV address can be
1673 // handled with a CALLpcrel32 instead.
1674 X86AddressMode CalleeAM;
1675 if (!X86SelectCallAddress(Callee, CalleeAM))
1677 unsigned CalleeOp = 0;
1678 const GlobalValue *GV = 0;
1679 if (CalleeAM.GV != 0) {
1681 } else if (CalleeAM.Base.Reg != 0) {
1682 CalleeOp = CalleeAM.Base.Reg;
1686 // Deal with call operands first.
1687 SmallVector<const Value *, 8> ArgVals;
1688 SmallVector<unsigned, 8> Args;
1689 SmallVector<MVT, 8> ArgVTs;
1690 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1691 unsigned arg_size = CS.arg_size();
1692 Args.reserve(arg_size);
1693 ArgVals.reserve(arg_size);
1694 ArgVTs.reserve(arg_size);
1695 ArgFlags.reserve(arg_size);
1696 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1698 // If we're lowering a mem intrinsic instead of a regular call, skip the
1699 // last two arguments, which should not passed to the underlying functions.
1700 if (MemIntName && e-i <= 2)
1703 ISD::ArgFlagsTy Flags;
1704 unsigned AttrInd = i - CS.arg_begin() + 1;
1705 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1707 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1710 if (CS.paramHasAttr(AttrInd, Attribute::ByVal)) {
1711 PointerType *Ty = cast<PointerType>(ArgVal->getType());
1712 Type *ElementTy = Ty->getElementType();
1713 unsigned FrameSize = TD.getTypeAllocSize(ElementTy);
1714 unsigned FrameAlign = CS.getParamAlignment(AttrInd);
1716 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
1718 Flags.setByValSize(FrameSize);
1719 Flags.setByValAlign(FrameAlign);
1720 if (!IsMemcpySmall(FrameSize))
1724 if (CS.paramHasAttr(AttrInd, Attribute::InReg))
1726 if (CS.paramHasAttr(AttrInd, Attribute::Nest))
1729 // If this is an i1/i8/i16 argument, promote to i32 to avoid an extra
1730 // instruction. This is safe because it is common to all fastisel supported
1731 // calling conventions on x86.
1732 if (ConstantInt *CI = dyn_cast<ConstantInt>(ArgVal)) {
1733 if (CI->getBitWidth() == 1 || CI->getBitWidth() == 8 ||
1734 CI->getBitWidth() == 16) {
1736 ArgVal = ConstantExpr::getSExt(CI,Type::getInt32Ty(CI->getContext()));
1738 ArgVal = ConstantExpr::getZExt(CI,Type::getInt32Ty(CI->getContext()));
1744 // Passing bools around ends up doing a trunc to i1 and passing it.
1745 // Codegen this as an argument + "and 1".
1746 if (ArgVal->getType()->isIntegerTy(1) && isa<TruncInst>(ArgVal) &&
1747 cast<TruncInst>(ArgVal)->getParent() == I->getParent() &&
1748 ArgVal->hasOneUse()) {
1749 ArgVal = cast<TruncInst>(ArgVal)->getOperand(0);
1750 ArgReg = getRegForValue(ArgVal);
1751 if (ArgReg == 0) return false;
1754 if (!isTypeLegal(ArgVal->getType(), ArgVT)) return false;
1756 ArgReg = FastEmit_ri(ArgVT, ArgVT, ISD::AND, ArgReg,
1757 ArgVal->hasOneUse(), 1);
1759 ArgReg = getRegForValue(ArgVal);
1762 if (ArgReg == 0) return false;
1764 Type *ArgTy = ArgVal->getType();
1766 if (!isTypeLegal(ArgTy, ArgVT))
1768 if (ArgVT == MVT::x86mmx)
1770 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1771 Flags.setOrigAlign(OriginalAlignment);
1773 Args.push_back(ArgReg);
1774 ArgVals.push_back(ArgVal);
1775 ArgVTs.push_back(ArgVT);
1776 ArgFlags.push_back(Flags);
1779 // Analyze operands of the call, assigning locations to each operand.
1780 SmallVector<CCValAssign, 16> ArgLocs;
1781 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs,
1782 I->getParent()->getContext());
1784 // Allocate shadow area for Win64
1785 if (Subtarget->isTargetWin64())
1786 CCInfo.AllocateStack(32, 8);
1788 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_X86);
1790 // Get a count of how many bytes are to be pushed on the stack.
1791 unsigned NumBytes = CCInfo.getNextStackOffset();
1793 // Issue CALLSEQ_START
1794 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1795 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
1798 // Process argument: walk the register/memloc assignments, inserting
1800 SmallVector<unsigned, 4> RegArgs;
1801 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1802 CCValAssign &VA = ArgLocs[i];
1803 unsigned Arg = Args[VA.getValNo()];
1804 EVT ArgVT = ArgVTs[VA.getValNo()];
1806 // Promote the value if needed.
1807 switch (VA.getLocInfo()) {
1808 case CCValAssign::Full: break;
1809 case CCValAssign::SExt: {
1810 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
1811 "Unexpected extend");
1812 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1814 assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
1815 ArgVT = VA.getLocVT();
1818 case CCValAssign::ZExt: {
1819 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
1820 "Unexpected extend");
1821 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1823 assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
1824 ArgVT = VA.getLocVT();
1827 case CCValAssign::AExt: {
1828 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
1829 "Unexpected extend");
1830 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1833 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1836 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1839 assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
1840 ArgVT = VA.getLocVT();
1843 case CCValAssign::BCvt: {
1844 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT(),
1845 ISD::BITCAST, Arg, /*TODO: Kill=*/false);
1846 assert(BC != 0 && "Failed to emit a bitcast!");
1848 ArgVT = VA.getLocVT();
1851 case CCValAssign::VExt:
1852 // VExt has not been implemented, so this should be impossible to reach
1853 // for now. However, fallback to Selection DAG isel once implemented.
1855 case CCValAssign::Indirect:
1856 // FIXME: Indirect doesn't need extending, but fast-isel doesn't fully
1861 if (VA.isRegLoc()) {
1862 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1863 VA.getLocReg()).addReg(Arg);
1864 RegArgs.push_back(VA.getLocReg());
1866 unsigned LocMemOffset = VA.getLocMemOffset();
1868 AM.Base.Reg = RegInfo->getStackRegister();
1869 AM.Disp = LocMemOffset;
1870 const Value *ArgVal = ArgVals[VA.getValNo()];
1871 ISD::ArgFlagsTy Flags = ArgFlags[VA.getValNo()];
1873 if (Flags.isByVal()) {
1874 X86AddressMode SrcAM;
1875 SrcAM.Base.Reg = Arg;
1876 bool Res = TryEmitSmallMemcpy(AM, SrcAM, Flags.getByValSize());
1877 assert(Res && "memcpy length already checked!"); (void)Res;
1878 } else if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) {
1879 // If this is a really simple value, emit this with the Value* version
1880 // of X86FastEmitStore. If it isn't simple, we don't want to do this,
1881 // as it can cause us to reevaluate the argument.
1882 if (!X86FastEmitStore(ArgVT, ArgVal, AM))
1885 if (!X86FastEmitStore(ArgVT, Arg, AM))
1891 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1893 if (Subtarget->isPICStyleGOT()) {
1894 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1895 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1896 X86::EBX).addReg(Base);
1899 if (Subtarget->is64Bit() && isVarArg && !Subtarget->isTargetWin64()) {
1900 // Count the number of XMM registers allocated.
1901 static const uint16_t XMMArgRegs[] = {
1902 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1903 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1905 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1906 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::MOV8ri),
1907 X86::AL).addImm(NumXMMRegs);
1911 MachineInstrBuilder MIB;
1913 // Register-indirect call.
1915 if (Subtarget->is64Bit())
1916 CallOpc = X86::CALL64r;
1918 CallOpc = X86::CALL32r;
1919 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1924 assert(GV && "Not a direct call");
1926 if (Subtarget->is64Bit())
1927 CallOpc = X86::CALL64pcrel32;
1929 CallOpc = X86::CALLpcrel32;
1931 // See if we need any target-specific flags on the GV operand.
1932 unsigned char OpFlags = 0;
1934 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1935 // external symbols most go through the PLT in PIC mode. If the symbol
1936 // has hidden or protected visibility, or if it is static or local, then
1937 // we don't need to use the PLT - we can directly call it.
1938 if (Subtarget->isTargetELF() &&
1939 TM.getRelocationModel() == Reloc::PIC_ &&
1940 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1941 OpFlags = X86II::MO_PLT;
1942 } else if (Subtarget->isPICStyleStubAny() &&
1943 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1944 (!Subtarget->getTargetTriple().isMacOSX() ||
1945 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
1946 // PC-relative references to external symbols should go through $stub,
1947 // unless we're building with the leopard linker or later, which
1948 // automatically synthesizes these stubs.
1949 OpFlags = X86II::MO_DARWIN_STUB;
1953 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc));
1955 MIB.addExternalSymbol(MemIntName, OpFlags);
1957 MIB.addGlobalAddress(GV, 0, OpFlags);
1960 // Add a register mask with the call-preserved registers.
1961 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1962 MIB.addRegMask(TRI.getCallPreservedMask(CS.getCallingConv()));
1964 // Add an implicit use GOT pointer in EBX.
1965 if (Subtarget->isPICStyleGOT())
1966 MIB.addReg(X86::EBX, RegState::Implicit);
1968 if (Subtarget->is64Bit() && isVarArg && !Subtarget->isTargetWin64())
1969 MIB.addReg(X86::AL, RegState::Implicit);
1971 // Add implicit physical register uses to the call.
1972 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1973 MIB.addReg(RegArgs[i], RegState::Implicit);
1975 // Issue CALLSEQ_END
1976 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1977 const unsigned NumBytesCallee = computeBytesPoppedByCallee(*Subtarget, CS);
1978 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
1979 .addImm(NumBytes).addImm(NumBytesCallee);
1981 // Build info for return calling conv lowering code.
1982 // FIXME: This is practically a copy-paste from TargetLowering::LowerCallTo.
1983 SmallVector<ISD::InputArg, 32> Ins;
1984 SmallVector<EVT, 4> RetTys;
1985 ComputeValueVTs(TLI, I->getType(), RetTys);
1986 for (unsigned i = 0, e = RetTys.size(); i != e; ++i) {
1988 MVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT);
1989 unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT);
1990 for (unsigned j = 0; j != NumRegs; ++j) {
1991 ISD::InputArg MyFlags;
1992 MyFlags.VT = RegisterVT;
1993 MyFlags.Used = !CS.getInstruction()->use_empty();
1994 if (CS.paramHasAttr(0, Attribute::SExt))
1995 MyFlags.Flags.setSExt();
1996 if (CS.paramHasAttr(0, Attribute::ZExt))
1997 MyFlags.Flags.setZExt();
1998 if (CS.paramHasAttr(0, Attribute::InReg))
1999 MyFlags.Flags.setInReg();
2000 Ins.push_back(MyFlags);
2004 // Now handle call return values.
2005 SmallVector<unsigned, 4> UsedRegs;
2006 SmallVector<CCValAssign, 16> RVLocs;
2007 CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs,
2008 I->getParent()->getContext());
2009 unsigned ResultReg = FuncInfo.CreateRegs(I->getType());
2010 CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86);
2011 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2012 EVT CopyVT = RVLocs[i].getValVT();
2013 unsigned CopyReg = ResultReg + i;
2015 // If this is a call to a function that returns an fp value on the x87 fp
2016 // stack, but where we prefer to use the value in xmm registers, copy it
2017 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
2018 if ((RVLocs[i].getLocReg() == X86::ST0 ||
2019 RVLocs[i].getLocReg() == X86::ST1)) {
2020 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
2022 CopyReg = createResultReg(&X86::RFP80RegClass);
2024 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL),
2027 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2028 CopyReg).addReg(RVLocs[i].getLocReg());
2029 UsedRegs.push_back(RVLocs[i].getLocReg());
2032 if (CopyVT != RVLocs[i].getValVT()) {
2033 // Round the F80 the right size, which also moves to the appropriate xmm
2034 // register. This is accomplished by storing the F80 value in memory and
2035 // then loading it back. Ewww...
2036 EVT ResVT = RVLocs[i].getValVT();
2037 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
2038 unsigned MemSize = ResVT.getSizeInBits()/8;
2039 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
2040 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2043 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
2044 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2045 TII.get(Opc), ResultReg + i), FI);
2050 UpdateValueMap(I, ResultReg, RVLocs.size());
2052 // Set all unused physreg defs as dead.
2053 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2060 X86FastISel::TargetSelectInstruction(const Instruction *I) {
2061 switch (I->getOpcode()) {
2063 case Instruction::Load:
2064 return X86SelectLoad(I);
2065 case Instruction::Store:
2066 return X86SelectStore(I);
2067 case Instruction::Ret:
2068 return X86SelectRet(I);
2069 case Instruction::ICmp:
2070 case Instruction::FCmp:
2071 return X86SelectCmp(I);
2072 case Instruction::ZExt:
2073 return X86SelectZExt(I);
2074 case Instruction::Br:
2075 return X86SelectBranch(I);
2076 case Instruction::Call:
2077 return X86SelectCall(I);
2078 case Instruction::LShr:
2079 case Instruction::AShr:
2080 case Instruction::Shl:
2081 return X86SelectShift(I);
2082 case Instruction::Select:
2083 return X86SelectSelect(I);
2084 case Instruction::Trunc:
2085 return X86SelectTrunc(I);
2086 case Instruction::FPExt:
2087 return X86SelectFPExt(I);
2088 case Instruction::FPTrunc:
2089 return X86SelectFPTrunc(I);
2090 case Instruction::IntToPtr: // Deliberate fall-through.
2091 case Instruction::PtrToInt: {
2092 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
2093 EVT DstVT = TLI.getValueType(I->getType());
2094 if (DstVT.bitsGT(SrcVT))
2095 return X86SelectZExt(I);
2096 if (DstVT.bitsLT(SrcVT))
2097 return X86SelectTrunc(I);
2098 unsigned Reg = getRegForValue(I->getOperand(0));
2099 if (Reg == 0) return false;
2100 UpdateValueMap(I, Reg);
2108 unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
2110 if (!isTypeLegal(C->getType(), VT))
2113 // Can't handle alternate code models yet.
2114 if (TM.getCodeModel() != CodeModel::Small)
2117 // Get opcode and regclass of the output for the given load instruction.
2119 const TargetRegisterClass *RC = NULL;
2120 switch (VT.SimpleTy) {
2124 RC = &X86::GR8RegClass;
2128 RC = &X86::GR16RegClass;
2132 RC = &X86::GR32RegClass;
2135 // Must be in x86-64 mode.
2137 RC = &X86::GR64RegClass;
2140 if (X86ScalarSSEf32) {
2141 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
2142 RC = &X86::FR32RegClass;
2144 Opc = X86::LD_Fp32m;
2145 RC = &X86::RFP32RegClass;
2149 if (X86ScalarSSEf64) {
2150 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
2151 RC = &X86::FR64RegClass;
2153 Opc = X86::LD_Fp64m;
2154 RC = &X86::RFP64RegClass;
2158 // No f80 support yet.
2162 // Materialize addresses with LEA instructions.
2163 if (isa<GlobalValue>(C)) {
2165 if (X86SelectAddress(C, AM)) {
2166 // If the expression is just a basereg, then we're done, otherwise we need
2168 if (AM.BaseType == X86AddressMode::RegBase &&
2169 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == 0)
2172 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
2173 unsigned ResultReg = createResultReg(RC);
2174 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2175 TII.get(Opc), ResultReg), AM);
2181 // MachineConstantPool wants an explicit alignment.
2182 unsigned Align = TD.getPrefTypeAlignment(C->getType());
2184 // Alignment of vector types. FIXME!
2185 Align = TD.getTypeAllocSize(C->getType());
2188 // x86-32 PIC requires a PIC base register for constant pools.
2189 unsigned PICBase = 0;
2190 unsigned char OpFlag = 0;
2191 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
2192 OpFlag = X86II::MO_PIC_BASE_OFFSET;
2193 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
2194 } else if (Subtarget->isPICStyleGOT()) {
2195 OpFlag = X86II::MO_GOTOFF;
2196 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
2197 } else if (Subtarget->isPICStyleRIPRel() &&
2198 TM.getCodeModel() == CodeModel::Small) {
2202 // Create the load from the constant pool.
2203 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
2204 unsigned ResultReg = createResultReg(RC);
2205 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2206 TII.get(Opc), ResultReg),
2207 MCPOffset, PICBase, OpFlag);
2212 unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
2213 // Fail on dynamic allocas. At this point, getRegForValue has already
2214 // checked its CSE maps, so if we're here trying to handle a dynamic
2215 // alloca, we're not going to succeed. X86SelectAddress has a
2216 // check for dynamic allocas, because it's called directly from
2217 // various places, but TargetMaterializeAlloca also needs a check
2218 // in order to avoid recursion between getRegForValue,
2219 // X86SelectAddrss, and TargetMaterializeAlloca.
2220 if (!FuncInfo.StaticAllocaMap.count(C))
2224 if (!X86SelectAddress(C, AM))
2226 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
2227 const TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
2228 unsigned ResultReg = createResultReg(RC);
2229 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2230 TII.get(Opc), ResultReg), AM);
2234 unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
2236 if (!isTypeLegal(CF->getType(), VT))
2239 // Get opcode and regclass for the given zero.
2241 const TargetRegisterClass *RC = NULL;
2242 switch (VT.SimpleTy) {
2245 if (X86ScalarSSEf32) {
2246 Opc = X86::FsFLD0SS;
2247 RC = &X86::FR32RegClass;
2249 Opc = X86::LD_Fp032;
2250 RC = &X86::RFP32RegClass;
2254 if (X86ScalarSSEf64) {
2255 Opc = X86::FsFLD0SD;
2256 RC = &X86::FR64RegClass;
2258 Opc = X86::LD_Fp064;
2259 RC = &X86::RFP64RegClass;
2263 // No f80 support yet.
2267 unsigned ResultReg = createResultReg(RC);
2268 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg);
2273 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
2274 /// vreg is being provided by the specified load instruction. If possible,
2275 /// try to fold the load as an operand to the instruction, returning true if
2277 bool X86FastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
2278 const LoadInst *LI) {
2280 if (!X86SelectAddress(LI->getOperand(0), AM))
2283 const X86InstrInfo &XII = (const X86InstrInfo&)TII;
2285 unsigned Size = TD.getTypeAllocSize(LI->getType());
2286 unsigned Alignment = LI->getAlignment();
2288 SmallVector<MachineOperand, 8> AddrOps;
2289 AM.getFullAddress(AddrOps);
2291 MachineInstr *Result =
2292 XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment);
2293 if (Result == 0) return false;
2295 FuncInfo.MBB->insert(FuncInfo.InsertPt, Result);
2296 MI->eraseFromParent();
2302 FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo,
2303 const TargetLibraryInfo *libInfo) {
2304 return new X86FastISel(funcInfo, libInfo);