1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Support/CallSite.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/GetElementPtrTypeIterator.h"
34 #include "llvm/Target/TargetOptions.h"
39 class X86FastISel : public FastISel {
40 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
41 /// make the right decision when generating code for different targets.
42 const X86Subtarget *Subtarget;
44 /// StackPtr - Register used as the stack pointer.
48 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
49 /// floating point ops.
50 /// When SSE is available, use it for f32 operations.
51 /// When SSE2 is available, use it for f64 operations.
56 explicit X86FastISel(MachineFunction &mf,
57 MachineModuleInfo *mmi,
59 DenseMap<const Value *, unsigned> &vm,
60 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
61 DenseMap<const AllocaInst *, int> &am
63 , SmallSet<Instruction*, 8> &cil
66 : FastISel(mf, mmi, dw, vm, bm, am
71 Subtarget = &TM.getSubtarget<X86Subtarget>();
72 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
77 virtual bool TargetSelectInstruction(Instruction *I);
79 #include "X86GenFastISel.inc"
82 bool X86FastEmitCompare(Value *LHS, Value *RHS, EVT VT);
84 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
86 bool X86FastEmitStore(EVT VT, Value *Val,
87 const X86AddressMode &AM);
88 bool X86FastEmitStore(EVT VT, unsigned Val,
89 const X86AddressMode &AM);
91 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
94 bool X86SelectAddress(Value *V, X86AddressMode &AM);
95 bool X86SelectCallAddress(Value *V, X86AddressMode &AM);
97 bool X86SelectLoad(Instruction *I);
99 bool X86SelectStore(Instruction *I);
101 bool X86SelectCmp(Instruction *I);
103 bool X86SelectZExt(Instruction *I);
105 bool X86SelectBranch(Instruction *I);
107 bool X86SelectShift(Instruction *I);
109 bool X86SelectSelect(Instruction *I);
111 bool X86SelectTrunc(Instruction *I);
113 bool X86SelectFPExt(Instruction *I);
114 bool X86SelectFPTrunc(Instruction *I);
116 bool X86SelectExtractValue(Instruction *I);
118 bool X86VisitIntrinsicCall(IntrinsicInst &I);
119 bool X86SelectCall(Instruction *I);
121 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false);
123 const X86InstrInfo *getInstrInfo() const {
124 return getTargetMachine()->getInstrInfo();
126 const X86TargetMachine *getTargetMachine() const {
127 return static_cast<const X86TargetMachine *>(&TM);
130 unsigned TargetMaterializeConstant(Constant *C);
132 unsigned TargetMaterializeAlloca(AllocaInst *C);
134 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
135 /// computed in an SSE register, not on the X87 floating point stack.
136 bool isScalarFPTypeInSSEReg(EVT VT) const {
137 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
138 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
141 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false);
144 } // end anonymous namespace.
146 bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
147 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
148 if (VT == MVT::Other || !VT.isSimple())
149 // Unhandled type. Halt "fast" selection and bail.
152 // For now, require SSE/SSE2 for performing floating-point operations,
153 // since x87 requires additional work.
154 if (VT == MVT::f64 && !X86ScalarSSEf64)
156 if (VT == MVT::f32 && !X86ScalarSSEf32)
158 // Similarly, no f80 support yet.
161 // We only handle legal types. For example, on x86-32 the instruction
162 // selector contains all of the 64-bit instructions from x86-64,
163 // under the assumption that i64 won't be used if the target doesn't
165 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
168 #include "X86GenCallingConv.inc"
170 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
172 CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC,
174 if (Subtarget->is64Bit()) {
175 if (Subtarget->isTargetWin64())
176 return CC_X86_Win64_C;
181 if (CC == CallingConv::X86_FastCall)
182 return CC_X86_32_FastCall;
183 else if (CC == CallingConv::Fast)
184 return CC_X86_32_FastCC;
189 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
190 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
191 /// Return true and the result register by reference if it is possible.
192 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
193 unsigned &ResultReg) {
194 // Get opcode and regclass of the output for the given load instruction.
196 const TargetRegisterClass *RC = NULL;
197 switch (VT.getSimpleVT().SimpleTy) {
198 default: return false;
202 RC = X86::GR8RegisterClass;
206 RC = X86::GR16RegisterClass;
210 RC = X86::GR32RegisterClass;
213 // Must be in x86-64 mode.
215 RC = X86::GR64RegisterClass;
218 if (Subtarget->hasSSE1()) {
220 RC = X86::FR32RegisterClass;
223 RC = X86::RFP32RegisterClass;
227 if (Subtarget->hasSSE2()) {
229 RC = X86::FR64RegisterClass;
232 RC = X86::RFP64RegisterClass;
236 // No f80 support yet.
240 ResultReg = createResultReg(RC);
241 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
245 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
246 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
247 /// and a displacement offset, or a GlobalAddress,
248 /// i.e. V. Return true if it is possible.
250 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val,
251 const X86AddressMode &AM) {
252 // Get opcode and regclass of the output for the given store instruction.
254 switch (VT.getSimpleVT().SimpleTy) {
255 case MVT::f80: // No f80 support yet.
256 default: return false;
258 // Mask out all but lowest bit.
259 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
261 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
264 // FALLTHROUGH, handling i1 as i8.
265 case MVT::i8: Opc = X86::MOV8mr; break;
266 case MVT::i16: Opc = X86::MOV16mr; break;
267 case MVT::i32: Opc = X86::MOV32mr; break;
268 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
270 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
273 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
277 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
281 bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val,
282 const X86AddressMode &AM) {
283 // Handle 'null' like i32/i64 0.
284 if (isa<ConstantPointerNull>(Val))
285 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
287 // If this is a store of a simple constant, fold the constant into the store.
288 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
291 switch (VT.getSimpleVT().SimpleTy) {
293 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
294 case MVT::i8: Opc = X86::MOV8mi; break;
295 case MVT::i16: Opc = X86::MOV16mi; break;
296 case MVT::i32: Opc = X86::MOV32mi; break;
298 // Must be a 32-bit sign extended value.
299 if ((int)CI->getSExtValue() == CI->getSExtValue())
300 Opc = X86::MOV64mi32;
305 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
306 .addImm(Signed ? CI->getSExtValue() :
312 unsigned ValReg = getRegForValue(Val);
316 return X86FastEmitStore(VT, ValReg, AM);
319 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
320 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
321 /// ISD::SIGN_EXTEND).
322 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
323 unsigned Src, EVT SrcVT,
324 unsigned &ResultReg) {
325 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
334 /// X86SelectAddress - Attempt to fill in an address from the given value.
336 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) {
338 unsigned Opcode = Instruction::UserOp1;
339 if (Instruction *I = dyn_cast<Instruction>(V)) {
340 Opcode = I->getOpcode();
342 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
343 Opcode = C->getOpcode();
349 case Instruction::BitCast:
350 // Look past bitcasts.
351 return X86SelectAddress(U->getOperand(0), AM);
353 case Instruction::IntToPtr:
354 // Look past no-op inttoptrs.
355 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
356 return X86SelectAddress(U->getOperand(0), AM);
359 case Instruction::PtrToInt:
360 // Look past no-op ptrtoints.
361 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
362 return X86SelectAddress(U->getOperand(0), AM);
365 case Instruction::Alloca: {
366 // Do static allocas.
367 const AllocaInst *A = cast<AllocaInst>(V);
368 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
369 if (SI != StaticAllocaMap.end()) {
370 AM.BaseType = X86AddressMode::FrameIndexBase;
371 AM.Base.FrameIndex = SI->second;
377 case Instruction::Add: {
378 // Adds of constants are common and easy enough.
379 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
380 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
381 // They have to fit in the 32-bit signed displacement field though.
383 AM.Disp = (uint32_t)Disp;
384 return X86SelectAddress(U->getOperand(0), AM);
390 case Instruction::GetElementPtr: {
391 // Pattern-match simple GEPs.
392 uint64_t Disp = (int32_t)AM.Disp;
393 unsigned IndexReg = AM.IndexReg;
394 unsigned Scale = AM.Scale;
395 gep_type_iterator GTI = gep_type_begin(U);
396 // Iterate through the indices, folding what we can. Constants can be
397 // folded, and one dynamic index can be handled, if the scale is supported.
398 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
399 i != e; ++i, ++GTI) {
401 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
402 const StructLayout *SL = TD.getStructLayout(STy);
403 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
404 Disp += SL->getElementOffset(Idx);
406 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
407 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
408 // Constant-offset addressing.
409 Disp += CI->getSExtValue() * S;
410 } else if (IndexReg == 0 &&
411 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
412 (S == 1 || S == 2 || S == 4 || S == 8)) {
413 // Scaled-index addressing.
415 IndexReg = getRegForGEPIndex(Op);
420 goto unsupported_gep;
423 // Check for displacement overflow.
426 // Ok, the GEP indices were covered by constant-offset and scaled-index
427 // addressing. Update the address state and move on to examining the base.
428 AM.IndexReg = IndexReg;
430 AM.Disp = (uint32_t)Disp;
431 return X86SelectAddress(U->getOperand(0), AM);
433 // Ok, the GEP indices weren't all covered.
438 // Handle constant address.
439 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
440 // Can't handle alternate code models yet.
441 if (TM.getCodeModel() != CodeModel::Small)
444 // RIP-relative addresses can't have additional register operands.
445 if (Subtarget->isPICStyleRIPRel() &&
446 (AM.Base.Reg != 0 || AM.IndexReg != 0))
449 // Can't handle TLS yet.
450 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
451 if (GVar->isThreadLocal())
454 // Okay, we've committed to selecting this global. Set up the basic address.
457 // Allow the subtarget to classify the global.
458 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
460 // If this reference is relative to the pic base, set it now.
461 if (isGlobalRelativeToPICBase(GVFlags)) {
462 // FIXME: How do we know Base.Reg is free??
463 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
466 // Unless the ABI requires an extra load, return a direct reference to
468 if (!isGlobalStubReference(GVFlags)) {
469 if (Subtarget->isPICStyleRIPRel()) {
470 // Use rip-relative addressing if we can. Above we verified that the
471 // base and index registers are unused.
472 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
473 AM.Base.Reg = X86::RIP;
475 AM.GVOpFlags = GVFlags;
479 // Ok, we need to do a load from a stub. If we've already loaded from this
480 // stub, reuse the loaded pointer, otherwise emit the load now.
481 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
483 if (I != LocalValueMap.end() && I->second != 0) {
486 // Issue load from stub.
488 const TargetRegisterClass *RC = NULL;
489 X86AddressMode StubAM;
490 StubAM.Base.Reg = AM.Base.Reg;
492 StubAM.GVOpFlags = GVFlags;
494 if (TLI.getPointerTy() == MVT::i64) {
496 RC = X86::GR64RegisterClass;
498 if (Subtarget->isPICStyleRIPRel())
499 StubAM.Base.Reg = X86::RIP;
502 RC = X86::GR32RegisterClass;
505 LoadReg = createResultReg(RC);
506 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM);
508 // Prevent loading GV stub multiple times in same MBB.
509 LocalValueMap[V] = LoadReg;
512 // Now construct the final address. Note that the Disp, Scale,
513 // and Index values may already be set here.
514 AM.Base.Reg = LoadReg;
519 // If all else fails, try to materialize the value in a register.
520 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
521 if (AM.Base.Reg == 0) {
522 AM.Base.Reg = getRegForValue(V);
523 return AM.Base.Reg != 0;
525 if (AM.IndexReg == 0) {
526 assert(AM.Scale == 1 && "Scale with no index!");
527 AM.IndexReg = getRegForValue(V);
528 return AM.IndexReg != 0;
535 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
537 bool X86FastISel::X86SelectCallAddress(Value *V, X86AddressMode &AM) {
539 unsigned Opcode = Instruction::UserOp1;
540 if (Instruction *I = dyn_cast<Instruction>(V)) {
541 Opcode = I->getOpcode();
543 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
544 Opcode = C->getOpcode();
550 case Instruction::BitCast:
551 // Look past bitcasts.
552 return X86SelectCallAddress(U->getOperand(0), AM);
554 case Instruction::IntToPtr:
555 // Look past no-op inttoptrs.
556 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
557 return X86SelectCallAddress(U->getOperand(0), AM);
560 case Instruction::PtrToInt:
561 // Look past no-op ptrtoints.
562 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
563 return X86SelectCallAddress(U->getOperand(0), AM);
567 // Handle constant address.
568 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
569 // Can't handle alternate code models yet.
570 if (TM.getCodeModel() != CodeModel::Small)
573 // RIP-relative addresses can't have additional register operands.
574 if (Subtarget->isPICStyleRIPRel() &&
575 (AM.Base.Reg != 0 || AM.IndexReg != 0))
578 // Can't handle TLS or DLLImport.
579 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
580 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage())
583 // Okay, we've committed to selecting this global. Set up the basic address.
586 // No ABI requires an extra load for anything other than DLLImport, which
587 // we rejected above. Return a direct reference to the global.
588 if (Subtarget->isPICStyleRIPRel()) {
589 // Use rip-relative addressing if we can. Above we verified that the
590 // base and index registers are unused.
591 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
592 AM.Base.Reg = X86::RIP;
593 } else if (Subtarget->isPICStyleStubPIC()) {
594 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
595 } else if (Subtarget->isPICStyleGOT()) {
596 AM.GVOpFlags = X86II::MO_GOTOFF;
602 // If all else fails, try to materialize the value in a register.
603 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
604 if (AM.Base.Reg == 0) {
605 AM.Base.Reg = getRegForValue(V);
606 return AM.Base.Reg != 0;
608 if (AM.IndexReg == 0) {
609 assert(AM.Scale == 1 && "Scale with no index!");
610 AM.IndexReg = getRegForValue(V);
611 return AM.IndexReg != 0;
619 /// X86SelectStore - Select and emit code to implement store instructions.
620 bool X86FastISel::X86SelectStore(Instruction* I) {
622 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
626 if (!X86SelectAddress(I->getOperand(1), AM))
629 return X86FastEmitStore(VT, I->getOperand(0), AM);
632 /// X86SelectLoad - Select and emit code to implement load instructions.
634 bool X86FastISel::X86SelectLoad(Instruction *I) {
636 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
640 if (!X86SelectAddress(I->getOperand(0), AM))
643 unsigned ResultReg = 0;
644 if (X86FastEmitLoad(VT, AM, ResultReg)) {
645 UpdateValueMap(I, ResultReg);
651 static unsigned X86ChooseCmpOpcode(EVT VT) {
652 switch (VT.getSimpleVT().SimpleTy) {
654 case MVT::i8: return X86::CMP8rr;
655 case MVT::i16: return X86::CMP16rr;
656 case MVT::i32: return X86::CMP32rr;
657 case MVT::i64: return X86::CMP64rr;
658 case MVT::f32: return X86::UCOMISSrr;
659 case MVT::f64: return X86::UCOMISDrr;
663 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
664 /// of the comparison, return an opcode that works for the compare (e.g.
665 /// CMP32ri) otherwise return 0.
666 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, ConstantInt *RHSC) {
667 switch (VT.getSimpleVT().SimpleTy) {
668 // Otherwise, we can't fold the immediate into this comparison.
670 case MVT::i8: return X86::CMP8ri;
671 case MVT::i16: return X86::CMP16ri;
672 case MVT::i32: return X86::CMP32ri;
674 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
676 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
677 return X86::CMP64ri32;
682 bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, EVT VT) {
683 unsigned Op0Reg = getRegForValue(Op0);
684 if (Op0Reg == 0) return false;
686 // Handle 'null' like i32/i64 0.
687 if (isa<ConstantPointerNull>(Op1))
688 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
690 // We have two options: compare with register or immediate. If the RHS of
691 // the compare is an immediate that we can fold into this compare, use
692 // CMPri, otherwise use CMPrr.
693 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
694 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
695 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
696 .addImm(Op1C->getSExtValue());
701 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
702 if (CompareOpc == 0) return false;
704 unsigned Op1Reg = getRegForValue(Op1);
705 if (Op1Reg == 0) return false;
706 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
711 bool X86FastISel::X86SelectCmp(Instruction *I) {
712 CmpInst *CI = cast<CmpInst>(I);
715 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
718 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
720 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
721 switch (CI->getPredicate()) {
722 case CmpInst::FCMP_OEQ: {
723 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
726 unsigned EReg = createResultReg(&X86::GR8RegClass);
727 unsigned NPReg = createResultReg(&X86::GR8RegClass);
728 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
729 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
731 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
732 UpdateValueMap(I, ResultReg);
735 case CmpInst::FCMP_UNE: {
736 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
739 unsigned NEReg = createResultReg(&X86::GR8RegClass);
740 unsigned PReg = createResultReg(&X86::GR8RegClass);
741 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
742 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
743 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
744 UpdateValueMap(I, ResultReg);
747 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
748 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
749 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
750 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
751 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
752 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
753 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
754 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
755 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
756 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
757 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
758 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
760 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
761 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
762 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
763 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
764 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
765 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
766 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
767 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
768 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
769 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
774 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
778 // Emit a compare of Op0/Op1.
779 if (!X86FastEmitCompare(Op0, Op1, VT))
782 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
783 UpdateValueMap(I, ResultReg);
787 bool X86FastISel::X86SelectZExt(Instruction *I) {
788 // Handle zero-extension from i1 to i8, which is common.
789 if (I->getType()->isIntegerTy(8) &&
790 I->getOperand(0)->getType()->isIntegerTy(1)) {
791 unsigned ResultReg = getRegForValue(I->getOperand(0));
792 if (ResultReg == 0) return false;
793 // Set the high bits to zero.
794 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
795 if (ResultReg == 0) return false;
796 UpdateValueMap(I, ResultReg);
804 bool X86FastISel::X86SelectBranch(Instruction *I) {
805 // Unconditional branches are selected by tablegen-generated code.
806 // Handle a conditional branch.
807 BranchInst *BI = cast<BranchInst>(I);
808 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
809 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
811 // Fold the common case of a conditional branch with a comparison.
812 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
813 if (CI->hasOneUse()) {
814 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
816 // Try to take advantage of fallthrough opportunities.
817 CmpInst::Predicate Predicate = CI->getPredicate();
818 if (MBB->isLayoutSuccessor(TrueMBB)) {
819 std::swap(TrueMBB, FalseMBB);
820 Predicate = CmpInst::getInversePredicate(Predicate);
823 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
824 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
827 case CmpInst::FCMP_OEQ:
828 std::swap(TrueMBB, FalseMBB);
829 Predicate = CmpInst::FCMP_UNE;
831 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
832 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
833 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
834 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
835 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
836 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
837 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
838 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
839 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
840 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
841 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
842 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
843 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
845 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
846 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
847 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
848 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
849 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
850 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
851 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
852 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
853 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
854 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
859 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
863 // Emit a compare of the LHS and RHS, setting the flags.
864 if (!X86FastEmitCompare(Op0, Op1, VT))
867 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
869 if (Predicate == CmpInst::FCMP_UNE) {
870 // X86 requires a second branch to handle UNE (and OEQ,
871 // which is mapped to UNE above).
872 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
875 FastEmitBranch(FalseMBB);
876 MBB->addSuccessor(TrueMBB);
879 } else if (ExtractValueInst *EI =
880 dyn_cast<ExtractValueInst>(BI->getCondition())) {
881 // Check to see if the branch instruction is from an "arithmetic with
882 // overflow" intrinsic. The main way these intrinsics are used is:
884 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
885 // %sum = extractvalue { i32, i1 } %t, 0
886 // %obit = extractvalue { i32, i1 } %t, 1
887 // br i1 %obit, label %overflow, label %normal
889 // The %sum and %obit are converted in an ADD and a SETO/SETB before
890 // reaching the branch. Therefore, we search backwards through the MBB
891 // looking for the SETO/SETB instruction. If an instruction modifies the
892 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
893 // convert the branch into a JO/JB instruction.
894 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
895 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
896 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
897 const MachineInstr *SetMI = 0;
898 unsigned Reg = lookUpRegForValue(EI);
900 for (MachineBasicBlock::const_reverse_iterator
901 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
902 const MachineInstr &MI = *RI;
904 if (MI.modifiesRegister(Reg)) {
905 unsigned Src, Dst, SrcSR, DstSR;
907 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
916 const TargetInstrDesc &TID = MI.getDesc();
917 if (TID.hasUnmodeledSideEffects() ||
918 TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
923 unsigned OpCode = SetMI->getOpcode();
925 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
926 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
927 X86::JO_4 : X86::JB_4))
929 FastEmitBranch(FalseMBB);
930 MBB->addSuccessor(TrueMBB);
938 // Otherwise do a clumsy setcc and re-test it.
939 unsigned OpReg = getRegForValue(BI->getCondition());
940 if (OpReg == 0) return false;
942 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
943 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
944 FastEmitBranch(FalseMBB);
945 MBB->addSuccessor(TrueMBB);
949 bool X86FastISel::X86SelectShift(Instruction *I) {
950 unsigned CReg = 0, OpReg = 0, OpImm = 0;
951 const TargetRegisterClass *RC = NULL;
952 if (I->getType()->isIntegerTy(8)) {
954 RC = &X86::GR8RegClass;
955 switch (I->getOpcode()) {
956 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
957 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
958 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
959 default: return false;
961 } else if (I->getType()->isIntegerTy(16)) {
963 RC = &X86::GR16RegClass;
964 switch (I->getOpcode()) {
965 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
966 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
967 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
968 default: return false;
970 } else if (I->getType()->isIntegerTy(32)) {
972 RC = &X86::GR32RegClass;
973 switch (I->getOpcode()) {
974 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
975 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
976 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
977 default: return false;
979 } else if (I->getType()->isIntegerTy(64)) {
981 RC = &X86::GR64RegClass;
982 switch (I->getOpcode()) {
983 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
984 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
985 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
986 default: return false;
992 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
993 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
996 unsigned Op0Reg = getRegForValue(I->getOperand(0));
997 if (Op0Reg == 0) return false;
999 // Fold immediate in shl(x,3).
1000 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
1001 unsigned ResultReg = createResultReg(RC);
1002 BuildMI(MBB, DL, TII.get(OpImm),
1003 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
1004 UpdateValueMap(I, ResultReg);
1008 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1009 if (Op1Reg == 0) return false;
1010 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
1012 // The shift instruction uses X86::CL. If we defined a super-register
1013 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
1014 // we're doing here.
1015 if (CReg != X86::CL)
1016 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL)
1017 .addReg(CReg).addImm(X86::SUBREG_8BIT);
1019 unsigned ResultReg = createResultReg(RC);
1020 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
1021 UpdateValueMap(I, ResultReg);
1025 bool X86FastISel::X86SelectSelect(Instruction *I) {
1026 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1027 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1031 const TargetRegisterClass *RC = NULL;
1032 if (VT.getSimpleVT() == MVT::i16) {
1033 Opc = X86::CMOVE16rr;
1034 RC = &X86::GR16RegClass;
1035 } else if (VT.getSimpleVT() == MVT::i32) {
1036 Opc = X86::CMOVE32rr;
1037 RC = &X86::GR32RegClass;
1038 } else if (VT.getSimpleVT() == MVT::i64) {
1039 Opc = X86::CMOVE64rr;
1040 RC = &X86::GR64RegClass;
1045 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1046 if (Op0Reg == 0) return false;
1047 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1048 if (Op1Reg == 0) return false;
1049 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1050 if (Op2Reg == 0) return false;
1052 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
1053 unsigned ResultReg = createResultReg(RC);
1054 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
1055 UpdateValueMap(I, ResultReg);
1059 bool X86FastISel::X86SelectFPExt(Instruction *I) {
1060 // fpext from float to double.
1061 if (Subtarget->hasSSE2() &&
1062 I->getType()->isDoubleTy()) {
1063 Value *V = I->getOperand(0);
1064 if (V->getType()->isFloatTy()) {
1065 unsigned OpReg = getRegForValue(V);
1066 if (OpReg == 0) return false;
1067 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1068 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
1069 UpdateValueMap(I, ResultReg);
1077 bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
1078 if (Subtarget->hasSSE2()) {
1079 if (I->getType()->isFloatTy()) {
1080 Value *V = I->getOperand(0);
1081 if (V->getType()->isDoubleTy()) {
1082 unsigned OpReg = getRegForValue(V);
1083 if (OpReg == 0) return false;
1084 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1085 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
1086 UpdateValueMap(I, ResultReg);
1095 bool X86FastISel::X86SelectTrunc(Instruction *I) {
1096 if (Subtarget->is64Bit())
1097 // All other cases should be handled by the tblgen generated code.
1099 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1100 EVT DstVT = TLI.getValueType(I->getType());
1102 // This code only handles truncation to byte right now.
1103 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1104 // All other cases should be handled by the tblgen generated code.
1106 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
1107 // All other cases should be handled by the tblgen generated code.
1110 unsigned InputReg = getRegForValue(I->getOperand(0));
1112 // Unhandled operand. Halt "fast" selection and bail.
1115 // First issue a copy to GR16_ABCD or GR32_ABCD.
1116 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
1117 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1118 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1119 unsigned CopyReg = createResultReg(CopyRC);
1120 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1122 // Then issue an extract_subreg.
1123 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1124 CopyReg, X86::SUBREG_8BIT);
1128 UpdateValueMap(I, ResultReg);
1132 bool X86FastISel::X86SelectExtractValue(Instruction *I) {
1133 ExtractValueInst *EI = cast<ExtractValueInst>(I);
1134 Value *Agg = EI->getAggregateOperand();
1136 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1137 switch (CI->getIntrinsicID()) {
1139 case Intrinsic::sadd_with_overflow:
1140 case Intrinsic::uadd_with_overflow:
1141 // Cheat a little. We know that the registers for "add" and "seto" are
1142 // allocated sequentially. However, we only keep track of the register
1143 // for "add" in the value map. Use extractvalue's index to get the
1144 // correct register for "seto".
1145 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1153 bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) {
1154 // FIXME: Handle more intrinsics.
1155 switch (I.getIntrinsicID()) {
1156 default: return false;
1157 case Intrinsic::dbg_declare: {
1158 DbgDeclareInst *DI = cast<DbgDeclareInst>(&I);
1160 assert(DI->getAddress() && "Null address should be checked earlier!");
1161 if (!X86SelectAddress(DI->getAddress(), AM))
1163 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1164 // FIXME may need to add RegState::Debug to any registers produced,
1165 // although ESP/EBP should be the only ones at the moment.
1166 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0).
1167 addMetadata(DI->getVariable());
1170 case Intrinsic::dbg_value: {
1171 // FIXME this should eventually be moved to FastISel, when all targets
1172 // are able to cope with DBG_VALUE. There is nothing target dependent here.
1173 DbgValueInst *DI = cast<DbgValueInst>(&I);
1174 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1175 Value *V = DI->getValue();
1177 // Currently the optimizer can produce this; insert an undef to
1178 // help debugging. Probably the optimizer should not do this.
1179 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
1180 addMetadata(DI->getVariable());
1181 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
1182 BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()).
1183 addMetadata(DI->getVariable());
1184 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
1185 BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()).
1186 addMetadata(DI->getVariable());
1187 } else if (unsigned Reg = lookUpRegForValue(V)) {
1188 BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()).
1189 addMetadata(DI->getVariable());
1191 // We can't yet handle anything else here because it would require
1192 // generating code, thus altering codegen because of debug info.
1193 // Insert an undef so we can see what we dropped.
1194 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
1195 addMetadata(DI->getVariable());
1199 case Intrinsic::trap: {
1200 BuildMI(MBB, DL, TII.get(X86::TRAP));
1203 case Intrinsic::sadd_with_overflow:
1204 case Intrinsic::uadd_with_overflow: {
1205 // Replace "add with overflow" intrinsics with an "add" instruction followed
1206 // by a seto/setc instruction. Later on, when the "extractvalue"
1207 // instructions are encountered, we use the fact that two registers were
1208 // created sequentially to get the correct registers for the "sum" and the
1210 const Function *Callee = I.getCalledFunction();
1212 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1215 if (!isTypeLegal(RetTy, VT))
1218 Value *Op1 = I.getOperand(1);
1219 Value *Op2 = I.getOperand(2);
1220 unsigned Reg1 = getRegForValue(Op1);
1221 unsigned Reg2 = getRegForValue(Op2);
1223 if (Reg1 == 0 || Reg2 == 0)
1224 // FIXME: Handle values *not* in registers.
1230 else if (VT == MVT::i64)
1235 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1236 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1237 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1239 // If the add with overflow is an intra-block value then we just want to
1240 // create temporaries for it like normal. If it is a cross-block value then
1241 // UpdateValueMap will return the cross-block register used. Since we
1242 // *really* want the value to be live in the register pair known by
1243 // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1244 // the cross block case. In the non-cross-block case, we should just make
1245 // another register for the value.
1246 if (DestReg1 != ResultReg)
1247 ResultReg = DestReg1+1;
1249 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1251 unsigned Opc = X86::SETBr;
1252 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1254 BuildMI(MBB, DL, TII.get(Opc), ResultReg);
1260 bool X86FastISel::X86SelectCall(Instruction *I) {
1261 CallInst *CI = cast<CallInst>(I);
1262 Value *Callee = I->getOperand(0);
1264 // Can't handle inline asm yet.
1265 if (isa<InlineAsm>(Callee))
1268 // Handle intrinsic calls.
1269 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1270 return X86VisitIntrinsicCall(*II);
1272 // Handle only C and fastcc calling conventions for now.
1274 CallingConv::ID CC = CS.getCallingConv();
1275 if (CC != CallingConv::C &&
1276 CC != CallingConv::Fast &&
1277 CC != CallingConv::X86_FastCall)
1280 // fastcc with -tailcallopt is intended to provide a guaranteed
1281 // tail call optimization. Fastisel doesn't know how to do that.
1282 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
1285 // Let SDISel handle vararg functions.
1286 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1287 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1288 if (FTy->isVarArg())
1291 // Handle *simple* calls for now.
1292 const Type *RetTy = CS.getType();
1294 if (RetTy->isVoidTy())
1295 RetVT = MVT::isVoid;
1296 else if (!isTypeLegal(RetTy, RetVT, true))
1299 // Materialize callee address in a register. FIXME: GV address can be
1300 // handled with a CALLpcrel32 instead.
1301 X86AddressMode CalleeAM;
1302 if (!X86SelectCallAddress(Callee, CalleeAM))
1304 unsigned CalleeOp = 0;
1305 GlobalValue *GV = 0;
1306 if (CalleeAM.GV != 0) {
1308 } else if (CalleeAM.Base.Reg != 0) {
1309 CalleeOp = CalleeAM.Base.Reg;
1313 // Allow calls which produce i1 results.
1314 bool AndToI1 = false;
1315 if (RetVT == MVT::i1) {
1320 // Deal with call operands first.
1321 SmallVector<Value*, 8> ArgVals;
1322 SmallVector<unsigned, 8> Args;
1323 SmallVector<EVT, 8> ArgVTs;
1324 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1325 Args.reserve(CS.arg_size());
1326 ArgVals.reserve(CS.arg_size());
1327 ArgVTs.reserve(CS.arg_size());
1328 ArgFlags.reserve(CS.arg_size());
1329 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1331 unsigned Arg = getRegForValue(*i);
1334 ISD::ArgFlagsTy Flags;
1335 unsigned AttrInd = i - CS.arg_begin() + 1;
1336 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1338 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1341 // FIXME: Only handle *easy* calls for now.
1342 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1343 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1344 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1345 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1348 const Type *ArgTy = (*i)->getType();
1350 if (!isTypeLegal(ArgTy, ArgVT))
1352 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1353 Flags.setOrigAlign(OriginalAlignment);
1355 Args.push_back(Arg);
1356 ArgVals.push_back(*i);
1357 ArgVTs.push_back(ArgVT);
1358 ArgFlags.push_back(Flags);
1361 // Analyze operands of the call, assigning locations to each operand.
1362 SmallVector<CCValAssign, 16> ArgLocs;
1363 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext());
1364 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1366 // Get a count of how many bytes are to be pushed on the stack.
1367 unsigned NumBytes = CCInfo.getNextStackOffset();
1369 // Issue CALLSEQ_START
1370 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1371 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1373 // Process argument: walk the register/memloc assignments, inserting
1375 SmallVector<unsigned, 4> RegArgs;
1376 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1377 CCValAssign &VA = ArgLocs[i];
1378 unsigned Arg = Args[VA.getValNo()];
1379 EVT ArgVT = ArgVTs[VA.getValNo()];
1381 // Promote the value if needed.
1382 switch (VA.getLocInfo()) {
1383 default: llvm_unreachable("Unknown loc info!");
1384 case CCValAssign::Full: break;
1385 case CCValAssign::SExt: {
1386 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1388 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1390 ArgVT = VA.getLocVT();
1393 case CCValAssign::ZExt: {
1394 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1396 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1398 ArgVT = VA.getLocVT();
1401 case CCValAssign::AExt: {
1402 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1405 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1408 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1411 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1412 ArgVT = VA.getLocVT();
1415 case CCValAssign::BCvt: {
1416 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(),
1417 ISD::BIT_CONVERT, Arg);
1418 assert(BC != 0 && "Failed to emit a bitcast!");
1420 ArgVT = VA.getLocVT();
1425 if (VA.isRegLoc()) {
1426 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1427 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1429 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1431 RegArgs.push_back(VA.getLocReg());
1433 unsigned LocMemOffset = VA.getLocMemOffset();
1435 AM.Base.Reg = StackPtr;
1436 AM.Disp = LocMemOffset;
1437 Value *ArgVal = ArgVals[VA.getValNo()];
1439 // If this is a really simple value, emit this with the Value* version of
1440 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1441 // can cause us to reevaluate the argument.
1442 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1443 X86FastEmitStore(ArgVT, ArgVal, AM);
1445 X86FastEmitStore(ArgVT, Arg, AM);
1449 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1451 if (Subtarget->isPICStyleGOT()) {
1452 TargetRegisterClass *RC = X86::GR32RegisterClass;
1453 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1454 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1455 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1460 MachineInstrBuilder MIB;
1462 // Register-indirect call.
1463 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r;
1464 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp);
1468 assert(GV && "Not a direct call");
1470 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
1472 // See if we need any target-specific flags on the GV operand.
1473 unsigned char OpFlags = 0;
1475 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1476 // external symbols most go through the PLT in PIC mode. If the symbol
1477 // has hidden or protected visibility, or if it is static or local, then
1478 // we don't need to use the PLT - we can directly call it.
1479 if (Subtarget->isTargetELF() &&
1480 TM.getRelocationModel() == Reloc::PIC_ &&
1481 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1482 OpFlags = X86II::MO_PLT;
1483 } else if (Subtarget->isPICStyleStubAny() &&
1484 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1485 Subtarget->getDarwinVers() < 9) {
1486 // PC-relative references to external symbols should go through $stub,
1487 // unless we're building with the leopard linker or later, which
1488 // automatically synthesizes these stubs.
1489 OpFlags = X86II::MO_DARWIN_STUB;
1493 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags);
1496 // Add an implicit use GOT pointer in EBX.
1497 if (Subtarget->isPICStyleGOT())
1498 MIB.addReg(X86::EBX);
1500 // Add implicit physical register uses to the call.
1501 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1502 MIB.addReg(RegArgs[i]);
1504 // Issue CALLSEQ_END
1505 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1506 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1508 // Now handle call return value (if any).
1509 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1510 SmallVector<CCValAssign, 16> RVLocs;
1511 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
1512 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1514 // Copy all of the result registers out of their specified physreg.
1515 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1516 EVT CopyVT = RVLocs[0].getValVT();
1517 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1518 TargetRegisterClass *SrcRC = DstRC;
1520 // If this is a call to a function that returns an fp value on the x87 fp
1521 // stack, but where we prefer to use the value in xmm registers, copy it
1522 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1523 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1524 RVLocs[0].getLocReg() == X86::ST1) &&
1525 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1527 SrcRC = X86::RSTRegisterClass;
1528 DstRC = X86::RFP80RegisterClass;
1531 unsigned ResultReg = createResultReg(DstRC);
1532 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1533 RVLocs[0].getLocReg(), DstRC, SrcRC);
1534 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1536 if (CopyVT != RVLocs[0].getValVT()) {
1537 // Round the F80 the right size, which also moves to the appropriate xmm
1538 // register. This is accomplished by storing the F80 value in memory and
1539 // then loading it back. Ewww...
1540 EVT ResVT = RVLocs[0].getValVT();
1541 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1542 unsigned MemSize = ResVT.getSizeInBits()/8;
1543 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
1544 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1545 DstRC = ResVT == MVT::f32
1546 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1547 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1548 ResultReg = createResultReg(DstRC);
1549 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1553 // Mask out all but lowest bit for some call which produces an i1.
1554 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1556 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1557 ResultReg = AndResult;
1560 UpdateValueMap(I, ResultReg);
1568 X86FastISel::TargetSelectInstruction(Instruction *I) {
1569 switch (I->getOpcode()) {
1571 case Instruction::Load:
1572 return X86SelectLoad(I);
1573 case Instruction::Store:
1574 return X86SelectStore(I);
1575 case Instruction::ICmp:
1576 case Instruction::FCmp:
1577 return X86SelectCmp(I);
1578 case Instruction::ZExt:
1579 return X86SelectZExt(I);
1580 case Instruction::Br:
1581 return X86SelectBranch(I);
1582 case Instruction::Call:
1583 return X86SelectCall(I);
1584 case Instruction::LShr:
1585 case Instruction::AShr:
1586 case Instruction::Shl:
1587 return X86SelectShift(I);
1588 case Instruction::Select:
1589 return X86SelectSelect(I);
1590 case Instruction::Trunc:
1591 return X86SelectTrunc(I);
1592 case Instruction::FPExt:
1593 return X86SelectFPExt(I);
1594 case Instruction::FPTrunc:
1595 return X86SelectFPTrunc(I);
1596 case Instruction::ExtractValue:
1597 return X86SelectExtractValue(I);
1598 case Instruction::IntToPtr: // Deliberate fall-through.
1599 case Instruction::PtrToInt: {
1600 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1601 EVT DstVT = TLI.getValueType(I->getType());
1602 if (DstVT.bitsGT(SrcVT))
1603 return X86SelectZExt(I);
1604 if (DstVT.bitsLT(SrcVT))
1605 return X86SelectTrunc(I);
1606 unsigned Reg = getRegForValue(I->getOperand(0));
1607 if (Reg == 0) return false;
1608 UpdateValueMap(I, Reg);
1616 unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
1618 if (!isTypeLegal(C->getType(), VT))
1621 // Get opcode and regclass of the output for the given load instruction.
1623 const TargetRegisterClass *RC = NULL;
1624 switch (VT.getSimpleVT().SimpleTy) {
1625 default: return false;
1628 RC = X86::GR8RegisterClass;
1632 RC = X86::GR16RegisterClass;
1636 RC = X86::GR32RegisterClass;
1639 // Must be in x86-64 mode.
1641 RC = X86::GR64RegisterClass;
1644 if (Subtarget->hasSSE1()) {
1646 RC = X86::FR32RegisterClass;
1648 Opc = X86::LD_Fp32m;
1649 RC = X86::RFP32RegisterClass;
1653 if (Subtarget->hasSSE2()) {
1655 RC = X86::FR64RegisterClass;
1657 Opc = X86::LD_Fp64m;
1658 RC = X86::RFP64RegisterClass;
1662 // No f80 support yet.
1666 // Materialize addresses with LEA instructions.
1667 if (isa<GlobalValue>(C)) {
1669 if (X86SelectAddress(C, AM)) {
1670 if (TLI.getPointerTy() == MVT::i32)
1674 unsigned ResultReg = createResultReg(RC);
1675 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1681 // MachineConstantPool wants an explicit alignment.
1682 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1684 // Alignment of vector types. FIXME!
1685 Align = TD.getTypeAllocSize(C->getType());
1688 // x86-32 PIC requires a PIC base register for constant pools.
1689 unsigned PICBase = 0;
1690 unsigned char OpFlag = 0;
1691 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
1692 OpFlag = X86II::MO_PIC_BASE_OFFSET;
1693 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1694 } else if (Subtarget->isPICStyleGOT()) {
1695 OpFlag = X86II::MO_GOTOFF;
1696 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1697 } else if (Subtarget->isPICStyleRIPRel() &&
1698 TM.getCodeModel() == CodeModel::Small) {
1702 // Create the load from the constant pool.
1703 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1704 unsigned ResultReg = createResultReg(RC);
1705 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg),
1706 MCPOffset, PICBase, OpFlag);
1711 unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
1712 // Fail on dynamic allocas. At this point, getRegForValue has already
1713 // checked its CSE maps, so if we're here trying to handle a dynamic
1714 // alloca, we're not going to succeed. X86SelectAddress has a
1715 // check for dynamic allocas, because it's called directly from
1716 // various places, but TargetMaterializeAlloca also needs a check
1717 // in order to avoid recursion between getRegForValue,
1718 // X86SelectAddrss, and TargetMaterializeAlloca.
1719 if (!StaticAllocaMap.count(C))
1723 if (!X86SelectAddress(C, AM))
1725 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1726 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1727 unsigned ResultReg = createResultReg(RC);
1728 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1733 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1734 MachineModuleInfo *mmi,
1736 DenseMap<const Value *, unsigned> &vm,
1737 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1738 DenseMap<const AllocaInst *, int> &am
1740 , SmallSet<Instruction*, 8> &cil
1743 return new X86FastISel(mf, mmi, dw, vm, bm, am