1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86InstrInfo.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86RegisterInfo.h"
22 #include "X86Subtarget.h"
23 #include "X86TargetMachine.h"
24 #include "llvm/Analysis/BranchProbabilityInfo.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/GetElementPtrTypeIterator.h"
35 #include "llvm/IR/GlobalAlias.h"
36 #include "llvm/IR/GlobalVariable.h"
37 #include "llvm/IR/Instructions.h"
38 #include "llvm/IR/IntrinsicInst.h"
39 #include "llvm/IR/Operator.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Target/TargetOptions.h"
46 class X86FastISel final : public FastISel {
47 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
48 /// make the right decision when generating code for different targets.
49 const X86Subtarget *Subtarget;
51 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
52 /// floating point ops.
53 /// When SSE is available, use it for f32 operations.
54 /// When SSE2 is available, use it for f64 operations.
59 explicit X86FastISel(FunctionLoweringInfo &funcInfo,
60 const TargetLibraryInfo *libInfo)
61 : FastISel(funcInfo, libInfo) {
62 Subtarget = &TM.getSubtarget<X86Subtarget>();
63 X86ScalarSSEf64 = Subtarget->hasSSE2();
64 X86ScalarSSEf32 = Subtarget->hasSSE1();
67 bool fastSelectInstruction(const Instruction *I) override;
69 /// \brief The specified machine instr operand is a vreg, and that
70 /// vreg is being provided by the specified load instruction. If possible,
71 /// try to fold the load as an operand to the instruction, returning true if
73 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
74 const LoadInst *LI) override;
76 bool fastLowerArguments() override;
77 bool fastLowerCall(CallLoweringInfo &CLI) override;
78 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
80 #include "X86GenFastISel.inc"
83 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
85 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, MachineMemOperand *MMO,
88 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM,
89 MachineMemOperand *MMO = nullptr, bool Aligned = false);
90 bool X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
91 const X86AddressMode &AM,
92 MachineMemOperand *MMO = nullptr, bool Aligned = false);
94 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
97 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
98 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
100 bool X86SelectLoad(const Instruction *I);
102 bool X86SelectStore(const Instruction *I);
104 bool X86SelectRet(const Instruction *I);
106 bool X86SelectCmp(const Instruction *I);
108 bool X86SelectZExt(const Instruction *I);
110 bool X86SelectBranch(const Instruction *I);
112 bool X86SelectShift(const Instruction *I);
114 bool X86SelectDivRem(const Instruction *I);
116 bool X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I);
118 bool X86FastEmitSSESelect(MVT RetVT, const Instruction *I);
120 bool X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I);
122 bool X86SelectSelect(const Instruction *I);
124 bool X86SelectTrunc(const Instruction *I);
126 bool X86SelectFPExt(const Instruction *I);
127 bool X86SelectFPTrunc(const Instruction *I);
129 const X86InstrInfo *getInstrInfo() const {
130 return getTargetMachine()->getSubtargetImpl()->getInstrInfo();
132 const X86TargetMachine *getTargetMachine() const {
133 return static_cast<const X86TargetMachine *>(&TM);
136 bool handleConstantAddresses(const Value *V, X86AddressMode &AM);
138 unsigned X86MaterializeInt(const ConstantInt *CI, MVT VT);
139 unsigned X86MaterializeFP(const ConstantFP *CFP, MVT VT);
140 unsigned X86MaterializeGV(const GlobalValue *GV, MVT VT);
141 unsigned fastMaterializeConstant(const Constant *C) override;
143 unsigned fastMaterializeAlloca(const AllocaInst *C) override;
145 unsigned fastMaterializeFloatZero(const ConstantFP *CF) override;
147 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
148 /// computed in an SSE register, not on the X87 floating point stack.
149 bool isScalarFPTypeInSSEReg(EVT VT) const {
150 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
151 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
154 bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false);
156 bool IsMemcpySmall(uint64_t Len);
158 bool TryEmitSmallMemcpy(X86AddressMode DestAM,
159 X86AddressMode SrcAM, uint64_t Len);
161 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
165 } // end anonymous namespace.
167 static std::pair<X86::CondCode, bool>
168 getX86ConditionCode(CmpInst::Predicate Predicate) {
169 X86::CondCode CC = X86::COND_INVALID;
170 bool NeedSwap = false;
173 // Floating-point Predicates
174 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;
175 case CmpInst::FCMP_OLT: NeedSwap = true; // fall-through
176 case CmpInst::FCMP_OGT: CC = X86::COND_A; break;
177 case CmpInst::FCMP_OLE: NeedSwap = true; // fall-through
178 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;
179 case CmpInst::FCMP_UGT: NeedSwap = true; // fall-through
180 case CmpInst::FCMP_ULT: CC = X86::COND_B; break;
181 case CmpInst::FCMP_UGE: NeedSwap = true; // fall-through
182 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;
183 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;
184 case CmpInst::FCMP_UNO: CC = X86::COND_P; break;
185 case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;
186 case CmpInst::FCMP_OEQ: // fall-through
187 case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
189 // Integer Predicates
190 case CmpInst::ICMP_EQ: CC = X86::COND_E; break;
191 case CmpInst::ICMP_NE: CC = X86::COND_NE; break;
192 case CmpInst::ICMP_UGT: CC = X86::COND_A; break;
193 case CmpInst::ICMP_UGE: CC = X86::COND_AE; break;
194 case CmpInst::ICMP_ULT: CC = X86::COND_B; break;
195 case CmpInst::ICMP_ULE: CC = X86::COND_BE; break;
196 case CmpInst::ICMP_SGT: CC = X86::COND_G; break;
197 case CmpInst::ICMP_SGE: CC = X86::COND_GE; break;
198 case CmpInst::ICMP_SLT: CC = X86::COND_L; break;
199 case CmpInst::ICMP_SLE: CC = X86::COND_LE; break;
202 return std::make_pair(CC, NeedSwap);
205 static std::pair<unsigned, bool>
206 getX86SSEConditionCode(CmpInst::Predicate Predicate) {
208 bool NeedSwap = false;
210 // SSE Condition code mapping:
220 default: llvm_unreachable("Unexpected predicate");
221 case CmpInst::FCMP_OEQ: CC = 0; break;
222 case CmpInst::FCMP_OGT: NeedSwap = true; // fall-through
223 case CmpInst::FCMP_OLT: CC = 1; break;
224 case CmpInst::FCMP_OGE: NeedSwap = true; // fall-through
225 case CmpInst::FCMP_OLE: CC = 2; break;
226 case CmpInst::FCMP_UNO: CC = 3; break;
227 case CmpInst::FCMP_UNE: CC = 4; break;
228 case CmpInst::FCMP_ULE: NeedSwap = true; // fall-through
229 case CmpInst::FCMP_UGE: CC = 5; break;
230 case CmpInst::FCMP_ULT: NeedSwap = true; // fall-through
231 case CmpInst::FCMP_UGT: CC = 6; break;
232 case CmpInst::FCMP_ORD: CC = 7; break;
233 case CmpInst::FCMP_UEQ:
234 case CmpInst::FCMP_ONE: CC = 8; break;
237 return std::make_pair(CC, NeedSwap);
240 /// \brief Check if it is possible to fold the condition from the XALU intrinsic
241 /// into the user. The condition code will only be updated on success.
242 bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
244 if (!isa<ExtractValueInst>(Cond))
247 const auto *EV = cast<ExtractValueInst>(Cond);
248 if (!isa<IntrinsicInst>(EV->getAggregateOperand()))
251 const auto *II = cast<IntrinsicInst>(EV->getAggregateOperand());
253 const Function *Callee = II->getCalledFunction();
255 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(0U);
256 if (!isTypeLegal(RetTy, RetVT))
259 if (RetVT != MVT::i32 && RetVT != MVT::i64)
263 switch (II->getIntrinsicID()) {
264 default: return false;
265 case Intrinsic::sadd_with_overflow:
266 case Intrinsic::ssub_with_overflow:
267 case Intrinsic::smul_with_overflow:
268 case Intrinsic::umul_with_overflow: TmpCC = X86::COND_O; break;
269 case Intrinsic::uadd_with_overflow:
270 case Intrinsic::usub_with_overflow: TmpCC = X86::COND_B; break;
273 // Check if both instructions are in the same basic block.
274 if (II->getParent() != I->getParent())
277 // Make sure nothing is in the way
278 BasicBlock::const_iterator Start = I;
279 BasicBlock::const_iterator End = II;
280 for (auto Itr = std::prev(Start); Itr != End; --Itr) {
281 // We only expect extractvalue instructions between the intrinsic and the
282 // instruction to be selected.
283 if (!isa<ExtractValueInst>(Itr))
286 // Check that the extractvalue operand comes from the intrinsic.
287 const auto *EVI = cast<ExtractValueInst>(Itr);
288 if (EVI->getAggregateOperand() != II)
296 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
297 EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true);
298 if (evt == MVT::Other || !evt.isSimple())
299 // Unhandled type. Halt "fast" selection and bail.
302 VT = evt.getSimpleVT();
303 // For now, require SSE/SSE2 for performing floating-point operations,
304 // since x87 requires additional work.
305 if (VT == MVT::f64 && !X86ScalarSSEf64)
307 if (VT == MVT::f32 && !X86ScalarSSEf32)
309 // Similarly, no f80 support yet.
312 // We only handle legal types. For example, on x86-32 the instruction
313 // selector contains all of the 64-bit instructions from x86-64,
314 // under the assumption that i64 won't be used if the target doesn't
316 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
319 #include "X86GenCallingConv.inc"
321 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
322 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
323 /// Return true and the result register by reference if it is possible.
324 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
325 MachineMemOperand *MMO, unsigned &ResultReg) {
326 // Get opcode and regclass of the output for the given load instruction.
328 const TargetRegisterClass *RC = nullptr;
329 switch (VT.getSimpleVT().SimpleTy) {
330 default: return false;
334 RC = &X86::GR8RegClass;
338 RC = &X86::GR16RegClass;
342 RC = &X86::GR32RegClass;
345 // Must be in x86-64 mode.
347 RC = &X86::GR64RegClass;
350 if (X86ScalarSSEf32) {
351 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
352 RC = &X86::FR32RegClass;
355 RC = &X86::RFP32RegClass;
359 if (X86ScalarSSEf64) {
360 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
361 RC = &X86::FR64RegClass;
364 RC = &X86::RFP64RegClass;
368 // No f80 support yet.
372 ResultReg = createResultReg(RC);
373 MachineInstrBuilder MIB =
374 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
375 addFullAddress(MIB, AM);
377 MIB->addMemOperand(*FuncInfo.MF, MMO);
381 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
382 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
383 /// and a displacement offset, or a GlobalAddress,
384 /// i.e. V. Return true if it is possible.
385 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill,
386 const X86AddressMode &AM,
387 MachineMemOperand *MMO, bool Aligned) {
388 // Get opcode and regclass of the output for the given store instruction.
390 switch (VT.getSimpleVT().SimpleTy) {
391 case MVT::f80: // No f80 support yet.
392 default: return false;
394 // Mask out all but lowest bit.
395 unsigned AndResult = createResultReg(&X86::GR8RegClass);
396 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
397 TII.get(X86::AND8ri), AndResult)
398 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1);
401 // FALLTHROUGH, handling i1 as i8.
402 case MVT::i8: Opc = X86::MOV8mr; break;
403 case MVT::i16: Opc = X86::MOV16mr; break;
404 case MVT::i32: Opc = X86::MOV32mr; break;
405 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
407 Opc = X86ScalarSSEf32 ?
408 (Subtarget->hasAVX() ? X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m;
411 Opc = X86ScalarSSEf64 ?
412 (Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m;
416 Opc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
418 Opc = Subtarget->hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr;
422 Opc = Subtarget->hasAVX() ? X86::VMOVAPDmr : X86::MOVAPDmr;
424 Opc = Subtarget->hasAVX() ? X86::VMOVUPDmr : X86::MOVUPDmr;
431 Opc = Subtarget->hasAVX() ? X86::VMOVDQAmr : X86::MOVDQAmr;
433 Opc = Subtarget->hasAVX() ? X86::VMOVDQUmr : X86::MOVDQUmr;
437 MachineInstrBuilder MIB =
438 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
439 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill));
441 MIB->addMemOperand(*FuncInfo.MF, MMO);
446 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
447 const X86AddressMode &AM,
448 MachineMemOperand *MMO, bool Aligned) {
449 // Handle 'null' like i32/i64 0.
450 if (isa<ConstantPointerNull>(Val))
451 Val = Constant::getNullValue(DL.getIntPtrType(Val->getContext()));
453 // If this is a store of a simple constant, fold the constant into the store.
454 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
457 switch (VT.getSimpleVT().SimpleTy) {
459 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
460 case MVT::i8: Opc = X86::MOV8mi; break;
461 case MVT::i16: Opc = X86::MOV16mi; break;
462 case MVT::i32: Opc = X86::MOV32mi; break;
464 // Must be a 32-bit sign extended value.
465 if (isInt<32>(CI->getSExtValue()))
466 Opc = X86::MOV64mi32;
471 MachineInstrBuilder MIB =
472 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
473 addFullAddress(MIB, AM).addImm(Signed ? (uint64_t) CI->getSExtValue()
474 : CI->getZExtValue());
476 MIB->addMemOperand(*FuncInfo.MF, MMO);
481 unsigned ValReg = getRegForValue(Val);
485 bool ValKill = hasTrivialKill(Val);
486 return X86FastEmitStore(VT, ValReg, ValKill, AM, MMO, Aligned);
489 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
490 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
491 /// ISD::SIGN_EXTEND).
492 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
493 unsigned Src, EVT SrcVT,
494 unsigned &ResultReg) {
495 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
496 Src, /*TODO: Kill=*/false);
504 bool X86FastISel::handleConstantAddresses(const Value *V, X86AddressMode &AM) {
505 // Handle constant address.
506 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
507 // Can't handle alternate code models yet.
508 if (TM.getCodeModel() != CodeModel::Small)
511 // Can't handle TLS yet.
512 if (GV->isThreadLocal())
515 // RIP-relative addresses can't have additional register operands, so if
516 // we've already folded stuff into the addressing mode, just force the
517 // global value into its own register, which we can use as the basereg.
518 if (!Subtarget->isPICStyleRIPRel() ||
519 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
520 // Okay, we've committed to selecting this global. Set up the address.
523 // Allow the subtarget to classify the global.
524 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
526 // If this reference is relative to the pic base, set it now.
527 if (isGlobalRelativeToPICBase(GVFlags)) {
528 // FIXME: How do we know Base.Reg is free??
529 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
532 // Unless the ABI requires an extra load, return a direct reference to
534 if (!isGlobalStubReference(GVFlags)) {
535 if (Subtarget->isPICStyleRIPRel()) {
536 // Use rip-relative addressing if we can. Above we verified that the
537 // base and index registers are unused.
538 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
539 AM.Base.Reg = X86::RIP;
541 AM.GVOpFlags = GVFlags;
545 // Ok, we need to do a load from a stub. If we've already loaded from
546 // this stub, reuse the loaded pointer, otherwise emit the load now.
547 DenseMap<const Value *, unsigned>::iterator I = LocalValueMap.find(V);
549 if (I != LocalValueMap.end() && I->second != 0) {
552 // Issue load from stub.
554 const TargetRegisterClass *RC = nullptr;
555 X86AddressMode StubAM;
556 StubAM.Base.Reg = AM.Base.Reg;
558 StubAM.GVOpFlags = GVFlags;
560 // Prepare for inserting code in the local-value area.
561 SavePoint SaveInsertPt = enterLocalValueArea();
563 if (TLI.getPointerTy() == MVT::i64) {
565 RC = &X86::GR64RegClass;
567 if (Subtarget->isPICStyleRIPRel())
568 StubAM.Base.Reg = X86::RIP;
571 RC = &X86::GR32RegClass;
574 LoadReg = createResultReg(RC);
575 MachineInstrBuilder LoadMI =
576 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), LoadReg);
577 addFullAddress(LoadMI, StubAM);
579 // Ok, back to normal mode.
580 leaveLocalValueArea(SaveInsertPt);
582 // Prevent loading GV stub multiple times in same MBB.
583 LocalValueMap[V] = LoadReg;
586 // Now construct the final address. Note that the Disp, Scale,
587 // and Index values may already be set here.
588 AM.Base.Reg = LoadReg;
594 // If all else fails, try to materialize the value in a register.
595 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
596 if (AM.Base.Reg == 0) {
597 AM.Base.Reg = getRegForValue(V);
598 return AM.Base.Reg != 0;
600 if (AM.IndexReg == 0) {
601 assert(AM.Scale == 1 && "Scale with no index!");
602 AM.IndexReg = getRegForValue(V);
603 return AM.IndexReg != 0;
610 /// X86SelectAddress - Attempt to fill in an address from the given value.
612 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
613 SmallVector<const Value *, 32> GEPs;
615 const User *U = nullptr;
616 unsigned Opcode = Instruction::UserOp1;
617 if (const Instruction *I = dyn_cast<Instruction>(V)) {
618 // Don't walk into other basic blocks; it's possible we haven't
619 // visited them yet, so the instructions may not yet be assigned
620 // virtual registers.
621 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(V)) ||
622 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
623 Opcode = I->getOpcode();
626 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
627 Opcode = C->getOpcode();
631 if (PointerType *Ty = dyn_cast<PointerType>(V->getType()))
632 if (Ty->getAddressSpace() > 255)
633 // Fast instruction selection doesn't support the special
639 case Instruction::BitCast:
640 // Look past bitcasts.
641 return X86SelectAddress(U->getOperand(0), AM);
643 case Instruction::IntToPtr:
644 // Look past no-op inttoptrs.
645 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
646 return X86SelectAddress(U->getOperand(0), AM);
649 case Instruction::PtrToInt:
650 // Look past no-op ptrtoints.
651 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
652 return X86SelectAddress(U->getOperand(0), AM);
655 case Instruction::Alloca: {
656 // Do static allocas.
657 const AllocaInst *A = cast<AllocaInst>(V);
658 DenseMap<const AllocaInst *, int>::iterator SI =
659 FuncInfo.StaticAllocaMap.find(A);
660 if (SI != FuncInfo.StaticAllocaMap.end()) {
661 AM.BaseType = X86AddressMode::FrameIndexBase;
662 AM.Base.FrameIndex = SI->second;
668 case Instruction::Add: {
669 // Adds of constants are common and easy enough.
670 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
671 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
672 // They have to fit in the 32-bit signed displacement field though.
673 if (isInt<32>(Disp)) {
674 AM.Disp = (uint32_t)Disp;
675 return X86SelectAddress(U->getOperand(0), AM);
681 case Instruction::GetElementPtr: {
682 X86AddressMode SavedAM = AM;
684 // Pattern-match simple GEPs.
685 uint64_t Disp = (int32_t)AM.Disp;
686 unsigned IndexReg = AM.IndexReg;
687 unsigned Scale = AM.Scale;
688 gep_type_iterator GTI = gep_type_begin(U);
689 // Iterate through the indices, folding what we can. Constants can be
690 // folded, and one dynamic index can be handled, if the scale is supported.
691 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
692 i != e; ++i, ++GTI) {
693 const Value *Op = *i;
694 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
695 const StructLayout *SL = DL.getStructLayout(STy);
696 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue());
700 // A array/variable index is always of the form i*S where S is the
701 // constant scale size. See if we can push the scale into immediates.
702 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
704 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
705 // Constant-offset addressing.
706 Disp += CI->getSExtValue() * S;
709 if (canFoldAddIntoGEP(U, Op)) {
710 // A compatible add with a constant operand. Fold the constant.
712 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
713 Disp += CI->getSExtValue() * S;
714 // Iterate on the other operand.
715 Op = cast<AddOperator>(Op)->getOperand(0);
719 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
720 (S == 1 || S == 2 || S == 4 || S == 8)) {
721 // Scaled-index addressing.
723 IndexReg = getRegForGEPIndex(Op).first;
729 goto unsupported_gep;
733 // Check for displacement overflow.
734 if (!isInt<32>(Disp))
737 AM.IndexReg = IndexReg;
739 AM.Disp = (uint32_t)Disp;
742 if (const GetElementPtrInst *GEP =
743 dyn_cast<GetElementPtrInst>(U->getOperand(0))) {
744 // Ok, the GEP indices were covered by constant-offset and scaled-index
745 // addressing. Update the address state and move on to examining the base.
748 } else if (X86SelectAddress(U->getOperand(0), AM)) {
752 // If we couldn't merge the gep value into this addr mode, revert back to
753 // our address and just match the value instead of completely failing.
756 for (SmallVectorImpl<const Value *>::reverse_iterator
757 I = GEPs.rbegin(), E = GEPs.rend(); I != E; ++I)
758 if (handleConstantAddresses(*I, AM))
763 // Ok, the GEP indices weren't all covered.
768 return handleConstantAddresses(V, AM);
771 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
773 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
774 const User *U = nullptr;
775 unsigned Opcode = Instruction::UserOp1;
776 const Instruction *I = dyn_cast<Instruction>(V);
777 // Record if the value is defined in the same basic block.
779 // This information is crucial to know whether or not folding an
781 // Indeed, FastISel generates or reuses a virtual register for all
782 // operands of all instructions it selects. Obviously, the definition and
783 // its uses must use the same virtual register otherwise the produced
784 // code is incorrect.
785 // Before instruction selection, FunctionLoweringInfo::set sets the virtual
786 // registers for values that are alive across basic blocks. This ensures
787 // that the values are consistently set between across basic block, even
788 // if different instruction selection mechanisms are used (e.g., a mix of
789 // SDISel and FastISel).
790 // For values local to a basic block, the instruction selection process
791 // generates these virtual registers with whatever method is appropriate
792 // for its needs. In particular, FastISel and SDISel do not share the way
793 // local virtual registers are set.
794 // Therefore, this is impossible (or at least unsafe) to share values
795 // between basic blocks unless they use the same instruction selection
796 // method, which is not guarantee for X86.
797 // Moreover, things like hasOneUse could not be used accurately, if we
798 // allow to reference values across basic blocks whereas they are not
799 // alive across basic blocks initially.
802 Opcode = I->getOpcode();
804 InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock();
805 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
806 Opcode = C->getOpcode();
812 case Instruction::BitCast:
813 // Look past bitcasts if its operand is in the same BB.
815 return X86SelectCallAddress(U->getOperand(0), AM);
818 case Instruction::IntToPtr:
819 // Look past no-op inttoptrs if its operand is in the same BB.
821 TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
822 return X86SelectCallAddress(U->getOperand(0), AM);
825 case Instruction::PtrToInt:
826 // Look past no-op ptrtoints if its operand is in the same BB.
828 TLI.getValueType(U->getType()) == TLI.getPointerTy())
829 return X86SelectCallAddress(U->getOperand(0), AM);
833 // Handle constant address.
834 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
835 // Can't handle alternate code models yet.
836 if (TM.getCodeModel() != CodeModel::Small)
839 // RIP-relative addresses can't have additional register operands.
840 if (Subtarget->isPICStyleRIPRel() &&
841 (AM.Base.Reg != 0 || AM.IndexReg != 0))
844 // Can't handle DLL Import.
845 if (GV->hasDLLImportStorageClass())
849 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
850 if (GVar->isThreadLocal())
853 // Okay, we've committed to selecting this global. Set up the basic address.
856 // No ABI requires an extra load for anything other than DLLImport, which
857 // we rejected above. Return a direct reference to the global.
858 if (Subtarget->isPICStyleRIPRel()) {
859 // Use rip-relative addressing if we can. Above we verified that the
860 // base and index registers are unused.
861 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
862 AM.Base.Reg = X86::RIP;
863 } else if (Subtarget->isPICStyleStubPIC()) {
864 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
865 } else if (Subtarget->isPICStyleGOT()) {
866 AM.GVOpFlags = X86II::MO_GOTOFF;
872 // If all else fails, try to materialize the value in a register.
873 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
874 if (AM.Base.Reg == 0) {
875 AM.Base.Reg = getRegForValue(V);
876 return AM.Base.Reg != 0;
878 if (AM.IndexReg == 0) {
879 assert(AM.Scale == 1 && "Scale with no index!");
880 AM.IndexReg = getRegForValue(V);
881 return AM.IndexReg != 0;
889 /// X86SelectStore - Select and emit code to implement store instructions.
890 bool X86FastISel::X86SelectStore(const Instruction *I) {
891 // Atomic stores need special handling.
892 const StoreInst *S = cast<StoreInst>(I);
897 const Value *Val = S->getValueOperand();
898 const Value *Ptr = S->getPointerOperand();
901 if (!isTypeLegal(Val->getType(), VT, /*AllowI1=*/true))
904 unsigned Alignment = S->getAlignment();
905 unsigned ABIAlignment = DL.getABITypeAlignment(Val->getType());
906 if (Alignment == 0) // Ensure that codegen never sees alignment 0
907 Alignment = ABIAlignment;
908 bool Aligned = Alignment >= ABIAlignment;
911 if (!X86SelectAddress(Ptr, AM))
914 return X86FastEmitStore(VT, Val, AM, createMachineMemOperandFor(I), Aligned);
917 /// X86SelectRet - Select and emit code to implement ret instructions.
918 bool X86FastISel::X86SelectRet(const Instruction *I) {
919 const ReturnInst *Ret = cast<ReturnInst>(I);
920 const Function &F = *I->getParent()->getParent();
921 const X86MachineFunctionInfo *X86MFInfo =
922 FuncInfo.MF->getInfo<X86MachineFunctionInfo>();
924 if (!FuncInfo.CanLowerReturn)
927 CallingConv::ID CC = F.getCallingConv();
928 if (CC != CallingConv::C &&
929 CC != CallingConv::Fast &&
930 CC != CallingConv::X86_FastCall &&
931 CC != CallingConv::X86_64_SysV)
934 if (Subtarget->isCallingConvWin64(CC))
937 // Don't handle popping bytes on return for now.
938 if (X86MFInfo->getBytesToPopOnReturn() != 0)
941 // fastcc with -tailcallopt is intended to provide a guaranteed
942 // tail call optimization. Fastisel doesn't know how to do that.
943 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt)
946 // Let SDISel handle vararg functions.
950 // Build a list of return value registers.
951 SmallVector<unsigned, 4> RetRegs;
953 if (Ret->getNumOperands() > 0) {
954 SmallVector<ISD::OutputArg, 4> Outs;
955 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
957 // Analyze operands of the call, assigning locations to each operand.
958 SmallVector<CCValAssign, 16> ValLocs;
959 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
960 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
962 const Value *RV = Ret->getOperand(0);
963 unsigned Reg = getRegForValue(RV);
967 // Only handle a single return value for now.
968 if (ValLocs.size() != 1)
971 CCValAssign &VA = ValLocs[0];
973 // Don't bother handling odd stuff for now.
974 if (VA.getLocInfo() != CCValAssign::Full)
976 // Only handle register returns for now.
980 // The calling-convention tables for x87 returns don't tell
982 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
985 unsigned SrcReg = Reg + VA.getValNo();
986 EVT SrcVT = TLI.getValueType(RV->getType());
987 EVT DstVT = VA.getValVT();
988 // Special handling for extended integers.
989 if (SrcVT != DstVT) {
990 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
993 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
996 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
998 if (SrcVT == MVT::i1) {
999 if (Outs[0].Flags.isSExt())
1001 SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
1004 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
1006 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
1007 SrcReg, /*TODO: Kill=*/false);
1011 unsigned DstReg = VA.getLocReg();
1012 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
1013 // Avoid a cross-class copy. This is very unlikely.
1014 if (!SrcRC->contains(DstReg))
1016 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1017 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
1019 // Add register to return instruction.
1020 RetRegs.push_back(VA.getLocReg());
1023 // The x86-64 ABI for returning structs by value requires that we copy
1024 // the sret argument into %rax for the return. We saved the argument into
1025 // a virtual register in the entry block, so now we copy the value out
1026 // and into %rax. We also do the same with %eax for Win32.
1027 if (F.hasStructRetAttr() &&
1028 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
1029 unsigned Reg = X86MFInfo->getSRetReturnReg();
1031 "SRetReturnReg should have been set in LowerFormalArguments()!");
1032 unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
1033 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1034 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg);
1035 RetRegs.push_back(RetReg);
1038 // Now emit the RET.
1039 MachineInstrBuilder MIB =
1040 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1041 TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL));
1042 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1043 MIB.addReg(RetRegs[i], RegState::Implicit);
1047 /// X86SelectLoad - Select and emit code to implement load instructions.
1049 bool X86FastISel::X86SelectLoad(const Instruction *I) {
1050 const LoadInst *LI = cast<LoadInst>(I);
1052 // Atomic loads need special handling.
1057 if (!isTypeLegal(LI->getType(), VT, /*AllowI1=*/true))
1060 const Value *Ptr = LI->getPointerOperand();
1063 if (!X86SelectAddress(Ptr, AM))
1066 unsigned ResultReg = 0;
1067 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg))
1070 updateValueMap(I, ResultReg);
1074 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) {
1075 bool HasAVX = Subtarget->hasAVX();
1076 bool X86ScalarSSEf32 = Subtarget->hasSSE1();
1077 bool X86ScalarSSEf64 = Subtarget->hasSSE2();
1079 switch (VT.getSimpleVT().SimpleTy) {
1081 case MVT::i8: return X86::CMP8rr;
1082 case MVT::i16: return X86::CMP16rr;
1083 case MVT::i32: return X86::CMP32rr;
1084 case MVT::i64: return X86::CMP64rr;
1086 return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0;
1088 return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0;
1092 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
1093 /// of the comparison, return an opcode that works for the compare (e.g.
1094 /// CMP32ri) otherwise return 0.
1095 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
1096 switch (VT.getSimpleVT().SimpleTy) {
1097 // Otherwise, we can't fold the immediate into this comparison.
1099 case MVT::i8: return X86::CMP8ri;
1100 case MVT::i16: return X86::CMP16ri;
1101 case MVT::i32: return X86::CMP32ri;
1103 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
1105 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
1106 return X86::CMP64ri32;
1111 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
1113 unsigned Op0Reg = getRegForValue(Op0);
1114 if (Op0Reg == 0) return false;
1116 // Handle 'null' like i32/i64 0.
1117 if (isa<ConstantPointerNull>(Op1))
1118 Op1 = Constant::getNullValue(DL.getIntPtrType(Op0->getContext()));
1120 // We have two options: compare with register or immediate. If the RHS of
1121 // the compare is an immediate that we can fold into this compare, use
1122 // CMPri, otherwise use CMPrr.
1123 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
1124 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
1125 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CompareImmOpc))
1127 .addImm(Op1C->getSExtValue());
1132 unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget);
1133 if (CompareOpc == 0) return false;
1135 unsigned Op1Reg = getRegForValue(Op1);
1136 if (Op1Reg == 0) return false;
1137 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CompareOpc))
1144 bool X86FastISel::X86SelectCmp(const Instruction *I) {
1145 const CmpInst *CI = cast<CmpInst>(I);
1148 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
1151 // Try to optimize or fold the cmp.
1152 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
1153 unsigned ResultReg = 0;
1154 switch (Predicate) {
1156 case CmpInst::FCMP_FALSE: {
1157 ResultReg = createResultReg(&X86::GR32RegClass);
1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV32r0),
1160 ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultReg, /*Kill=*/true,
1166 case CmpInst::FCMP_TRUE: {
1167 ResultReg = createResultReg(&X86::GR8RegClass);
1168 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
1169 ResultReg).addImm(1);
1175 updateValueMap(I, ResultReg);
1179 const Value *LHS = CI->getOperand(0);
1180 const Value *RHS = CI->getOperand(1);
1182 // The optimizer might have replaced fcmp oeq %x, %x with fcmp ord %x, 0.0.
1183 // We don't have to materialize a zero constant for this case and can just use
1184 // %x again on the RHS.
1185 if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) {
1186 const auto *RHSC = dyn_cast<ConstantFP>(RHS);
1187 if (RHSC && RHSC->isNullValue())
1191 // FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction.
1192 static unsigned SETFOpcTable[2][3] = {
1193 { X86::SETEr, X86::SETNPr, X86::AND8rr },
1194 { X86::SETNEr, X86::SETPr, X86::OR8rr }
1196 unsigned *SETFOpc = nullptr;
1197 switch (Predicate) {
1199 case CmpInst::FCMP_OEQ: SETFOpc = &SETFOpcTable[0][0]; break;
1200 case CmpInst::FCMP_UNE: SETFOpc = &SETFOpcTable[1][0]; break;
1203 ResultReg = createResultReg(&X86::GR8RegClass);
1205 if (!X86FastEmitCompare(LHS, RHS, VT))
1208 unsigned FlagReg1 = createResultReg(&X86::GR8RegClass);
1209 unsigned FlagReg2 = createResultReg(&X86::GR8RegClass);
1210 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[0]),
1212 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[1]),
1214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[2]),
1215 ResultReg).addReg(FlagReg1).addReg(FlagReg2);
1216 updateValueMap(I, ResultReg);
1222 std::tie(CC, SwapArgs) = getX86ConditionCode(Predicate);
1223 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
1224 unsigned Opc = X86::getSETFromCond(CC);
1227 std::swap(LHS, RHS);
1229 // Emit a compare of LHS/RHS.
1230 if (!X86FastEmitCompare(LHS, RHS, VT))
1233 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
1234 updateValueMap(I, ResultReg);
1238 bool X86FastISel::X86SelectZExt(const Instruction *I) {
1239 EVT DstVT = TLI.getValueType(I->getType());
1240 if (!TLI.isTypeLegal(DstVT))
1243 unsigned ResultReg = getRegForValue(I->getOperand(0));
1247 // Handle zero-extension from i1 to i8, which is common.
1248 MVT SrcVT = TLI.getSimpleValueType(I->getOperand(0)->getType());
1249 if (SrcVT.SimpleTy == MVT::i1) {
1250 // Set the high bits to zero.
1251 ResultReg = fastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
1258 if (DstVT == MVT::i64) {
1259 // Handle extension to 64-bits via sub-register shenanigans.
1262 switch (SrcVT.SimpleTy) {
1263 case MVT::i8: MovInst = X86::MOVZX32rr8; break;
1264 case MVT::i16: MovInst = X86::MOVZX32rr16; break;
1265 case MVT::i32: MovInst = X86::MOV32rr; break;
1266 default: llvm_unreachable("Unexpected zext to i64 source type");
1269 unsigned Result32 = createResultReg(&X86::GR32RegClass);
1270 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovInst), Result32)
1273 ResultReg = createResultReg(&X86::GR64RegClass);
1274 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::SUBREG_TO_REG),
1276 .addImm(0).addReg(Result32).addImm(X86::sub_32bit);
1277 } else if (DstVT != MVT::i8) {
1278 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND,
1279 ResultReg, /*Kill=*/true);
1284 updateValueMap(I, ResultReg);
1288 bool X86FastISel::X86SelectBranch(const Instruction *I) {
1289 // Unconditional branches are selected by tablegen-generated code.
1290 // Handle a conditional branch.
1291 const BranchInst *BI = cast<BranchInst>(I);
1292 MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1293 MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1295 // Fold the common case of a conditional branch with a comparison
1296 // in the same block (values defined on other blocks may not have
1297 // initialized registers).
1299 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1300 if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
1301 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
1303 // Try to optimize or fold the cmp.
1304 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
1305 switch (Predicate) {
1307 case CmpInst::FCMP_FALSE: fastEmitBranch(FalseMBB, DbgLoc); return true;
1308 case CmpInst::FCMP_TRUE: fastEmitBranch(TrueMBB, DbgLoc); return true;
1311 const Value *CmpLHS = CI->getOperand(0);
1312 const Value *CmpRHS = CI->getOperand(1);
1314 // The optimizer might have replaced fcmp oeq %x, %x with fcmp ord %x,
1316 // We don't have to materialize a zero constant for this case and can just
1317 // use %x again on the RHS.
1318 if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) {
1319 const auto *CmpRHSC = dyn_cast<ConstantFP>(CmpRHS);
1320 if (CmpRHSC && CmpRHSC->isNullValue())
1324 // Try to take advantage of fallthrough opportunities.
1325 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
1326 std::swap(TrueMBB, FalseMBB);
1327 Predicate = CmpInst::getInversePredicate(Predicate);
1330 // FCMP_OEQ and FCMP_UNE cannot be expressed with a single flag/condition
1331 // code check. Instead two branch instructions are required to check all
1332 // the flags. First we change the predicate to a supported condition code,
1333 // which will be the first branch. Later one we will emit the second
1335 bool NeedExtraBranch = false;
1336 switch (Predicate) {
1338 case CmpInst::FCMP_OEQ:
1339 std::swap(TrueMBB, FalseMBB); // fall-through
1340 case CmpInst::FCMP_UNE:
1341 NeedExtraBranch = true;
1342 Predicate = CmpInst::FCMP_ONE;
1348 std::tie(CC, SwapArgs) = getX86ConditionCode(Predicate);
1349 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
1351 BranchOpc = X86::GetCondBranchFromCond(CC);
1353 std::swap(CmpLHS, CmpRHS);
1355 // Emit a compare of the LHS and RHS, setting the flags.
1356 if (!X86FastEmitCompare(CmpLHS, CmpRHS, VT))
1359 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BranchOpc))
1362 // X86 requires a second branch to handle UNE (and OEQ, which is mapped
1364 if (NeedExtraBranch) {
1365 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JP_4))
1369 // Obtain the branch weight and add the TrueBB to the successor list.
1370 uint32_t BranchWeight = 0;
1372 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1373 TrueMBB->getBasicBlock());
1374 FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
1376 // Emits an unconditional branch to the FalseBB, obtains the branch
1377 // weight, and adds it to the successor list.
1378 fastEmitBranch(FalseMBB, DbgLoc);
1382 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1383 // Handle things like "%cond = trunc i32 %X to i1 / br i1 %cond", which
1384 // typically happen for _Bool and C++ bools.
1386 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1387 isTypeLegal(TI->getOperand(0)->getType(), SourceVT)) {
1388 unsigned TestOpc = 0;
1389 switch (SourceVT.SimpleTy) {
1391 case MVT::i8: TestOpc = X86::TEST8ri; break;
1392 case MVT::i16: TestOpc = X86::TEST16ri; break;
1393 case MVT::i32: TestOpc = X86::TEST32ri; break;
1394 case MVT::i64: TestOpc = X86::TEST64ri32; break;
1397 unsigned OpReg = getRegForValue(TI->getOperand(0));
1398 if (OpReg == 0) return false;
1399 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc))
1400 .addReg(OpReg).addImm(1);
1402 unsigned JmpOpc = X86::JNE_4;
1403 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
1404 std::swap(TrueMBB, FalseMBB);
1408 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(JmpOpc))
1410 fastEmitBranch(FalseMBB, DbgLoc);
1411 uint32_t BranchWeight = 0;
1413 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1414 TrueMBB->getBasicBlock());
1415 FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
1419 } else if (foldX86XALUIntrinsic(CC, BI, BI->getCondition())) {
1420 // Fake request the condition, otherwise the intrinsic might be completely
1422 unsigned TmpReg = getRegForValue(BI->getCondition());
1426 unsigned BranchOpc = X86::GetCondBranchFromCond(CC);
1428 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BranchOpc))
1430 fastEmitBranch(FalseMBB, DbgLoc);
1431 uint32_t BranchWeight = 0;
1433 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1434 TrueMBB->getBasicBlock());
1435 FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
1439 // Otherwise do a clumsy setcc and re-test it.
1440 // Note that i1 essentially gets ANY_EXTEND'ed to i8 where it isn't used
1441 // in an explicit cast, so make sure to handle that correctly.
1442 unsigned OpReg = getRegForValue(BI->getCondition());
1443 if (OpReg == 0) return false;
1445 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
1446 .addReg(OpReg).addImm(1);
1447 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JNE_4))
1449 fastEmitBranch(FalseMBB, DbgLoc);
1450 uint32_t BranchWeight = 0;
1452 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1453 TrueMBB->getBasicBlock());
1454 FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
1458 bool X86FastISel::X86SelectShift(const Instruction *I) {
1459 unsigned CReg = 0, OpReg = 0;
1460 const TargetRegisterClass *RC = nullptr;
1461 if (I->getType()->isIntegerTy(8)) {
1463 RC = &X86::GR8RegClass;
1464 switch (I->getOpcode()) {
1465 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1466 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1467 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1468 default: return false;
1470 } else if (I->getType()->isIntegerTy(16)) {
1472 RC = &X86::GR16RegClass;
1473 switch (I->getOpcode()) {
1474 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1475 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1476 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1477 default: return false;
1479 } else if (I->getType()->isIntegerTy(32)) {
1481 RC = &X86::GR32RegClass;
1482 switch (I->getOpcode()) {
1483 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1484 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1485 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1486 default: return false;
1488 } else if (I->getType()->isIntegerTy(64)) {
1490 RC = &X86::GR64RegClass;
1491 switch (I->getOpcode()) {
1492 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1493 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1494 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1495 default: return false;
1502 if (!isTypeLegal(I->getType(), VT))
1505 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1506 if (Op0Reg == 0) return false;
1508 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1509 if (Op1Reg == 0) return false;
1510 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1511 CReg).addReg(Op1Reg);
1513 // The shift instruction uses X86::CL. If we defined a super-register
1514 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1515 if (CReg != X86::CL)
1516 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1517 TII.get(TargetOpcode::KILL), X86::CL)
1518 .addReg(CReg, RegState::Kill);
1520 unsigned ResultReg = createResultReg(RC);
1521 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg)
1523 updateValueMap(I, ResultReg);
1527 bool X86FastISel::X86SelectDivRem(const Instruction *I) {
1528 const static unsigned NumTypes = 4; // i8, i16, i32, i64
1529 const static unsigned NumOps = 4; // SDiv, SRem, UDiv, URem
1530 const static bool S = true; // IsSigned
1531 const static bool U = false; // !IsSigned
1532 const static unsigned Copy = TargetOpcode::COPY;
1533 // For the X86 DIV/IDIV instruction, in most cases the dividend
1534 // (numerator) must be in a specific register pair highreg:lowreg,
1535 // producing the quotient in lowreg and the remainder in highreg.
1536 // For most data types, to set up the instruction, the dividend is
1537 // copied into lowreg, and lowreg is sign-extended or zero-extended
1538 // into highreg. The exception is i8, where the dividend is defined
1539 // as a single register rather than a register pair, and we
1540 // therefore directly sign-extend or zero-extend the dividend into
1541 // lowreg, instead of copying, and ignore the highreg.
1542 const static struct DivRemEntry {
1543 // The following portion depends only on the data type.
1544 const TargetRegisterClass *RC;
1545 unsigned LowInReg; // low part of the register pair
1546 unsigned HighInReg; // high part of the register pair
1547 // The following portion depends on both the data type and the operation.
1548 struct DivRemResult {
1549 unsigned OpDivRem; // The specific DIV/IDIV opcode to use.
1550 unsigned OpSignExtend; // Opcode for sign-extending lowreg into
1551 // highreg, or copying a zero into highreg.
1552 unsigned OpCopy; // Opcode for copying dividend into lowreg, or
1553 // zero/sign-extending into lowreg for i8.
1554 unsigned DivRemResultReg; // Register containing the desired result.
1555 bool IsOpSigned; // Whether to use signed or unsigned form.
1556 } ResultTable[NumOps];
1557 } OpTable[NumTypes] = {
1558 { &X86::GR8RegClass, X86::AX, 0, {
1559 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S }, // SDiv
1560 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S }, // SRem
1561 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U }, // UDiv
1562 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U }, // URem
1565 { &X86::GR16RegClass, X86::AX, X86::DX, {
1566 { X86::IDIV16r, X86::CWD, Copy, X86::AX, S }, // SDiv
1567 { X86::IDIV16r, X86::CWD, Copy, X86::DX, S }, // SRem
1568 { X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U }, // UDiv
1569 { X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U }, // URem
1572 { &X86::GR32RegClass, X86::EAX, X86::EDX, {
1573 { X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S }, // SDiv
1574 { X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S }, // SRem
1575 { X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv
1576 { X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U }, // URem
1579 { &X86::GR64RegClass, X86::RAX, X86::RDX, {
1580 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv
1581 { X86::IDIV64r, X86::CQO, Copy, X86::RDX, S }, // SRem
1582 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv
1583 { X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U }, // URem
1589 if (!isTypeLegal(I->getType(), VT))
1592 unsigned TypeIndex, OpIndex;
1593 switch (VT.SimpleTy) {
1594 default: return false;
1595 case MVT::i8: TypeIndex = 0; break;
1596 case MVT::i16: TypeIndex = 1; break;
1597 case MVT::i32: TypeIndex = 2; break;
1598 case MVT::i64: TypeIndex = 3;
1599 if (!Subtarget->is64Bit())
1604 switch (I->getOpcode()) {
1605 default: llvm_unreachable("Unexpected div/rem opcode");
1606 case Instruction::SDiv: OpIndex = 0; break;
1607 case Instruction::SRem: OpIndex = 1; break;
1608 case Instruction::UDiv: OpIndex = 2; break;
1609 case Instruction::URem: OpIndex = 3; break;
1612 const DivRemEntry &TypeEntry = OpTable[TypeIndex];
1613 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
1614 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1617 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1621 // Move op0 into low-order input register.
1622 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1623 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg);
1624 // Zero-extend or sign-extend into high-order input register.
1625 if (OpEntry.OpSignExtend) {
1626 if (OpEntry.IsOpSigned)
1627 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1628 TII.get(OpEntry.OpSignExtend));
1630 unsigned Zero32 = createResultReg(&X86::GR32RegClass);
1631 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1632 TII.get(X86::MOV32r0), Zero32);
1634 // Copy the zero into the appropriate sub/super/identical physical
1635 // register. Unfortunately the operations needed are not uniform enough
1636 // to fit neatly into the table above.
1637 if (VT.SimpleTy == MVT::i16) {
1638 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1639 TII.get(Copy), TypeEntry.HighInReg)
1640 .addReg(Zero32, 0, X86::sub_16bit);
1641 } else if (VT.SimpleTy == MVT::i32) {
1642 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1643 TII.get(Copy), TypeEntry.HighInReg)
1645 } else if (VT.SimpleTy == MVT::i64) {
1646 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1647 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg)
1648 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
1652 // Generate the DIV/IDIV instruction.
1653 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1654 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg);
1655 // For i8 remainder, we can't reference AH directly, as we'll end
1656 // up with bogus copies like %R9B = COPY %AH. Reference AX
1657 // instead to prevent AH references in a REX instruction.
1659 // The current assumption of the fast register allocator is that isel
1660 // won't generate explicit references to the GPR8_NOREX registers. If
1661 // the allocator and/or the backend get enhanced to be more robust in
1662 // that regard, this can be, and should be, removed.
1663 unsigned ResultReg = 0;
1664 if ((I->getOpcode() == Instruction::SRem ||
1665 I->getOpcode() == Instruction::URem) &&
1666 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) {
1667 unsigned SourceSuperReg = createResultReg(&X86::GR16RegClass);
1668 unsigned ResultSuperReg = createResultReg(&X86::GR16RegClass);
1669 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1670 TII.get(Copy), SourceSuperReg).addReg(X86::AX);
1672 // Shift AX right by 8 bits instead of using AH.
1673 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SHR16ri),
1674 ResultSuperReg).addReg(SourceSuperReg).addImm(8);
1676 // Now reference the 8-bit subreg of the result.
1677 ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultSuperReg,
1678 /*Kill=*/true, X86::sub_8bit);
1680 // Copy the result out of the physreg if we haven't already.
1682 ResultReg = createResultReg(TypeEntry.RC);
1683 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Copy), ResultReg)
1684 .addReg(OpEntry.DivRemResultReg);
1686 updateValueMap(I, ResultReg);
1691 /// \brief Emit a conditional move instruction (if the are supported) to lower
1693 bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
1694 // Check if the subtarget supports these instructions.
1695 if (!Subtarget->hasCMov())
1698 // FIXME: Add support for i8.
1699 if (RetVT < MVT::i16 || RetVT > MVT::i64)
1702 const Value *Cond = I->getOperand(0);
1703 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
1704 bool NeedTest = true;
1705 X86::CondCode CC = X86::COND_NE;
1707 // Optimize conditions coming from a compare if both instructions are in the
1708 // same basic block (values defined in other basic blocks may not have
1709 // initialized registers).
1710 const auto *CI = dyn_cast<CmpInst>(Cond);
1711 if (CI && (CI->getParent() == I->getParent())) {
1712 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
1714 // FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction.
1715 static unsigned SETFOpcTable[2][3] = {
1716 { X86::SETNPr, X86::SETEr , X86::TEST8rr },
1717 { X86::SETPr, X86::SETNEr, X86::OR8rr }
1719 unsigned *SETFOpc = nullptr;
1720 switch (Predicate) {
1722 case CmpInst::FCMP_OEQ:
1723 SETFOpc = &SETFOpcTable[0][0];
1724 Predicate = CmpInst::ICMP_NE;
1726 case CmpInst::FCMP_UNE:
1727 SETFOpc = &SETFOpcTable[1][0];
1728 Predicate = CmpInst::ICMP_NE;
1733 std::tie(CC, NeedSwap) = getX86ConditionCode(Predicate);
1734 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
1736 const Value *CmpLHS = CI->getOperand(0);
1737 const Value *CmpRHS = CI->getOperand(1);
1739 std::swap(CmpLHS, CmpRHS);
1741 EVT CmpVT = TLI.getValueType(CmpLHS->getType());
1742 // Emit a compare of the LHS and RHS, setting the flags.
1743 if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT))
1747 unsigned FlagReg1 = createResultReg(&X86::GR8RegClass);
1748 unsigned FlagReg2 = createResultReg(&X86::GR8RegClass);
1749 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[0]),
1751 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[1]),
1753 auto const &II = TII.get(SETFOpc[2]);
1754 if (II.getNumDefs()) {
1755 unsigned TmpReg = createResultReg(&X86::GR8RegClass);
1756 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, TmpReg)
1757 .addReg(FlagReg2).addReg(FlagReg1);
1759 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1760 .addReg(FlagReg2).addReg(FlagReg1);
1764 } else if (foldX86XALUIntrinsic(CC, I, Cond)) {
1765 // Fake request the condition, otherwise the intrinsic might be completely
1767 unsigned TmpReg = getRegForValue(Cond);
1775 // Selects operate on i1, however, CondReg is 8 bits width and may contain
1776 // garbage. Indeed, only the less significant bit is supposed to be
1777 // accurate. If we read more than the lsb, we may see non-zero values
1778 // whereas lsb is zero. Therefore, we have to truncate Op0Reg to i1 for
1779 // the select. This is achieved by performing TEST against 1.
1780 unsigned CondReg = getRegForValue(Cond);
1783 bool CondIsKill = hasTrivialKill(Cond);
1785 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
1786 .addReg(CondReg, getKillRegState(CondIsKill)).addImm(1);
1789 const Value *LHS = I->getOperand(1);
1790 const Value *RHS = I->getOperand(2);
1792 unsigned RHSReg = getRegForValue(RHS);
1793 bool RHSIsKill = hasTrivialKill(RHS);
1795 unsigned LHSReg = getRegForValue(LHS);
1796 bool LHSIsKill = hasTrivialKill(LHS);
1798 if (!LHSReg || !RHSReg)
1801 unsigned Opc = X86::getCMovFromCond(CC, RC->getSize());
1802 unsigned ResultReg = fastEmitInst_rr(Opc, RC, RHSReg, RHSIsKill,
1804 updateValueMap(I, ResultReg);
1808 /// \brief Emit SSE instructions to lower the select.
1810 /// Try to use SSE1/SSE2 instructions to simulate a select without branches.
1811 /// This lowers fp selects into a CMP/AND/ANDN/OR sequence when the necessary
1812 /// SSE instructions are available.
1813 bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) {
1814 // Optimize conditions coming from a compare if both instructions are in the
1815 // same basic block (values defined in other basic blocks may not have
1816 // initialized registers).
1817 const auto *CI = dyn_cast<FCmpInst>(I->getOperand(0));
1818 if (!CI || (CI->getParent() != I->getParent()))
1821 if (I->getType() != CI->getOperand(0)->getType() ||
1822 !((Subtarget->hasSSE1() && RetVT == MVT::f32) ||
1823 (Subtarget->hasSSE2() && RetVT == MVT::f64)))
1826 const Value *CmpLHS = CI->getOperand(0);
1827 const Value *CmpRHS = CI->getOperand(1);
1828 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
1830 // The optimizer might have replaced fcmp oeq %x, %x with fcmp ord %x, 0.0.
1831 // We don't have to materialize a zero constant for this case and can just use
1832 // %x again on the RHS.
1833 if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) {
1834 const auto *CmpRHSC = dyn_cast<ConstantFP>(CmpRHS);
1835 if (CmpRHSC && CmpRHSC->isNullValue())
1841 std::tie(CC, NeedSwap) = getX86SSEConditionCode(Predicate);
1846 std::swap(CmpLHS, CmpRHS);
1848 static unsigned OpcTable[2][2][4] = {
1849 { { X86::CMPSSrr, X86::FsANDPSrr, X86::FsANDNPSrr, X86::FsORPSrr },
1850 { X86::VCMPSSrr, X86::VFsANDPSrr, X86::VFsANDNPSrr, X86::VFsORPSrr } },
1851 { { X86::CMPSDrr, X86::FsANDPDrr, X86::FsANDNPDrr, X86::FsORPDrr },
1852 { X86::VCMPSDrr, X86::VFsANDPDrr, X86::VFsANDNPDrr, X86::VFsORPDrr } }
1855 bool HasAVX = Subtarget->hasAVX();
1856 unsigned *Opc = nullptr;
1857 switch (RetVT.SimpleTy) {
1858 default: return false;
1859 case MVT::f32: Opc = &OpcTable[0][HasAVX][0]; break;
1860 case MVT::f64: Opc = &OpcTable[1][HasAVX][0]; break;
1863 const Value *LHS = I->getOperand(1);
1864 const Value *RHS = I->getOperand(2);
1866 unsigned LHSReg = getRegForValue(LHS);
1867 bool LHSIsKill = hasTrivialKill(LHS);
1869 unsigned RHSReg = getRegForValue(RHS);
1870 bool RHSIsKill = hasTrivialKill(RHS);
1872 unsigned CmpLHSReg = getRegForValue(CmpLHS);
1873 bool CmpLHSIsKill = hasTrivialKill(CmpLHS);
1875 unsigned CmpRHSReg = getRegForValue(CmpRHS);
1876 bool CmpRHSIsKill = hasTrivialKill(CmpRHS);
1878 if (!LHSReg || !RHSReg || !CmpLHS || !CmpRHS)
1881 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
1882 unsigned CmpReg = fastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpLHSIsKill,
1883 CmpRHSReg, CmpRHSIsKill, CC);
1884 unsigned AndReg = fastEmitInst_rr(Opc[1], RC, CmpReg, /*IsKill=*/false,
1886 unsigned AndNReg = fastEmitInst_rr(Opc[2], RC, CmpReg, /*IsKill=*/true,
1888 unsigned ResultReg = fastEmitInst_rr(Opc[3], RC, AndNReg, /*IsKill=*/true,
1889 AndReg, /*IsKill=*/true);
1890 updateValueMap(I, ResultReg);
1894 bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) {
1895 // These are pseudo CMOV instructions and will be later expanded into control-
1898 switch (RetVT.SimpleTy) {
1899 default: return false;
1900 case MVT::i8: Opc = X86::CMOV_GR8; break;
1901 case MVT::i16: Opc = X86::CMOV_GR16; break;
1902 case MVT::i32: Opc = X86::CMOV_GR32; break;
1903 case MVT::f32: Opc = X86::CMOV_FR32; break;
1904 case MVT::f64: Opc = X86::CMOV_FR64; break;
1907 const Value *Cond = I->getOperand(0);
1908 X86::CondCode CC = X86::COND_NE;
1910 // Optimize conditions coming from a compare if both instructions are in the
1911 // same basic block (values defined in other basic blocks may not have
1912 // initialized registers).
1913 const auto *CI = dyn_cast<CmpInst>(Cond);
1914 if (CI && (CI->getParent() == I->getParent())) {
1916 std::tie(CC, NeedSwap) = getX86ConditionCode(CI->getPredicate());
1917 if (CC > X86::LAST_VALID_COND)
1920 const Value *CmpLHS = CI->getOperand(0);
1921 const Value *CmpRHS = CI->getOperand(1);
1924 std::swap(CmpLHS, CmpRHS);
1926 EVT CmpVT = TLI.getValueType(CmpLHS->getType());
1927 if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT))
1930 unsigned CondReg = getRegForValue(Cond);
1933 bool CondIsKill = hasTrivialKill(Cond);
1934 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
1935 .addReg(CondReg, getKillRegState(CondIsKill)).addImm(1);
1938 const Value *LHS = I->getOperand(1);
1939 const Value *RHS = I->getOperand(2);
1941 unsigned LHSReg = getRegForValue(LHS);
1942 bool LHSIsKill = hasTrivialKill(LHS);
1944 unsigned RHSReg = getRegForValue(RHS);
1945 bool RHSIsKill = hasTrivialKill(RHS);
1947 if (!LHSReg || !RHSReg)
1950 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
1952 unsigned ResultReg =
1953 fastEmitInst_rri(Opc, RC, RHSReg, RHSIsKill, LHSReg, LHSIsKill, CC);
1954 updateValueMap(I, ResultReg);
1958 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1960 if (!isTypeLegal(I->getType(), RetVT))
1963 // Check if we can fold the select.
1964 if (const auto *CI = dyn_cast<CmpInst>(I->getOperand(0))) {
1965 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
1966 const Value *Opnd = nullptr;
1967 switch (Predicate) {
1969 case CmpInst::FCMP_FALSE: Opnd = I->getOperand(2); break;
1970 case CmpInst::FCMP_TRUE: Opnd = I->getOperand(1); break;
1972 // No need for a select anymore - this is an unconditional move.
1974 unsigned OpReg = getRegForValue(Opnd);
1977 bool OpIsKill = hasTrivialKill(Opnd);
1978 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
1979 unsigned ResultReg = createResultReg(RC);
1980 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1981 TII.get(TargetOpcode::COPY), ResultReg)
1982 .addReg(OpReg, getKillRegState(OpIsKill));
1983 updateValueMap(I, ResultReg);
1988 // First try to use real conditional move instructions.
1989 if (X86FastEmitCMoveSelect(RetVT, I))
1992 // Try to use a sequence of SSE instructions to simulate a conditional move.
1993 if (X86FastEmitSSESelect(RetVT, I))
1996 // Fall-back to pseudo conditional move instructions, which will be later
1997 // converted to control-flow.
1998 if (X86FastEmitPseudoSelect(RetVT, I))
2004 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
2005 // fpext from float to double.
2006 if (X86ScalarSSEf64 &&
2007 I->getType()->isDoubleTy()) {
2008 const Value *V = I->getOperand(0);
2009 if (V->getType()->isFloatTy()) {
2010 unsigned OpReg = getRegForValue(V);
2011 if (OpReg == 0) return false;
2012 unsigned ResultReg = createResultReg(&X86::FR64RegClass);
2013 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2014 TII.get(X86::CVTSS2SDrr), ResultReg)
2016 updateValueMap(I, ResultReg);
2024 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
2025 if (X86ScalarSSEf64) {
2026 if (I->getType()->isFloatTy()) {
2027 const Value *V = I->getOperand(0);
2028 if (V->getType()->isDoubleTy()) {
2029 unsigned OpReg = getRegForValue(V);
2030 if (OpReg == 0) return false;
2031 unsigned ResultReg = createResultReg(&X86::FR32RegClass);
2032 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2033 TII.get(X86::CVTSD2SSrr), ResultReg)
2035 updateValueMap(I, ResultReg);
2044 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
2045 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
2046 EVT DstVT = TLI.getValueType(I->getType());
2048 // This code only handles truncation to byte.
2049 if (DstVT != MVT::i8 && DstVT != MVT::i1)
2051 if (!TLI.isTypeLegal(SrcVT))
2054 unsigned InputReg = getRegForValue(I->getOperand(0));
2056 // Unhandled operand. Halt "fast" selection and bail.
2059 if (SrcVT == MVT::i8) {
2060 // Truncate from i8 to i1; no code needed.
2061 updateValueMap(I, InputReg);
2065 if (!Subtarget->is64Bit()) {
2066 // If we're on x86-32; we can't extract an i8 from a general register.
2067 // First issue a copy to GR16_ABCD or GR32_ABCD.
2068 const TargetRegisterClass *CopyRC =
2069 (SrcVT == MVT::i16) ? &X86::GR16_ABCDRegClass : &X86::GR32_ABCDRegClass;
2070 unsigned CopyReg = createResultReg(CopyRC);
2071 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2072 TII.get(TargetOpcode::COPY), CopyReg).addReg(InputReg);
2076 // Issue an extract_subreg.
2077 unsigned ResultReg = fastEmitInst_extractsubreg(MVT::i8,
2078 InputReg, /*Kill=*/true,
2083 updateValueMap(I, ResultReg);
2087 bool X86FastISel::IsMemcpySmall(uint64_t Len) {
2088 return Len <= (Subtarget->is64Bit() ? 32 : 16);
2091 bool X86FastISel::TryEmitSmallMemcpy(X86AddressMode DestAM,
2092 X86AddressMode SrcAM, uint64_t Len) {
2094 // Make sure we don't bloat code by inlining very large memcpy's.
2095 if (!IsMemcpySmall(Len))
2098 bool i64Legal = Subtarget->is64Bit();
2100 // We don't care about alignment here since we just emit integer accesses.
2103 if (Len >= 8 && i64Legal)
2113 bool RV = X86FastEmitLoad(VT, SrcAM, nullptr, Reg);
2114 RV &= X86FastEmitStore(VT, Reg, /*Kill=*/true, DestAM);
2115 assert(RV && "Failed to emit load or store??");
2117 unsigned Size = VT.getSizeInBits()/8;
2119 DestAM.Disp += Size;
2126 bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
2127 // FIXME: Handle more intrinsics.
2128 switch (II->getIntrinsicID()) {
2129 default: return false;
2130 case Intrinsic::frameaddress: {
2131 Type *RetTy = II->getCalledFunction()->getReturnType();
2134 if (!isTypeLegal(RetTy, VT))
2138 const TargetRegisterClass *RC = nullptr;
2140 switch (VT.SimpleTy) {
2141 default: llvm_unreachable("Invalid result type for frameaddress.");
2142 case MVT::i32: Opc = X86::MOV32rm; RC = &X86::GR32RegClass; break;
2143 case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break;
2146 // This needs to be set before we call getPtrSizedFrameRegister, otherwise
2147 // we get the wrong frame register.
2148 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2149 MFI->setFrameAddressIsTaken(true);
2151 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2152 TM.getSubtargetImpl()->getRegisterInfo());
2153 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(*(FuncInfo.MF));
2154 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
2155 (FrameReg == X86::EBP && VT == MVT::i32)) &&
2156 "Invalid Frame Register!");
2158 // Always make a copy of the frame register to to a vreg first, so that we
2159 // never directly reference the frame register (the TwoAddressInstruction-
2160 // Pass doesn't like that).
2161 unsigned SrcReg = createResultReg(RC);
2162 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2163 TII.get(TargetOpcode::COPY), SrcReg).addReg(FrameReg);
2165 // Now recursively load from the frame address.
2166 // movq (%rbp), %rax
2167 // movq (%rax), %rax
2168 // movq (%rax), %rax
2171 unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
2173 DestReg = createResultReg(RC);
2174 addDirectMem(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2175 TII.get(Opc), DestReg), SrcReg);
2179 updateValueMap(II, SrcReg);
2182 case Intrinsic::memcpy: {
2183 const MemCpyInst *MCI = cast<MemCpyInst>(II);
2184 // Don't handle volatile or variable length memcpys.
2185 if (MCI->isVolatile())
2188 if (isa<ConstantInt>(MCI->getLength())) {
2189 // Small memcpy's are common enough that we want to do them
2190 // without a call if possible.
2191 uint64_t Len = cast<ConstantInt>(MCI->getLength())->getZExtValue();
2192 if (IsMemcpySmall(Len)) {
2193 X86AddressMode DestAM, SrcAM;
2194 if (!X86SelectAddress(MCI->getRawDest(), DestAM) ||
2195 !X86SelectAddress(MCI->getRawSource(), SrcAM))
2197 TryEmitSmallMemcpy(DestAM, SrcAM, Len);
2202 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32;
2203 if (!MCI->getLength()->getType()->isIntegerTy(SizeWidth))
2206 if (MCI->getSourceAddressSpace() > 255 || MCI->getDestAddressSpace() > 255)
2209 return lowerCallTo(II, "memcpy", II->getNumArgOperands() - 2);
2211 case Intrinsic::memset: {
2212 const MemSetInst *MSI = cast<MemSetInst>(II);
2214 if (MSI->isVolatile())
2217 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32;
2218 if (!MSI->getLength()->getType()->isIntegerTy(SizeWidth))
2221 if (MSI->getDestAddressSpace() > 255)
2224 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
2226 case Intrinsic::stackprotector: {
2227 // Emit code to store the stack guard onto the stack.
2228 EVT PtrTy = TLI.getPointerTy();
2230 const Value *Op1 = II->getArgOperand(0); // The guard's value.
2231 const AllocaInst *Slot = cast<AllocaInst>(II->getArgOperand(1));
2233 MFI.setStackProtectorIndex(FuncInfo.StaticAllocaMap[Slot]);
2235 // Grab the frame index.
2237 if (!X86SelectAddress(Slot, AM)) return false;
2238 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
2241 case Intrinsic::dbg_declare: {
2242 const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
2244 assert(DI->getAddress() && "Null address should be checked earlier!");
2245 if (!X86SelectAddress(DI->getAddress(), AM))
2247 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
2248 // FIXME may need to add RegState::Debug to any registers produced,
2249 // although ESP/EBP should be the only ones at the moment.
2250 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II), AM)
2252 .addMetadata(DI->getVariable())
2253 .addMetadata(DI->getExpression());
2256 case Intrinsic::trap: {
2257 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TRAP));
2260 case Intrinsic::sqrt: {
2261 if (!Subtarget->hasSSE1())
2264 Type *RetTy = II->getCalledFunction()->getReturnType();
2267 if (!isTypeLegal(RetTy, VT))
2270 // Unfortunately we can't use fastEmit_r, because the AVX version of FSQRT
2271 // is not generated by FastISel yet.
2272 // FIXME: Update this code once tablegen can handle it.
2273 static const unsigned SqrtOpc[2][2] = {
2274 {X86::SQRTSSr, X86::VSQRTSSr},
2275 {X86::SQRTSDr, X86::VSQRTSDr}
2277 bool HasAVX = Subtarget->hasAVX();
2279 const TargetRegisterClass *RC;
2280 switch (VT.SimpleTy) {
2281 default: return false;
2282 case MVT::f32: Opc = SqrtOpc[0][HasAVX]; RC = &X86::FR32RegClass; break;
2283 case MVT::f64: Opc = SqrtOpc[1][HasAVX]; RC = &X86::FR64RegClass; break;
2286 const Value *SrcVal = II->getArgOperand(0);
2287 unsigned SrcReg = getRegForValue(SrcVal);
2292 unsigned ImplicitDefReg = 0;
2294 ImplicitDefReg = createResultReg(RC);
2295 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2296 TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
2299 unsigned ResultReg = createResultReg(RC);
2300 MachineInstrBuilder MIB;
2301 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
2305 MIB.addReg(ImplicitDefReg);
2309 updateValueMap(II, ResultReg);
2312 case Intrinsic::sadd_with_overflow:
2313 case Intrinsic::uadd_with_overflow:
2314 case Intrinsic::ssub_with_overflow:
2315 case Intrinsic::usub_with_overflow:
2316 case Intrinsic::smul_with_overflow:
2317 case Intrinsic::umul_with_overflow: {
2318 // This implements the basic lowering of the xalu with overflow intrinsics
2319 // into add/sub/mul followed by either seto or setb.
2320 const Function *Callee = II->getCalledFunction();
2321 auto *Ty = cast<StructType>(Callee->getReturnType());
2322 Type *RetTy = Ty->getTypeAtIndex(0U);
2323 Type *CondTy = Ty->getTypeAtIndex(1);
2326 if (!isTypeLegal(RetTy, VT))
2329 if (VT < MVT::i8 || VT > MVT::i64)
2332 const Value *LHS = II->getArgOperand(0);
2333 const Value *RHS = II->getArgOperand(1);
2335 // Canonicalize immediate to the RHS.
2336 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
2337 isCommutativeIntrinsic(II))
2338 std::swap(LHS, RHS);
2340 bool UseIncDec = false;
2341 if (isa<ConstantInt>(RHS) && cast<ConstantInt>(RHS)->isOne())
2344 unsigned BaseOpc, CondOpc;
2345 switch (II->getIntrinsicID()) {
2346 default: llvm_unreachable("Unexpected intrinsic!");
2347 case Intrinsic::sadd_with_overflow:
2348 BaseOpc = UseIncDec ? unsigned(X86ISD::INC) : unsigned(ISD::ADD);
2349 CondOpc = X86::SETOr;
2351 case Intrinsic::uadd_with_overflow:
2352 BaseOpc = ISD::ADD; CondOpc = X86::SETBr; break;
2353 case Intrinsic::ssub_with_overflow:
2354 BaseOpc = UseIncDec ? unsigned(X86ISD::DEC) : unsigned(ISD::SUB);
2355 CondOpc = X86::SETOr;
2357 case Intrinsic::usub_with_overflow:
2358 BaseOpc = ISD::SUB; CondOpc = X86::SETBr; break;
2359 case Intrinsic::smul_with_overflow:
2360 BaseOpc = X86ISD::SMUL; CondOpc = X86::SETOr; break;
2361 case Intrinsic::umul_with_overflow:
2362 BaseOpc = X86ISD::UMUL; CondOpc = X86::SETOr; break;
2365 unsigned LHSReg = getRegForValue(LHS);
2368 bool LHSIsKill = hasTrivialKill(LHS);
2370 unsigned ResultReg = 0;
2371 // Check if we have an immediate version.
2372 if (const auto *CI = dyn_cast<ConstantInt>(RHS)) {
2373 static const unsigned Opc[2][2][4] = {
2374 { { X86::INC8r, X86::INC16r, X86::INC32r, X86::INC64r },
2375 { X86::DEC8r, X86::DEC16r, X86::DEC32r, X86::DEC64r } },
2376 { { X86::INC8r, X86::INC64_16r, X86::INC64_32r, X86::INC64r },
2377 { X86::DEC8r, X86::DEC64_16r, X86::DEC64_32r, X86::DEC64r } }
2380 if (BaseOpc == X86ISD::INC || BaseOpc == X86ISD::DEC) {
2381 ResultReg = createResultReg(TLI.getRegClassFor(VT));
2382 bool Is64Bit = Subtarget->is64Bit();
2383 bool IsDec = BaseOpc == X86ISD::DEC;
2384 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2385 TII.get(Opc[Is64Bit][IsDec][VT.SimpleTy-MVT::i8]), ResultReg)
2386 .addReg(LHSReg, getKillRegState(LHSIsKill));
2388 ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, LHSIsKill,
2389 CI->getZExtValue());
2395 RHSReg = getRegForValue(RHS);
2398 RHSIsKill = hasTrivialKill(RHS);
2399 ResultReg = fastEmit_rr(VT, VT, BaseOpc, LHSReg, LHSIsKill, RHSReg,
2403 // FastISel doesn't have a pattern for all X86::MUL*r and X86::IMUL*r. Emit
2405 if (BaseOpc == X86ISD::UMUL && !ResultReg) {
2406 static const unsigned MULOpc[] =
2407 { X86::MUL8r, X86::MUL16r, X86::MUL32r, X86::MUL64r };
2408 static const unsigned Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX };
2409 // First copy the first operand into RAX, which is an implicit input to
2410 // the X86::MUL*r instruction.
2411 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2412 TII.get(TargetOpcode::COPY), Reg[VT.SimpleTy-MVT::i8])
2413 .addReg(LHSReg, getKillRegState(LHSIsKill));
2414 ResultReg = fastEmitInst_r(MULOpc[VT.SimpleTy-MVT::i8],
2415 TLI.getRegClassFor(VT), RHSReg, RHSIsKill);
2416 } else if (BaseOpc == X86ISD::SMUL && !ResultReg) {
2417 static const unsigned MULOpc[] =
2418 { X86::IMUL8r, X86::IMUL16rr, X86::IMUL32rr, X86::IMUL64rr };
2419 if (VT == MVT::i8) {
2420 // Copy the first operand into AL, which is an implicit input to the
2421 // X86::IMUL8r instruction.
2422 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2423 TII.get(TargetOpcode::COPY), X86::AL)
2424 .addReg(LHSReg, getKillRegState(LHSIsKill));
2425 ResultReg = fastEmitInst_r(MULOpc[0], TLI.getRegClassFor(VT), RHSReg,
2428 ResultReg = fastEmitInst_rr(MULOpc[VT.SimpleTy-MVT::i8],
2429 TLI.getRegClassFor(VT), LHSReg, LHSIsKill,
2436 unsigned ResultReg2 = FuncInfo.CreateRegs(CondTy);
2437 assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
2438 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CondOpc),
2441 updateValueMap(II, ResultReg, 2);
2444 case Intrinsic::x86_sse_cvttss2si:
2445 case Intrinsic::x86_sse_cvttss2si64:
2446 case Intrinsic::x86_sse2_cvttsd2si:
2447 case Intrinsic::x86_sse2_cvttsd2si64: {
2449 switch (II->getIntrinsicID()) {
2450 default: llvm_unreachable("Unexpected intrinsic.");
2451 case Intrinsic::x86_sse_cvttss2si:
2452 case Intrinsic::x86_sse_cvttss2si64:
2453 if (!Subtarget->hasSSE1())
2455 IsInputDouble = false;
2457 case Intrinsic::x86_sse2_cvttsd2si:
2458 case Intrinsic::x86_sse2_cvttsd2si64:
2459 if (!Subtarget->hasSSE2())
2461 IsInputDouble = true;
2465 Type *RetTy = II->getCalledFunction()->getReturnType();
2467 if (!isTypeLegal(RetTy, VT))
2470 static const unsigned CvtOpc[2][2][2] = {
2471 { { X86::CVTTSS2SIrr, X86::VCVTTSS2SIrr },
2472 { X86::CVTTSS2SI64rr, X86::VCVTTSS2SI64rr } },
2473 { { X86::CVTTSD2SIrr, X86::VCVTTSD2SIrr },
2474 { X86::CVTTSD2SI64rr, X86::VCVTTSD2SI64rr } }
2476 bool HasAVX = Subtarget->hasAVX();
2478 switch (VT.SimpleTy) {
2479 default: llvm_unreachable("Unexpected result type.");
2480 case MVT::i32: Opc = CvtOpc[IsInputDouble][0][HasAVX]; break;
2481 case MVT::i64: Opc = CvtOpc[IsInputDouble][1][HasAVX]; break;
2484 // Check if we can fold insertelement instructions into the convert.
2485 const Value *Op = II->getArgOperand(0);
2486 while (auto *IE = dyn_cast<InsertElementInst>(Op)) {
2487 const Value *Index = IE->getOperand(2);
2488 if (!isa<ConstantInt>(Index))
2490 unsigned Idx = cast<ConstantInt>(Index)->getZExtValue();
2493 Op = IE->getOperand(1);
2496 Op = IE->getOperand(0);
2499 unsigned Reg = getRegForValue(Op);
2503 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
2504 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
2507 updateValueMap(II, ResultReg);
2513 bool X86FastISel::fastLowerArguments() {
2514 if (!FuncInfo.CanLowerReturn)
2517 const Function *F = FuncInfo.Fn;
2521 CallingConv::ID CC = F->getCallingConv();
2522 if (CC != CallingConv::C)
2525 if (Subtarget->isCallingConvWin64(CC))
2528 if (!Subtarget->is64Bit())
2531 // Only handle simple cases. i.e. Up to 6 i32/i64 scalar arguments.
2532 unsigned GPRCnt = 0;
2533 unsigned FPRCnt = 0;
2535 for (auto const &Arg : F->args()) {
2536 // The first argument is at index 1.
2538 if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
2539 F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
2540 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
2541 F->getAttributes().hasAttribute(Idx, Attribute::Nest))
2544 Type *ArgTy = Arg.getType();
2545 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
2548 EVT ArgVT = TLI.getValueType(ArgTy);
2549 if (!ArgVT.isSimple()) return false;
2550 switch (ArgVT.getSimpleVT().SimpleTy) {
2551 default: return false;
2558 if (!Subtarget->hasSSE1())
2571 static const MCPhysReg GPR32ArgRegs[] = {
2572 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
2574 static const MCPhysReg GPR64ArgRegs[] = {
2575 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
2577 static const MCPhysReg XMMArgRegs[] = {
2578 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2579 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2582 unsigned GPRIdx = 0;
2583 unsigned FPRIdx = 0;
2584 for (auto const &Arg : F->args()) {
2585 MVT VT = TLI.getSimpleValueType(Arg.getType());
2586 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
2588 switch (VT.SimpleTy) {
2589 default: llvm_unreachable("Unexpected value type.");
2590 case MVT::i32: SrcReg = GPR32ArgRegs[GPRIdx++]; break;
2591 case MVT::i64: SrcReg = GPR64ArgRegs[GPRIdx++]; break;
2592 case MVT::f32: // fall-through
2593 case MVT::f64: SrcReg = XMMArgRegs[FPRIdx++]; break;
2595 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
2596 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
2597 // Without this, EmitLiveInCopies may eliminate the livein if its only
2598 // use is a bitcast (which isn't turned into an instruction).
2599 unsigned ResultReg = createResultReg(RC);
2600 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2601 TII.get(TargetOpcode::COPY), ResultReg)
2602 .addReg(DstReg, getKillRegState(true));
2603 updateValueMap(&Arg, ResultReg);
2608 static unsigned computeBytesPoppedByCallee(const X86Subtarget *Subtarget,
2610 ImmutableCallSite *CS) {
2611 if (Subtarget->is64Bit())
2613 if (Subtarget->getTargetTriple().isOSMSVCRT())
2615 if (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2616 CC == CallingConv::HiPE)
2618 if (CS && !CS->paramHasAttr(1, Attribute::StructRet))
2620 if (CS && CS->paramHasAttr(1, Attribute::InReg))
2625 bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
2626 auto &OutVals = CLI.OutVals;
2627 auto &OutFlags = CLI.OutFlags;
2628 auto &OutRegs = CLI.OutRegs;
2629 auto &Ins = CLI.Ins;
2630 auto &InRegs = CLI.InRegs;
2631 CallingConv::ID CC = CLI.CallConv;
2632 bool &IsTailCall = CLI.IsTailCall;
2633 bool IsVarArg = CLI.IsVarArg;
2634 const Value *Callee = CLI.Callee;
2635 const char *SymName = CLI.SymName;
2637 bool Is64Bit = Subtarget->is64Bit();
2638 bool IsWin64 = Subtarget->isCallingConvWin64(CC);
2640 // Handle only C, fastcc, and webkit_js calling conventions for now.
2642 default: return false;
2643 case CallingConv::C:
2644 case CallingConv::Fast:
2645 case CallingConv::WebKit_JS:
2646 case CallingConv::X86_FastCall:
2647 case CallingConv::X86_64_Win64:
2648 case CallingConv::X86_64_SysV:
2652 // Allow SelectionDAG isel to handle tail calls.
2656 // fastcc with -tailcallopt is intended to provide a guaranteed
2657 // tail call optimization. Fastisel doesn't know how to do that.
2658 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt)
2661 // Don't know how to handle Win64 varargs yet. Nothing special needed for
2662 // x86-32. Special handling for x86-64 is implemented.
2663 if (IsVarArg && IsWin64)
2666 // Don't know about inalloca yet.
2667 if (CLI.CS && CLI.CS->hasInAllocaArgument())
2670 // Fast-isel doesn't know about callee-pop yet.
2671 if (X86::isCalleePop(CC, Subtarget->is64Bit(), IsVarArg,
2672 TM.Options.GuaranteedTailCallOpt))
2675 SmallVector<MVT, 16> OutVTs;
2676 SmallVector<unsigned, 16> ArgRegs;
2678 // If this is a constant i1/i8/i16 argument, promote to i32 to avoid an extra
2679 // instruction. This is safe because it is common to all FastISel supported
2680 // calling conventions on x86.
2681 for (int i = 0, e = OutVals.size(); i != e; ++i) {
2682 Value *&Val = OutVals[i];
2683 ISD::ArgFlagsTy Flags = OutFlags[i];
2684 if (auto *CI = dyn_cast<ConstantInt>(Val)) {
2685 if (CI->getBitWidth() < 32) {
2687 Val = ConstantExpr::getSExt(CI, Type::getInt32Ty(CI->getContext()));
2689 Val = ConstantExpr::getZExt(CI, Type::getInt32Ty(CI->getContext()));
2693 // Passing bools around ends up doing a trunc to i1 and passing it.
2694 // Codegen this as an argument + "and 1".
2696 auto *TI = dyn_cast<TruncInst>(Val);
2698 if (TI && TI->getType()->isIntegerTy(1) && CLI.CS &&
2699 (TI->getParent() == CLI.CS->getInstruction()->getParent()) &&
2701 Value *PrevVal = TI->getOperand(0);
2702 ResultReg = getRegForValue(PrevVal);
2707 if (!isTypeLegal(PrevVal->getType(), VT))
2711 fastEmit_ri(VT, VT, ISD::AND, ResultReg, hasTrivialKill(PrevVal), 1);
2713 if (!isTypeLegal(Val->getType(), VT))
2715 ResultReg = getRegForValue(Val);
2721 ArgRegs.push_back(ResultReg);
2722 OutVTs.push_back(VT);
2725 // Analyze operands of the call, assigning locations to each operand.
2726 SmallVector<CCValAssign, 16> ArgLocs;
2727 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, CLI.RetTy->getContext());
2729 // Allocate shadow area for Win64
2731 CCInfo.AllocateStack(32, 8);
2733 CCInfo.AnalyzeCallOperands(OutVTs, OutFlags, CC_X86);
2735 // Get a count of how many bytes are to be pushed on the stack.
2736 unsigned NumBytes = CCInfo.getNextStackOffset();
2738 // Issue CALLSEQ_START
2739 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2740 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
2743 // Walk the register/memloc assignments, inserting copies/loads.
2744 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2745 TM.getSubtargetImpl()->getRegisterInfo());
2746 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2747 CCValAssign const &VA = ArgLocs[i];
2748 const Value *ArgVal = OutVals[VA.getValNo()];
2749 MVT ArgVT = OutVTs[VA.getValNo()];
2751 if (ArgVT == MVT::x86mmx)
2754 unsigned ArgReg = ArgRegs[VA.getValNo()];
2756 // Promote the value if needed.
2757 switch (VA.getLocInfo()) {
2758 case CCValAssign::Full: break;
2759 case CCValAssign::SExt: {
2760 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
2761 "Unexpected extend");
2762 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg,
2764 assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
2765 ArgVT = VA.getLocVT();
2768 case CCValAssign::ZExt: {
2769 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
2770 "Unexpected extend");
2771 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg,
2773 assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
2774 ArgVT = VA.getLocVT();
2777 case CCValAssign::AExt: {
2778 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
2779 "Unexpected extend");
2780 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg,
2783 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg,
2786 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg,
2789 assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
2790 ArgVT = VA.getLocVT();
2793 case CCValAssign::BCvt: {
2794 ArgReg = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, ArgReg,
2795 /*TODO: Kill=*/false);
2796 assert(ArgReg && "Failed to emit a bitcast!");
2797 ArgVT = VA.getLocVT();
2800 case CCValAssign::VExt:
2801 // VExt has not been implemented, so this should be impossible to reach
2802 // for now. However, fallback to Selection DAG isel once implemented.
2804 case CCValAssign::AExtUpper:
2805 case CCValAssign::SExtUpper:
2806 case CCValAssign::ZExtUpper:
2807 case CCValAssign::FPExt:
2808 llvm_unreachable("Unexpected loc info!");
2809 case CCValAssign::Indirect:
2810 // FIXME: Indirect doesn't need extending, but fast-isel doesn't fully
2815 if (VA.isRegLoc()) {
2816 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2817 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
2818 OutRegs.push_back(VA.getLocReg());
2820 assert(VA.isMemLoc());
2822 // Don't emit stores for undef values.
2823 if (isa<UndefValue>(ArgVal))
2826 unsigned LocMemOffset = VA.getLocMemOffset();
2828 AM.Base.Reg = RegInfo->getStackRegister();
2829 AM.Disp = LocMemOffset;
2830 ISD::ArgFlagsTy Flags = OutFlags[VA.getValNo()];
2831 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
2832 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2833 MachinePointerInfo::getStack(LocMemOffset), MachineMemOperand::MOStore,
2834 ArgVT.getStoreSize(), Alignment);
2835 if (Flags.isByVal()) {
2836 X86AddressMode SrcAM;
2837 SrcAM.Base.Reg = ArgReg;
2838 if (!TryEmitSmallMemcpy(AM, SrcAM, Flags.getByValSize()))
2840 } else if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) {
2841 // If this is a really simple value, emit this with the Value* version
2842 // of X86FastEmitStore. If it isn't simple, we don't want to do this,
2843 // as it can cause us to reevaluate the argument.
2844 if (!X86FastEmitStore(ArgVT, ArgVal, AM, MMO))
2847 bool ValIsKill = hasTrivialKill(ArgVal);
2848 if (!X86FastEmitStore(ArgVT, ArgReg, ValIsKill, AM, MMO))
2854 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2856 if (Subtarget->isPICStyleGOT()) {
2857 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
2858 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2859 TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
2862 if (Is64Bit && IsVarArg && !IsWin64) {
2863 // From AMD64 ABI document:
2864 // For calls that may call functions that use varargs or stdargs
2865 // (prototype-less calls or calls to functions containing ellipsis (...) in
2866 // the declaration) %al is used as hidden argument to specify the number
2867 // of SSE registers used. The contents of %al do not need to match exactly
2868 // the number of registers, but must be an ubound on the number of SSE
2869 // registers used and is in the range 0 - 8 inclusive.
2871 // Count the number of XMM registers allocated.
2872 static const MCPhysReg XMMArgRegs[] = {
2873 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2874 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2876 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2877 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2878 && "SSE registers cannot be used when SSE is disabled");
2879 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
2880 X86::AL).addImm(NumXMMRegs);
2883 // Materialize callee address in a register. FIXME: GV address can be
2884 // handled with a CALLpcrel32 instead.
2885 X86AddressMode CalleeAM;
2886 if (!X86SelectCallAddress(Callee, CalleeAM))
2889 unsigned CalleeOp = 0;
2890 const GlobalValue *GV = nullptr;
2891 if (CalleeAM.GV != nullptr) {
2893 } else if (CalleeAM.Base.Reg != 0) {
2894 CalleeOp = CalleeAM.Base.Reg;
2899 MachineInstrBuilder MIB;
2901 // Register-indirect call.
2902 unsigned CallOpc = Is64Bit ? X86::CALL64r : X86::CALL32r;
2903 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc))
2907 assert(GV && "Not a direct call");
2908 unsigned CallOpc = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32;
2910 // See if we need any target-specific flags on the GV operand.
2911 unsigned char OpFlags = 0;
2913 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2914 // external symbols most go through the PLT in PIC mode. If the symbol
2915 // has hidden or protected visibility, or if it is static or local, then
2916 // we don't need to use the PLT - we can directly call it.
2917 if (Subtarget->isTargetELF() &&
2918 TM.getRelocationModel() == Reloc::PIC_ &&
2919 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2920 OpFlags = X86II::MO_PLT;
2921 } else if (Subtarget->isPICStyleStubAny() &&
2922 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2923 (!Subtarget->getTargetTriple().isMacOSX() ||
2924 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2925 // PC-relative references to external symbols should go through $stub,
2926 // unless we're building with the leopard linker or later, which
2927 // automatically synthesizes these stubs.
2928 OpFlags = X86II::MO_DARWIN_STUB;
2931 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc));
2933 MIB.addExternalSymbol(SymName, OpFlags);
2935 MIB.addGlobalAddress(GV, 0, OpFlags);
2938 // Add a register mask operand representing the call-preserved registers.
2939 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2940 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2942 // Add an implicit use GOT pointer in EBX.
2943 if (Subtarget->isPICStyleGOT())
2944 MIB.addReg(X86::EBX, RegState::Implicit);
2946 if (Is64Bit && IsVarArg && !IsWin64)
2947 MIB.addReg(X86::AL, RegState::Implicit);
2949 // Add implicit physical register uses to the call.
2950 for (auto Reg : OutRegs)
2951 MIB.addReg(Reg, RegState::Implicit);
2953 // Issue CALLSEQ_END
2954 unsigned NumBytesForCalleeToPop =
2955 computeBytesPoppedByCallee(Subtarget, CC, CLI.CS);
2956 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2957 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
2958 .addImm(NumBytes).addImm(NumBytesForCalleeToPop);
2960 // Now handle call return values.
2961 SmallVector<CCValAssign, 16> RVLocs;
2962 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs,
2963 CLI.RetTy->getContext());
2964 CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86);
2966 // Copy all of the result registers out of their specified physreg.
2967 unsigned ResultReg = FuncInfo.CreateRegs(CLI.RetTy);
2968 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2969 CCValAssign &VA = RVLocs[i];
2970 EVT CopyVT = VA.getValVT();
2971 unsigned CopyReg = ResultReg + i;
2973 // If this is x86-64, and we disabled SSE, we can't return FP values
2974 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2975 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2976 report_fatal_error("SSE register return with SSE disabled");
2979 // If we prefer to use the value in xmm registers, copy it out as f80 and
2980 // use a truncate to move it from fp stack reg to xmm reg.
2981 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2982 isScalarFPTypeInSSEReg(VA.getValVT())) {
2984 CopyReg = createResultReg(&X86::RFP80RegClass);
2987 // Copy out the result.
2988 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2989 TII.get(TargetOpcode::COPY), CopyReg).addReg(VA.getLocReg());
2990 InRegs.push_back(VA.getLocReg());
2992 // Round the f80 to the right size, which also moves it to the appropriate
2993 // xmm register. This is accomplished by storing the f80 value in memory
2994 // and then loading it back.
2995 if (CopyVT != VA.getValVT()) {
2996 EVT ResVT = VA.getValVT();
2997 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
2998 unsigned MemSize = ResVT.getSizeInBits()/8;
2999 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
3000 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3003 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
3004 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3005 TII.get(Opc), ResultReg + i), FI);
3009 CLI.ResultReg = ResultReg;
3010 CLI.NumResultRegs = RVLocs.size();
3017 X86FastISel::fastSelectInstruction(const Instruction *I) {
3018 switch (I->getOpcode()) {
3020 case Instruction::Load:
3021 return X86SelectLoad(I);
3022 case Instruction::Store:
3023 return X86SelectStore(I);
3024 case Instruction::Ret:
3025 return X86SelectRet(I);
3026 case Instruction::ICmp:
3027 case Instruction::FCmp:
3028 return X86SelectCmp(I);
3029 case Instruction::ZExt:
3030 return X86SelectZExt(I);
3031 case Instruction::Br:
3032 return X86SelectBranch(I);
3033 case Instruction::LShr:
3034 case Instruction::AShr:
3035 case Instruction::Shl:
3036 return X86SelectShift(I);
3037 case Instruction::SDiv:
3038 case Instruction::UDiv:
3039 case Instruction::SRem:
3040 case Instruction::URem:
3041 return X86SelectDivRem(I);
3042 case Instruction::Select:
3043 return X86SelectSelect(I);
3044 case Instruction::Trunc:
3045 return X86SelectTrunc(I);
3046 case Instruction::FPExt:
3047 return X86SelectFPExt(I);
3048 case Instruction::FPTrunc:
3049 return X86SelectFPTrunc(I);
3050 case Instruction::IntToPtr: // Deliberate fall-through.
3051 case Instruction::PtrToInt: {
3052 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
3053 EVT DstVT = TLI.getValueType(I->getType());
3054 if (DstVT.bitsGT(SrcVT))
3055 return X86SelectZExt(I);
3056 if (DstVT.bitsLT(SrcVT))
3057 return X86SelectTrunc(I);
3058 unsigned Reg = getRegForValue(I->getOperand(0));
3059 if (Reg == 0) return false;
3060 updateValueMap(I, Reg);
3068 unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
3072 uint64_t Imm = CI->getZExtValue();
3074 unsigned SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass);
3075 switch (VT.SimpleTy) {
3076 default: llvm_unreachable("Unexpected value type");
3079 return fastEmitInst_extractsubreg(MVT::i8, SrcReg, /*Kill=*/true,
3082 return fastEmitInst_extractsubreg(MVT::i16, SrcReg, /*Kill=*/true,
3087 unsigned ResultReg = createResultReg(&X86::GR64RegClass);
3088 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3089 TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg)
3090 .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
3097 switch (VT.SimpleTy) {
3098 default: llvm_unreachable("Unexpected value type");
3099 case MVT::i1: VT = MVT::i8; // fall-through
3100 case MVT::i8: Opc = X86::MOV8ri; break;
3101 case MVT::i16: Opc = X86::MOV16ri; break;
3102 case MVT::i32: Opc = X86::MOV32ri; break;
3104 if (isUInt<32>(Imm))
3106 else if (isInt<32>(Imm))
3107 Opc = X86::MOV64ri32;
3113 if (VT == MVT::i64 && Opc == X86::MOV32ri) {
3114 unsigned SrcReg = fastEmitInst_i(Opc, &X86::GR32RegClass, Imm);
3115 unsigned ResultReg = createResultReg(&X86::GR64RegClass);
3116 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3117 TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg)
3118 .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
3121 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
3124 unsigned X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) {
3125 if (CFP->isNullValue())
3126 return fastMaterializeFloatZero(CFP);
3128 // Can't handle alternate code models yet.
3129 CodeModel::Model CM = TM.getCodeModel();
3130 if (CM != CodeModel::Small && CM != CodeModel::Large)
3133 // Get opcode and regclass of the output for the given load instruction.
3135 const TargetRegisterClass *RC = nullptr;
3136 switch (VT.SimpleTy) {
3139 if (X86ScalarSSEf32) {
3140 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
3141 RC = &X86::FR32RegClass;
3143 Opc = X86::LD_Fp32m;
3144 RC = &X86::RFP32RegClass;
3148 if (X86ScalarSSEf64) {
3149 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
3150 RC = &X86::FR64RegClass;
3152 Opc = X86::LD_Fp64m;
3153 RC = &X86::RFP64RegClass;
3157 // No f80 support yet.
3161 // MachineConstantPool wants an explicit alignment.
3162 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
3164 // Alignment of vector types. FIXME!
3165 Align = DL.getTypeAllocSize(CFP->getType());
3168 // x86-32 PIC requires a PIC base register for constant pools.
3169 unsigned PICBase = 0;
3170 unsigned char OpFlag = 0;
3171 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
3172 OpFlag = X86II::MO_PIC_BASE_OFFSET;
3173 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
3174 } else if (Subtarget->isPICStyleGOT()) {
3175 OpFlag = X86II::MO_GOTOFF;
3176 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
3177 } else if (Subtarget->isPICStyleRIPRel() &&
3178 TM.getCodeModel() == CodeModel::Small) {
3182 // Create the load from the constant pool.
3183 unsigned CPI = MCP.getConstantPoolIndex(CFP, Align);
3184 unsigned ResultReg = createResultReg(RC);
3186 if (CM == CodeModel::Large) {
3187 unsigned AddrReg = createResultReg(&X86::GR64RegClass);
3188 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri),
3190 .addConstantPoolIndex(CPI, 0, OpFlag);
3191 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3192 TII.get(Opc), ResultReg);
3193 addDirectMem(MIB, AddrReg);
3194 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
3195 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
3196 TM.getSubtargetImpl()->getDataLayout()->getPointerSize(), Align);
3197 MIB->addMemOperand(*FuncInfo.MF, MMO);
3201 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3202 TII.get(Opc), ResultReg),
3203 CPI, PICBase, OpFlag);
3207 unsigned X86FastISel::X86MaterializeGV(const GlobalValue *GV, MVT VT) {
3208 // Can't handle alternate code models yet.
3209 if (TM.getCodeModel() != CodeModel::Small)
3212 // Materialize addresses with LEA/MOV instructions.
3214 if (X86SelectAddress(GV, AM)) {
3215 // If the expression is just a basereg, then we're done, otherwise we need
3217 if (AM.BaseType == X86AddressMode::RegBase &&
3218 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == nullptr)
3221 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
3222 if (TM.getRelocationModel() == Reloc::Static &&
3223 TLI.getPointerTy() == MVT::i64) {
3224 // The displacement code could be more than 32 bits away so we need to use
3225 // an instruction with a 64 bit immediate
3226 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri),
3228 .addGlobalAddress(GV);
3230 unsigned Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
3231 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3232 TII.get(Opc), ResultReg), AM);
3239 unsigned X86FastISel::fastMaterializeConstant(const Constant *C) {
3240 EVT CEVT = TLI.getValueType(C->getType(), true);
3242 // Only handle simple types.
3243 if (!CEVT.isSimple())
3245 MVT VT = CEVT.getSimpleVT();
3247 if (const auto *CI = dyn_cast<ConstantInt>(C))
3248 return X86MaterializeInt(CI, VT);
3249 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
3250 return X86MaterializeFP(CFP, VT);
3251 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
3252 return X86MaterializeGV(GV, VT);
3257 unsigned X86FastISel::fastMaterializeAlloca(const AllocaInst *C) {
3258 // Fail on dynamic allocas. At this point, getRegForValue has already
3259 // checked its CSE maps, so if we're here trying to handle a dynamic
3260 // alloca, we're not going to succeed. X86SelectAddress has a
3261 // check for dynamic allocas, because it's called directly from
3262 // various places, but targetMaterializeAlloca also needs a check
3263 // in order to avoid recursion between getRegForValue,
3264 // X86SelectAddrss, and targetMaterializeAlloca.
3265 if (!FuncInfo.StaticAllocaMap.count(C))
3267 assert(C->isStaticAlloca() && "dynamic alloca in the static alloca map?");
3270 if (!X86SelectAddress(C, AM))
3272 unsigned Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
3273 const TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
3274 unsigned ResultReg = createResultReg(RC);
3275 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3276 TII.get(Opc), ResultReg), AM);
3280 unsigned X86FastISel::fastMaterializeFloatZero(const ConstantFP *CF) {
3282 if (!isTypeLegal(CF->getType(), VT))
3285 // Get opcode and regclass for the given zero.
3287 const TargetRegisterClass *RC = nullptr;
3288 switch (VT.SimpleTy) {
3291 if (X86ScalarSSEf32) {
3292 Opc = X86::FsFLD0SS;
3293 RC = &X86::FR32RegClass;
3295 Opc = X86::LD_Fp032;
3296 RC = &X86::RFP32RegClass;
3300 if (X86ScalarSSEf64) {
3301 Opc = X86::FsFLD0SD;
3302 RC = &X86::FR64RegClass;
3304 Opc = X86::LD_Fp064;
3305 RC = &X86::RFP64RegClass;
3309 // No f80 support yet.
3313 unsigned ResultReg = createResultReg(RC);
3314 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
3319 bool X86FastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
3320 const LoadInst *LI) {
3321 const Value *Ptr = LI->getPointerOperand();
3323 if (!X86SelectAddress(Ptr, AM))
3326 const X86InstrInfo &XII = (const X86InstrInfo &)TII;
3328 unsigned Size = DL.getTypeAllocSize(LI->getType());
3329 unsigned Alignment = LI->getAlignment();
3331 if (Alignment == 0) // Ensure that codegen never sees alignment 0
3332 Alignment = DL.getABITypeAlignment(LI->getType());
3334 SmallVector<MachineOperand, 8> AddrOps;
3335 AM.getFullAddress(AddrOps);
3337 MachineInstr *Result =
3338 XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps,
3339 Size, Alignment, /*AllowCommute=*/true);
3343 Result->addMemOperand(*FuncInfo.MF, createMachineMemOperandFor(LI));
3344 FuncInfo.MBB->insert(FuncInfo.InsertPt, Result);
3345 MI->eraseFromParent();
3351 FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo,
3352 const TargetLibraryInfo *libInfo) {
3353 return new X86FastISel(funcInfo, libInfo);