1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/Support/CallSite.h"
31 #include "llvm/Support/GetElementPtrTypeIterator.h"
35 class X86FastISel : public FastISel {
36 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
37 /// make the right decision when generating code for different targets.
38 const X86Subtarget *Subtarget;
40 /// StackPtr - Register used as the stack pointer.
44 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
45 /// floating point ops.
46 /// When SSE is available, use it for f32 operations.
47 /// When SSE2 is available, use it for f64 operations.
52 explicit X86FastISel(MachineFunction &mf,
53 MachineModuleInfo *mmi,
55 DenseMap<const Value *, unsigned> &vm,
56 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
57 DenseMap<const AllocaInst *, int> &am
59 , SmallSet<Instruction*, 8> &cil
62 : FastISel(mf, mmi, dw, vm, bm, am
67 Subtarget = &TM.getSubtarget<X86Subtarget>();
68 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
69 X86ScalarSSEf64 = Subtarget->hasSSE2();
70 X86ScalarSSEf32 = Subtarget->hasSSE1();
73 virtual bool TargetSelectInstruction(Instruction *I);
75 #include "X86GenFastISel.inc"
78 bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
80 bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
82 bool X86FastEmitStore(MVT VT, Value *Val,
83 const X86AddressMode &AM);
84 bool X86FastEmitStore(MVT VT, unsigned Val,
85 const X86AddressMode &AM);
87 bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
90 bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
92 bool X86SelectLoad(Instruction *I);
94 bool X86SelectStore(Instruction *I);
96 bool X86SelectCmp(Instruction *I);
98 bool X86SelectZExt(Instruction *I);
100 bool X86SelectBranch(Instruction *I);
102 bool X86SelectShift(Instruction *I);
104 bool X86SelectSelect(Instruction *I);
106 bool X86SelectTrunc(Instruction *I);
108 bool X86SelectFPExt(Instruction *I);
109 bool X86SelectFPTrunc(Instruction *I);
111 bool X86SelectExtractValue(Instruction *I);
113 bool X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic);
114 bool X86SelectCall(Instruction *I);
116 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
118 const X86InstrInfo *getInstrInfo() const {
119 return getTargetMachine()->getInstrInfo();
121 const X86TargetMachine *getTargetMachine() const {
122 return static_cast<const X86TargetMachine *>(&TM);
125 unsigned TargetMaterializeConstant(Constant *C);
127 unsigned TargetMaterializeAlloca(AllocaInst *C);
129 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
130 /// computed in an SSE register, not on the X87 floating point stack.
131 bool isScalarFPTypeInSSEReg(MVT VT) const {
132 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
133 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
136 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
139 bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
140 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
141 if (VT == MVT::Other || !VT.isSimple())
142 // Unhandled type. Halt "fast" selection and bail.
145 // For now, require SSE/SSE2 for performing floating-point operations,
146 // since x87 requires additional work.
147 if (VT == MVT::f64 && !X86ScalarSSEf64)
149 if (VT == MVT::f32 && !X86ScalarSSEf32)
151 // Similarly, no f80 support yet.
154 // We only handle legal types. For example, on x86-32 the instruction
155 // selector contains all of the 64-bit instructions from x86-64,
156 // under the assumption that i64 won't be used if the target doesn't
158 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
161 #include "X86GenCallingConv.inc"
163 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
165 CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
166 if (Subtarget->is64Bit()) {
167 if (Subtarget->isTargetWin64())
168 return CC_X86_Win64_C;
169 else if (CC == CallingConv::Fast && isTaillCall)
170 return CC_X86_64_TailCall;
175 if (CC == CallingConv::X86_FastCall)
176 return CC_X86_32_FastCall;
177 else if (CC == CallingConv::Fast)
178 return CC_X86_32_FastCC;
183 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
184 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
185 /// Return true and the result register by reference if it is possible.
186 bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
187 unsigned &ResultReg) {
188 // Get opcode and regclass of the output for the given load instruction.
190 const TargetRegisterClass *RC = NULL;
191 switch (VT.getSimpleVT()) {
192 default: return false;
195 RC = X86::GR8RegisterClass;
199 RC = X86::GR16RegisterClass;
203 RC = X86::GR32RegisterClass;
206 // Must be in x86-64 mode.
208 RC = X86::GR64RegisterClass;
211 if (Subtarget->hasSSE1()) {
213 RC = X86::FR32RegisterClass;
216 RC = X86::RFP32RegisterClass;
220 if (Subtarget->hasSSE2()) {
222 RC = X86::FR64RegisterClass;
225 RC = X86::RFP64RegisterClass;
229 // No f80 support yet.
233 ResultReg = createResultReg(RC);
234 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
238 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
239 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
240 /// and a displacement offset, or a GlobalAddress,
241 /// i.e. V. Return true if it is possible.
243 X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
244 const X86AddressMode &AM) {
245 // Get opcode and regclass of the output for the given store instruction.
247 switch (VT.getSimpleVT()) {
248 case MVT::f80: // No f80 support yet.
249 default: return false;
250 case MVT::i8: Opc = X86::MOV8mr; break;
251 case MVT::i16: Opc = X86::MOV16mr; break;
252 case MVT::i32: Opc = X86::MOV32mr; break;
253 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
255 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
258 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
262 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
266 bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val,
267 const X86AddressMode &AM) {
268 // Handle 'null' like i32/i64 0.
269 if (isa<ConstantPointerNull>(Val))
270 Val = Constant::getNullValue(TD.getIntPtrType());
272 // If this is a store of a simple constant, fold the constant into the store.
273 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
275 switch (VT.getSimpleVT()) {
277 case MVT::i8: Opc = X86::MOV8mi; break;
278 case MVT::i16: Opc = X86::MOV16mi; break;
279 case MVT::i32: Opc = X86::MOV32mi; break;
281 // Must be a 32-bit sign extended value.
282 if ((int)CI->getSExtValue() == CI->getSExtValue())
283 Opc = X86::MOV64mi32;
288 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
289 .addImm(CI->getSExtValue());
294 unsigned ValReg = getRegForValue(Val);
298 return X86FastEmitStore(VT, ValReg, AM);
301 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
302 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
303 /// ISD::SIGN_EXTEND).
304 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
305 unsigned Src, MVT SrcVT,
306 unsigned &ResultReg) {
307 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
316 /// X86SelectAddress - Attempt to fill in an address from the given value.
318 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
320 unsigned Opcode = Instruction::UserOp1;
321 if (Instruction *I = dyn_cast<Instruction>(V)) {
322 Opcode = I->getOpcode();
324 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
325 Opcode = C->getOpcode();
331 case Instruction::BitCast:
332 // Look past bitcasts.
333 return X86SelectAddress(U->getOperand(0), AM, isCall);
335 case Instruction::IntToPtr:
336 // Look past no-op inttoptrs.
337 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
338 return X86SelectAddress(U->getOperand(0), AM, isCall);
341 case Instruction::PtrToInt:
342 // Look past no-op ptrtoints.
343 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
344 return X86SelectAddress(U->getOperand(0), AM, isCall);
347 case Instruction::Alloca: {
349 // Do static allocas.
350 const AllocaInst *A = cast<AllocaInst>(V);
351 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
352 if (SI != StaticAllocaMap.end()) {
353 AM.BaseType = X86AddressMode::FrameIndexBase;
354 AM.Base.FrameIndex = SI->second;
360 case Instruction::Add: {
362 // Adds of constants are common and easy enough.
363 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
364 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
365 // They have to fit in the 32-bit signed displacement field though.
367 AM.Disp = (uint32_t)Disp;
368 return X86SelectAddress(U->getOperand(0), AM, isCall);
374 case Instruction::GetElementPtr: {
376 // Pattern-match simple GEPs.
377 uint64_t Disp = (int32_t)AM.Disp;
378 unsigned IndexReg = AM.IndexReg;
379 unsigned Scale = AM.Scale;
380 gep_type_iterator GTI = gep_type_begin(U);
381 // Iterate through the indices, folding what we can. Constants can be
382 // folded, and one dynamic index can be handled, if the scale is supported.
383 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
384 i != e; ++i, ++GTI) {
386 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
387 const StructLayout *SL = TD.getStructLayout(STy);
388 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
389 Disp += SL->getElementOffset(Idx);
391 uint64_t S = TD.getTypePaddedSize(GTI.getIndexedType());
392 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
393 // Constant-offset addressing.
394 Disp += CI->getSExtValue() * S;
395 } else if (IndexReg == 0 &&
397 !getTargetMachine()->symbolicAddressesAreRIPRel()) &&
398 (S == 1 || S == 2 || S == 4 || S == 8)) {
399 // Scaled-index addressing.
401 IndexReg = getRegForGEPIndex(Op);
406 goto unsupported_gep;
409 // Check for displacement overflow.
412 // Ok, the GEP indices were covered by constant-offset and scaled-index
413 // addressing. Update the address state and move on to examining the base.
414 AM.IndexReg = IndexReg;
416 AM.Disp = (uint32_t)Disp;
417 return X86SelectAddress(U->getOperand(0), AM, isCall);
419 // Ok, the GEP indices weren't all covered.
424 // Handle constant address.
425 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
426 // Can't handle alternate code models yet.
427 if (TM.getCodeModel() != CodeModel::Default &&
428 TM.getCodeModel() != CodeModel::Small)
431 // RIP-relative addresses can't have additional register operands.
432 if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
433 (AM.Base.Reg != 0 || AM.IndexReg != 0))
436 // Set up the basic address.
439 TM.getRelocationModel() == Reloc::PIC_ &&
440 !Subtarget->is64Bit())
441 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
443 // Emit an extra load if the ABI requires it.
444 if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
445 // Check to see if we've already materialized this
446 // value in a register in this block.
447 if (unsigned Reg = LocalValueMap[V]) {
452 // Issue load from stub if necessary.
454 const TargetRegisterClass *RC = NULL;
455 if (TLI.getPointerTy() == MVT::i32) {
457 RC = X86::GR32RegisterClass;
460 RC = X86::GR64RegisterClass;
463 X86AddressMode StubAM;
464 StubAM.Base.Reg = AM.Base.Reg;
466 unsigned ResultReg = createResultReg(RC);
467 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), StubAM);
469 // Now construct the final address. Note that the Disp, Scale,
470 // and Index values may already be set here.
471 AM.Base.Reg = ResultReg;
474 // Prevent loading GV stub multiple times in same MBB.
475 LocalValueMap[V] = AM.Base.Reg;
480 // If all else fails, try to materialize the value in a register.
481 if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
482 if (AM.Base.Reg == 0) {
483 AM.Base.Reg = getRegForValue(V);
484 return AM.Base.Reg != 0;
486 if (AM.IndexReg == 0) {
487 assert(AM.Scale == 1 && "Scale with no index!");
488 AM.IndexReg = getRegForValue(V);
489 return AM.IndexReg != 0;
496 /// X86SelectStore - Select and emit code to implement store instructions.
497 bool X86FastISel::X86SelectStore(Instruction* I) {
499 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
503 if (!X86SelectAddress(I->getOperand(1), AM, false))
506 return X86FastEmitStore(VT, I->getOperand(0), AM);
509 /// X86SelectLoad - Select and emit code to implement load instructions.
511 bool X86FastISel::X86SelectLoad(Instruction *I) {
513 if (!isTypeLegal(I->getType(), VT))
517 if (!X86SelectAddress(I->getOperand(0), AM, false))
520 unsigned ResultReg = 0;
521 if (X86FastEmitLoad(VT, AM, ResultReg)) {
522 UpdateValueMap(I, ResultReg);
528 static unsigned X86ChooseCmpOpcode(MVT VT) {
529 switch (VT.getSimpleVT()) {
531 case MVT::i8: return X86::CMP8rr;
532 case MVT::i16: return X86::CMP16rr;
533 case MVT::i32: return X86::CMP32rr;
534 case MVT::i64: return X86::CMP64rr;
535 case MVT::f32: return X86::UCOMISSrr;
536 case MVT::f64: return X86::UCOMISDrr;
540 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
541 /// of the comparison, return an opcode that works for the compare (e.g.
542 /// CMP32ri) otherwise return 0.
543 static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
544 switch (VT.getSimpleVT()) {
545 // Otherwise, we can't fold the immediate into this comparison.
547 case MVT::i8: return X86::CMP8ri;
548 case MVT::i16: return X86::CMP16ri;
549 case MVT::i32: return X86::CMP32ri;
551 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
553 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
554 return X86::CMP64ri32;
559 bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
560 unsigned Op0Reg = getRegForValue(Op0);
561 if (Op0Reg == 0) return false;
563 // Handle 'null' like i32/i64 0.
564 if (isa<ConstantPointerNull>(Op1))
565 Op1 = Constant::getNullValue(TD.getIntPtrType());
567 // We have two options: compare with register or immediate. If the RHS of
568 // the compare is an immediate that we can fold into this compare, use
569 // CMPri, otherwise use CMPrr.
570 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
571 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
572 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
573 .addImm(Op1C->getSExtValue());
578 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
579 if (CompareOpc == 0) return false;
581 unsigned Op1Reg = getRegForValue(Op1);
582 if (Op1Reg == 0) return false;
583 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
588 bool X86FastISel::X86SelectCmp(Instruction *I) {
589 CmpInst *CI = cast<CmpInst>(I);
592 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
595 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
597 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
598 switch (CI->getPredicate()) {
599 case CmpInst::FCMP_OEQ: {
600 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
603 unsigned EReg = createResultReg(&X86::GR8RegClass);
604 unsigned NPReg = createResultReg(&X86::GR8RegClass);
605 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
606 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
608 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
609 UpdateValueMap(I, ResultReg);
612 case CmpInst::FCMP_UNE: {
613 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
616 unsigned NEReg = createResultReg(&X86::GR8RegClass);
617 unsigned PReg = createResultReg(&X86::GR8RegClass);
618 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
619 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
620 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
621 UpdateValueMap(I, ResultReg);
624 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
625 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
626 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
627 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
628 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
629 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
630 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
631 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
632 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
633 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
634 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
635 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
637 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
638 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
639 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
640 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
641 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
642 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
643 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
644 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
645 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
646 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
651 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
655 // Emit a compare of Op0/Op1.
656 if (!X86FastEmitCompare(Op0, Op1, VT))
659 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
660 UpdateValueMap(I, ResultReg);
664 bool X86FastISel::X86SelectZExt(Instruction *I) {
665 // Special-case hack: The only i1 values we know how to produce currently
666 // set the upper bits of an i8 value to zero.
667 if (I->getType() == Type::Int8Ty &&
668 I->getOperand(0)->getType() == Type::Int1Ty) {
669 unsigned ResultReg = getRegForValue(I->getOperand(0));
670 if (ResultReg == 0) return false;
671 UpdateValueMap(I, ResultReg);
679 bool X86FastISel::X86SelectBranch(Instruction *I) {
680 // Unconditional branches are selected by tablegen-generated code.
681 // Handle a conditional branch.
682 BranchInst *BI = cast<BranchInst>(I);
683 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
684 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
686 // Fold the common case of a conditional branch with a comparison.
687 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
688 if (CI->hasOneUse()) {
689 MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
691 // Try to take advantage of fallthrough opportunities.
692 CmpInst::Predicate Predicate = CI->getPredicate();
693 if (MBB->isLayoutSuccessor(TrueMBB)) {
694 std::swap(TrueMBB, FalseMBB);
695 Predicate = CmpInst::getInversePredicate(Predicate);
698 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
699 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
702 case CmpInst::FCMP_OEQ:
703 std::swap(TrueMBB, FalseMBB);
704 Predicate = CmpInst::FCMP_UNE;
706 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break;
707 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break;
708 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
709 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break;
710 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break;
711 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
712 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
713 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break;
714 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break;
715 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break;
716 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break;
717 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
718 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
720 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break;
721 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break;
722 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break;
723 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
724 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
725 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
726 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break;
727 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
728 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break;
729 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
734 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
738 // Emit a compare of the LHS and RHS, setting the flags.
739 if (!X86FastEmitCompare(Op0, Op1, VT))
742 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
744 if (Predicate == CmpInst::FCMP_UNE) {
745 // X86 requires a second branch to handle UNE (and OEQ,
746 // which is mapped to UNE above).
747 BuildMI(MBB, DL, TII.get(X86::JP)).addMBB(TrueMBB);
750 FastEmitBranch(FalseMBB);
751 MBB->addSuccessor(TrueMBB);
754 } else if (ExtractValueInst *EI =
755 dyn_cast<ExtractValueInst>(BI->getCondition())) {
756 // Check to see if the branch instruction is from an "arithmetic with
757 // overflow" intrinsic. The main way these intrinsics are used is:
759 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
760 // %sum = extractvalue { i32, i1 } %t, 0
761 // %obit = extractvalue { i32, i1 } %t, 1
762 // br i1 %obit, label %overflow, label %normal
764 // The %sum and %obit are converted in an ADD and a SETO/SETB before
765 // reaching the branch. Therefore, we search backwards through the MBB
766 // looking for the SETO/SETB instruction. If an instruction modifies the
767 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
768 // convert the branch into a JO/JB instruction.
770 Value *Agg = EI->getAggregateOperand();
772 if (CallInst *CI = dyn_cast<CallInst>(Agg)) {
773 Function *F = CI->getCalledFunction();
775 if (F && F->isDeclaration()) {
776 switch (F->getIntrinsicID()) {
778 case Intrinsic::sadd_with_overflow:
779 case Intrinsic::uadd_with_overflow: {
780 const MachineInstr *SetMI = 0;
781 unsigned Reg = lookUpRegForValue(EI);
783 for (MachineBasicBlock::const_reverse_iterator
784 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
785 const MachineInstr &MI = *RI;
787 if (MI.modifiesRegister(Reg)) {
788 unsigned Src, Dst, SrcSR, DstSR;
790 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
799 const TargetInstrDesc &TID = MI.getDesc();
800 const unsigned *ImpDefs = TID.getImplicitDefs();
802 if (TID.hasUnmodeledSideEffects()) break;
804 bool ModifiesEFlags = false;
807 for (unsigned u = 0; ImpDefs[u]; ++u)
808 if (ImpDefs[u] == X86::EFLAGS) {
809 ModifiesEFlags = true;
814 if (ModifiesEFlags) break;
818 unsigned OpCode = SetMI->getOpcode();
820 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
821 BuildMI(MBB, DL, TII.get((OpCode == X86::SETOr) ?
822 X86::JO : X86::JB)).addMBB(TrueMBB);
823 FastEmitBranch(FalseMBB);
824 MBB->addSuccessor(TrueMBB);
834 // Otherwise do a clumsy setcc and re-test it.
835 unsigned OpReg = getRegForValue(BI->getCondition());
836 if (OpReg == 0) return false;
838 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
839 BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(TrueMBB);
840 FastEmitBranch(FalseMBB);
841 MBB->addSuccessor(TrueMBB);
845 bool X86FastISel::X86SelectShift(Instruction *I) {
846 unsigned CReg = 0, OpReg = 0, OpImm = 0;
847 const TargetRegisterClass *RC = NULL;
848 if (I->getType() == Type::Int8Ty) {
850 RC = &X86::GR8RegClass;
851 switch (I->getOpcode()) {
852 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
853 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
854 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
855 default: return false;
857 } else if (I->getType() == Type::Int16Ty) {
859 RC = &X86::GR16RegClass;
860 switch (I->getOpcode()) {
861 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
862 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
863 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
864 default: return false;
866 } else if (I->getType() == Type::Int32Ty) {
868 RC = &X86::GR32RegClass;
869 switch (I->getOpcode()) {
870 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
871 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
872 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
873 default: return false;
875 } else if (I->getType() == Type::Int64Ty) {
877 RC = &X86::GR64RegClass;
878 switch (I->getOpcode()) {
879 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
880 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
881 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
882 default: return false;
888 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
889 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
892 unsigned Op0Reg = getRegForValue(I->getOperand(0));
893 if (Op0Reg == 0) return false;
895 // Fold immediate in shl(x,3).
896 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
897 unsigned ResultReg = createResultReg(RC);
898 BuildMI(MBB, DL, TII.get(OpImm),
899 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
900 UpdateValueMap(I, ResultReg);
904 unsigned Op1Reg = getRegForValue(I->getOperand(1));
905 if (Op1Reg == 0) return false;
906 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
908 // The shift instruction uses X86::CL. If we defined a super-register
909 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
912 BuildMI(MBB, DL, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
913 .addReg(CReg).addImm(X86::SUBREG_8BIT);
915 unsigned ResultReg = createResultReg(RC);
916 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
917 UpdateValueMap(I, ResultReg);
921 bool X86FastISel::X86SelectSelect(Instruction *I) {
922 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
923 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
927 const TargetRegisterClass *RC = NULL;
928 if (VT.getSimpleVT() == MVT::i16) {
929 Opc = X86::CMOVE16rr;
930 RC = &X86::GR16RegClass;
931 } else if (VT.getSimpleVT() == MVT::i32) {
932 Opc = X86::CMOVE32rr;
933 RC = &X86::GR32RegClass;
934 } else if (VT.getSimpleVT() == MVT::i64) {
935 Opc = X86::CMOVE64rr;
936 RC = &X86::GR64RegClass;
941 unsigned Op0Reg = getRegForValue(I->getOperand(0));
942 if (Op0Reg == 0) return false;
943 unsigned Op1Reg = getRegForValue(I->getOperand(1));
944 if (Op1Reg == 0) return false;
945 unsigned Op2Reg = getRegForValue(I->getOperand(2));
946 if (Op2Reg == 0) return false;
948 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
949 unsigned ResultReg = createResultReg(RC);
950 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
951 UpdateValueMap(I, ResultReg);
955 bool X86FastISel::X86SelectFPExt(Instruction *I) {
956 // fpext from float to double.
957 if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
958 Value *V = I->getOperand(0);
959 if (V->getType() == Type::FloatTy) {
960 unsigned OpReg = getRegForValue(V);
961 if (OpReg == 0) return false;
962 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
963 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
964 UpdateValueMap(I, ResultReg);
972 bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
973 if (Subtarget->hasSSE2()) {
974 if (I->getType() == Type::FloatTy) {
975 Value *V = I->getOperand(0);
976 if (V->getType() == Type::DoubleTy) {
977 unsigned OpReg = getRegForValue(V);
978 if (OpReg == 0) return false;
979 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
980 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
981 UpdateValueMap(I, ResultReg);
990 bool X86FastISel::X86SelectTrunc(Instruction *I) {
991 if (Subtarget->is64Bit())
992 // All other cases should be handled by the tblgen generated code.
994 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
995 MVT DstVT = TLI.getValueType(I->getType());
996 if (DstVT != MVT::i8)
997 // All other cases should be handled by the tblgen generated code.
999 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
1000 // All other cases should be handled by the tblgen generated code.
1003 unsigned InputReg = getRegForValue(I->getOperand(0));
1005 // Unhandled operand. Halt "fast" selection and bail.
1008 // First issue a copy to GR16_ or GR32_.
1009 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16to16_ : X86::MOV32to32_;
1010 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1011 ? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
1012 unsigned CopyReg = createResultReg(CopyRC);
1013 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1015 // Then issue an extract_subreg.
1016 unsigned ResultReg = FastEmitInst_extractsubreg(DstVT.getSimpleVT(),
1017 CopyReg, X86::SUBREG_8BIT);
1021 UpdateValueMap(I, ResultReg);
1025 bool X86FastISel::X86SelectExtractValue(Instruction *I) {
1026 ExtractValueInst *EI = cast<ExtractValueInst>(I);
1027 Value *Agg = EI->getAggregateOperand();
1029 if (CallInst *CI = dyn_cast<CallInst>(Agg)) {
1030 Function *F = CI->getCalledFunction();
1032 if (F && F->isDeclaration()) {
1033 switch (F->getIntrinsicID()) {
1035 case Intrinsic::sadd_with_overflow:
1036 case Intrinsic::uadd_with_overflow:
1037 // Cheat a little. We know that the registers for "add" and "seto" are
1038 // allocated sequentially. However, we only keep track of the register
1039 // for "add" in the value map. Use extractvalue's index to get the
1040 // correct register for "seto".
1041 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1050 bool X86FastISel::X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1051 // FIXME: Handle more intrinsics.
1052 switch (Intrinsic) {
1053 default: return false;
1054 case Intrinsic::sadd_with_overflow:
1055 case Intrinsic::uadd_with_overflow: {
1056 // Replace "add with overflow" intrinsics with an "add" instruction followed
1057 // by a seto/setc instruction. Later on, when the "extractvalue"
1058 // instructions are encountered, we use the fact that two registers were
1059 // created sequentially to get the correct registers for the "sum" and the
1062 const Function *Callee = I.getCalledFunction();
1064 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1066 if (!isTypeLegal(RetTy, VT))
1069 Value *Op1 = I.getOperand(1);
1070 Value *Op2 = I.getOperand(2);
1071 unsigned Reg1 = getRegForValue(Op1);
1072 unsigned Reg2 = getRegForValue(Op2);
1074 if (Reg1 == 0 || Reg2 == 0)
1075 // FIXME: Handle values *not* in registers.
1082 else if (VT == MVT::i64)
1087 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1088 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1089 UpdateValueMap(&I, ResultReg);
1091 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1092 BuildMI(MBB, DL, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ?
1093 X86::SETOr : X86::SETBr), ResultReg);
1099 bool X86FastISel::X86SelectCall(Instruction *I) {
1100 CallInst *CI = cast<CallInst>(I);
1101 Value *Callee = I->getOperand(0);
1103 // Can't handle inline asm yet.
1104 if (isa<InlineAsm>(Callee))
1107 // Handle intrinsic calls.
1108 if (Function *F = CI->getCalledFunction())
1109 if (F->isDeclaration())
1110 if (unsigned IID = F->getIntrinsicID())
1111 return X86VisitIntrinsicCall(*CI, IID);
1113 // Handle only C and fastcc calling conventions for now.
1115 unsigned CC = CS.getCallingConv();
1116 if (CC != CallingConv::C &&
1117 CC != CallingConv::Fast &&
1118 CC != CallingConv::X86_FastCall)
1121 // Let SDISel handle vararg functions.
1122 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1123 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1124 if (FTy->isVarArg())
1127 // Handle *simple* calls for now.
1128 const Type *RetTy = CS.getType();
1130 if (RetTy == Type::VoidTy)
1131 RetVT = MVT::isVoid;
1132 else if (!isTypeLegal(RetTy, RetVT, true))
1135 // Materialize callee address in a register. FIXME: GV address can be
1136 // handled with a CALLpcrel32 instead.
1137 X86AddressMode CalleeAM;
1138 if (!X86SelectAddress(Callee, CalleeAM, true))
1140 unsigned CalleeOp = 0;
1141 GlobalValue *GV = 0;
1142 if (CalleeAM.Base.Reg != 0) {
1143 assert(CalleeAM.GV == 0);
1144 CalleeOp = CalleeAM.Base.Reg;
1145 } else if (CalleeAM.GV != 0) {
1146 assert(CalleeAM.GV != 0);
1151 // Allow calls which produce i1 results.
1152 bool AndToI1 = false;
1153 if (RetVT == MVT::i1) {
1158 // Deal with call operands first.
1159 SmallVector<Value*, 8> ArgVals;
1160 SmallVector<unsigned, 8> Args;
1161 SmallVector<MVT, 8> ArgVTs;
1162 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1163 Args.reserve(CS.arg_size());
1164 ArgVals.reserve(CS.arg_size());
1165 ArgVTs.reserve(CS.arg_size());
1166 ArgFlags.reserve(CS.arg_size());
1167 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1169 unsigned Arg = getRegForValue(*i);
1172 ISD::ArgFlagsTy Flags;
1173 unsigned AttrInd = i - CS.arg_begin() + 1;
1174 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1176 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1179 // FIXME: Only handle *easy* calls for now.
1180 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1181 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1182 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1183 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1186 const Type *ArgTy = (*i)->getType();
1188 if (!isTypeLegal(ArgTy, ArgVT))
1190 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1191 Flags.setOrigAlign(OriginalAlignment);
1193 Args.push_back(Arg);
1194 ArgVals.push_back(*i);
1195 ArgVTs.push_back(ArgVT);
1196 ArgFlags.push_back(Flags);
1199 // Analyze operands of the call, assigning locations to each operand.
1200 SmallVector<CCValAssign, 16> ArgLocs;
1201 CCState CCInfo(CC, false, TM, ArgLocs);
1202 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1204 // Get a count of how many bytes are to be pushed on the stack.
1205 unsigned NumBytes = CCInfo.getNextStackOffset();
1207 // Issue CALLSEQ_START
1208 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1209 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1211 // Process argument: walk the register/memloc assignments, inserting
1213 SmallVector<unsigned, 4> RegArgs;
1214 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1215 CCValAssign &VA = ArgLocs[i];
1216 unsigned Arg = Args[VA.getValNo()];
1217 MVT ArgVT = ArgVTs[VA.getValNo()];
1219 // Promote the value if needed.
1220 switch (VA.getLocInfo()) {
1221 default: assert(0 && "Unknown loc info!");
1222 case CCValAssign::Full: break;
1223 case CCValAssign::SExt: {
1224 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1226 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1228 ArgVT = VA.getLocVT();
1231 case CCValAssign::ZExt: {
1232 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1234 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1236 ArgVT = VA.getLocVT();
1239 case CCValAssign::AExt: {
1240 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1243 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1246 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1249 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1250 ArgVT = VA.getLocVT();
1255 if (VA.isRegLoc()) {
1256 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1257 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1259 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1261 RegArgs.push_back(VA.getLocReg());
1263 unsigned LocMemOffset = VA.getLocMemOffset();
1265 AM.Base.Reg = StackPtr;
1266 AM.Disp = LocMemOffset;
1267 Value *ArgVal = ArgVals[VA.getValNo()];
1269 // If this is a really simple value, emit this with the Value* version of
1270 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1271 // can cause us to reevaluate the argument.
1272 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1273 X86FastEmitStore(ArgVT, ArgVal, AM);
1275 X86FastEmitStore(ArgVT, Arg, AM);
1279 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1281 if (!Subtarget->is64Bit() &&
1282 TM.getRelocationModel() == Reloc::PIC_ &&
1283 Subtarget->isPICStyleGOT()) {
1284 TargetRegisterClass *RC = X86::GR32RegisterClass;
1285 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1286 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1287 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1292 unsigned CallOpc = CalleeOp
1293 ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
1294 : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
1295 MachineInstrBuilder MIB = CalleeOp
1296 ? BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp)
1297 : BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV);
1299 // Add an implicit use GOT pointer in EBX.
1300 if (!Subtarget->is64Bit() &&
1301 TM.getRelocationModel() == Reloc::PIC_ &&
1302 Subtarget->isPICStyleGOT())
1303 MIB.addReg(X86::EBX);
1305 // Add implicit physical register uses to the call.
1306 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1307 MIB.addReg(RegArgs[i]);
1309 // Issue CALLSEQ_END
1310 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1311 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1313 // Now handle call return value (if any).
1314 if (RetVT.getSimpleVT() != MVT::isVoid) {
1315 SmallVector<CCValAssign, 16> RVLocs;
1316 CCState CCInfo(CC, false, TM, RVLocs);
1317 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1319 // Copy all of the result registers out of their specified physreg.
1320 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1321 MVT CopyVT = RVLocs[0].getValVT();
1322 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1323 TargetRegisterClass *SrcRC = DstRC;
1325 // If this is a call to a function that returns an fp value on the x87 fp
1326 // stack, but where we prefer to use the value in xmm registers, copy it
1327 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1328 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1329 RVLocs[0].getLocReg() == X86::ST1) &&
1330 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1332 SrcRC = X86::RSTRegisterClass;
1333 DstRC = X86::RFP80RegisterClass;
1336 unsigned ResultReg = createResultReg(DstRC);
1337 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1338 RVLocs[0].getLocReg(), DstRC, SrcRC);
1339 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1341 if (CopyVT != RVLocs[0].getValVT()) {
1342 // Round the F80 the right size, which also moves to the appropriate xmm
1343 // register. This is accomplished by storing the F80 value in memory and
1344 // then loading it back. Ewww...
1345 MVT ResVT = RVLocs[0].getValVT();
1346 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1347 unsigned MemSize = ResVT.getSizeInBits()/8;
1348 int FI = MFI.CreateStackObject(MemSize, MemSize);
1349 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1350 DstRC = ResVT == MVT::f32
1351 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1352 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1353 ResultReg = createResultReg(DstRC);
1354 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1358 // Mask out all but lowest bit for some call which produces an i1.
1359 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1361 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1362 ResultReg = AndResult;
1365 UpdateValueMap(I, ResultReg);
1373 X86FastISel::TargetSelectInstruction(Instruction *I) {
1374 switch (I->getOpcode()) {
1376 case Instruction::Load:
1377 return X86SelectLoad(I);
1378 case Instruction::Store:
1379 return X86SelectStore(I);
1380 case Instruction::ICmp:
1381 case Instruction::FCmp:
1382 return X86SelectCmp(I);
1383 case Instruction::ZExt:
1384 return X86SelectZExt(I);
1385 case Instruction::Br:
1386 return X86SelectBranch(I);
1387 case Instruction::Call:
1388 return X86SelectCall(I);
1389 case Instruction::LShr:
1390 case Instruction::AShr:
1391 case Instruction::Shl:
1392 return X86SelectShift(I);
1393 case Instruction::Select:
1394 return X86SelectSelect(I);
1395 case Instruction::Trunc:
1396 return X86SelectTrunc(I);
1397 case Instruction::FPExt:
1398 return X86SelectFPExt(I);
1399 case Instruction::FPTrunc:
1400 return X86SelectFPTrunc(I);
1401 case Instruction::ExtractValue:
1402 return X86SelectExtractValue(I);
1408 unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
1410 if (!isTypeLegal(C->getType(), VT))
1413 // Get opcode and regclass of the output for the given load instruction.
1415 const TargetRegisterClass *RC = NULL;
1416 switch (VT.getSimpleVT()) {
1417 default: return false;
1420 RC = X86::GR8RegisterClass;
1424 RC = X86::GR16RegisterClass;
1428 RC = X86::GR32RegisterClass;
1431 // Must be in x86-64 mode.
1433 RC = X86::GR64RegisterClass;
1436 if (Subtarget->hasSSE1()) {
1438 RC = X86::FR32RegisterClass;
1440 Opc = X86::LD_Fp32m;
1441 RC = X86::RFP32RegisterClass;
1445 if (Subtarget->hasSSE2()) {
1447 RC = X86::FR64RegisterClass;
1449 Opc = X86::LD_Fp64m;
1450 RC = X86::RFP64RegisterClass;
1454 // No f80 support yet.
1458 // Materialize addresses with LEA instructions.
1459 if (isa<GlobalValue>(C)) {
1461 if (X86SelectAddress(C, AM, false)) {
1462 if (TLI.getPointerTy() == MVT::i32)
1466 unsigned ResultReg = createResultReg(RC);
1467 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1473 // MachineConstantPool wants an explicit alignment.
1474 unsigned Align = TD.getPreferredTypeAlignmentShift(C->getType());
1476 // Alignment of vector types. FIXME!
1477 Align = TD.getTypePaddedSize(C->getType());
1478 Align = Log2_64(Align);
1481 // x86-32 PIC requires a PIC base register for constant pools.
1482 unsigned PICBase = 0;
1483 if (TM.getRelocationModel() == Reloc::PIC_ &&
1484 !Subtarget->is64Bit())
1485 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1487 // Create the load from the constant pool.
1488 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1489 unsigned ResultReg = createResultReg(RC);
1490 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), MCPOffset,
1496 unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
1497 // Fail on dynamic allocas. At this point, getRegForValue has already
1498 // checked its CSE maps, so if we're here trying to handle a dynamic
1499 // alloca, we're not going to succeed. X86SelectAddress has a
1500 // check for dynamic allocas, because it's called directly from
1501 // various places, but TargetMaterializeAlloca also needs a check
1502 // in order to avoid recursion between getRegForValue,
1503 // X86SelectAddrss, and TargetMaterializeAlloca.
1504 if (!StaticAllocaMap.count(C))
1508 if (!X86SelectAddress(C, AM, false))
1510 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1511 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1512 unsigned ResultReg = createResultReg(RC);
1513 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1518 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1519 MachineModuleInfo *mmi,
1521 DenseMap<const Value *, unsigned> &vm,
1522 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1523 DenseMap<const AllocaInst *, int> &am
1525 , SmallSet<Instruction*, 8> &cil
1528 return new X86FastISel(mf, mmi, dw, vm, bm, am