1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/GlobalAlias.h"
31 #include "llvm/IR/GlobalVariable.h"
32 #include "llvm/IR/Instructions.h"
33 #include "llvm/IR/IntrinsicInst.h"
34 #include "llvm/IR/Operator.h"
35 #include "llvm/Support/CallSite.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/GetElementPtrTypeIterator.h"
38 #include "llvm/Target/TargetOptions.h"
43 class X86FastISel : public FastISel {
44 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
45 /// make the right decision when generating code for different targets.
46 const X86Subtarget *Subtarget;
48 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
49 /// floating point ops.
50 /// When SSE is available, use it for f32 operations.
51 /// When SSE2 is available, use it for f64 operations.
56 explicit X86FastISel(FunctionLoweringInfo &funcInfo,
57 const TargetLibraryInfo *libInfo)
58 : FastISel(funcInfo, libInfo) {
59 Subtarget = &TM.getSubtarget<X86Subtarget>();
60 X86ScalarSSEf64 = Subtarget->hasSSE2();
61 X86ScalarSSEf32 = Subtarget->hasSSE1();
64 virtual bool TargetSelectInstruction(const Instruction *I);
66 /// \brief The specified machine instr operand is a vreg, and that
67 /// vreg is being provided by the specified load instruction. If possible,
68 /// try to fold the load as an operand to the instruction, returning true if
70 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
73 virtual bool FastLowerArguments();
75 #include "X86GenFastISel.inc"
78 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
80 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
82 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM,
83 bool Aligned = false);
84 bool X86FastEmitStore(EVT VT, unsigned ValReg, const X86AddressMode &AM,
85 bool Aligned = false);
87 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
90 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
91 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
93 bool X86SelectLoad(const Instruction *I);
95 bool X86SelectStore(const Instruction *I);
97 bool X86SelectRet(const Instruction *I);
99 bool X86SelectCmp(const Instruction *I);
101 bool X86SelectZExt(const Instruction *I);
103 bool X86SelectBranch(const Instruction *I);
105 bool X86SelectShift(const Instruction *I);
107 bool X86SelectDivRem(const Instruction *I);
109 bool X86SelectSelect(const Instruction *I);
111 bool X86SelectTrunc(const Instruction *I);
113 bool X86SelectFPExt(const Instruction *I);
114 bool X86SelectFPTrunc(const Instruction *I);
116 bool X86VisitIntrinsicCall(const IntrinsicInst &I);
117 bool X86SelectCall(const Instruction *I);
119 bool DoSelectCall(const Instruction *I, const char *MemIntName);
121 const X86InstrInfo *getInstrInfo() const {
122 return getTargetMachine()->getInstrInfo();
124 const X86TargetMachine *getTargetMachine() const {
125 return static_cast<const X86TargetMachine *>(&TM);
128 bool handleConstantAddresses(const Value *V, X86AddressMode &AM);
130 unsigned TargetMaterializeConstant(const Constant *C);
132 unsigned TargetMaterializeAlloca(const AllocaInst *C);
134 unsigned TargetMaterializeFloatZero(const ConstantFP *CF);
136 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
137 /// computed in an SSE register, not on the X87 floating point stack.
138 bool isScalarFPTypeInSSEReg(EVT VT) const {
139 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
140 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
143 bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false);
145 bool IsMemcpySmall(uint64_t Len);
147 bool TryEmitSmallMemcpy(X86AddressMode DestAM,
148 X86AddressMode SrcAM, uint64_t Len);
151 } // end anonymous namespace.
153 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
154 EVT evt = TLI.getValueType(Ty, /*HandleUnknown=*/true);
155 if (evt == MVT::Other || !evt.isSimple())
156 // Unhandled type. Halt "fast" selection and bail.
159 VT = evt.getSimpleVT();
160 // For now, require SSE/SSE2 for performing floating-point operations,
161 // since x87 requires additional work.
162 if (VT == MVT::f64 && !X86ScalarSSEf64)
164 if (VT == MVT::f32 && !X86ScalarSSEf32)
166 // Similarly, no f80 support yet.
169 // We only handle legal types. For example, on x86-32 the instruction
170 // selector contains all of the 64-bit instructions from x86-64,
171 // under the assumption that i64 won't be used if the target doesn't
173 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
176 #include "X86GenCallingConv.inc"
178 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
179 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
180 /// Return true and the result register by reference if it is possible.
181 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
182 unsigned &ResultReg) {
183 // Get opcode and regclass of the output for the given load instruction.
185 const TargetRegisterClass *RC = NULL;
186 switch (VT.getSimpleVT().SimpleTy) {
187 default: return false;
191 RC = &X86::GR8RegClass;
195 RC = &X86::GR16RegClass;
199 RC = &X86::GR32RegClass;
202 // Must be in x86-64 mode.
204 RC = &X86::GR64RegClass;
207 if (X86ScalarSSEf32) {
208 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
209 RC = &X86::FR32RegClass;
212 RC = &X86::RFP32RegClass;
216 if (X86ScalarSSEf64) {
217 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
218 RC = &X86::FR64RegClass;
221 RC = &X86::RFP64RegClass;
225 // No f80 support yet.
229 ResultReg = createResultReg(RC);
230 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
231 DL, TII.get(Opc), ResultReg), AM);
235 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
236 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
237 /// and a displacement offset, or a GlobalAddress,
238 /// i.e. V. Return true if it is possible.
240 X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg,
241 const X86AddressMode &AM, bool Aligned) {
242 // Get opcode and regclass of the output for the given store instruction.
244 switch (VT.getSimpleVT().SimpleTy) {
245 case MVT::f80: // No f80 support yet.
246 default: return false;
248 // Mask out all but lowest bit.
249 unsigned AndResult = createResultReg(&X86::GR8RegClass);
250 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
251 TII.get(X86::AND8ri), AndResult).addReg(ValReg).addImm(1);
254 // FALLTHROUGH, handling i1 as i8.
255 case MVT::i8: Opc = X86::MOV8mr; break;
256 case MVT::i16: Opc = X86::MOV16mr; break;
257 case MVT::i32: Opc = X86::MOV32mr; break;
258 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
260 Opc = X86ScalarSSEf32 ?
261 (Subtarget->hasAVX() ? X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m;
264 Opc = X86ScalarSSEf64 ?
265 (Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m;
269 Opc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
271 Opc = Subtarget->hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr;
275 Opc = Subtarget->hasAVX() ? X86::VMOVAPDmr : X86::MOVAPDmr;
277 Opc = Subtarget->hasAVX() ? X86::VMOVUPDmr : X86::MOVUPDmr;
284 Opc = Subtarget->hasAVX() ? X86::VMOVDQAmr : X86::MOVDQAmr;
286 Opc = Subtarget->hasAVX() ? X86::VMOVDQUmr : X86::MOVDQUmr;
290 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
291 DL, TII.get(Opc)), AM).addReg(ValReg);
295 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
296 const X86AddressMode &AM, bool Aligned) {
297 // Handle 'null' like i32/i64 0.
298 if (isa<ConstantPointerNull>(Val))
299 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
301 // If this is a store of a simple constant, fold the constant into the store.
302 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
305 switch (VT.getSimpleVT().SimpleTy) {
307 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
308 case MVT::i8: Opc = X86::MOV8mi; break;
309 case MVT::i16: Opc = X86::MOV16mi; break;
310 case MVT::i32: Opc = X86::MOV32mi; break;
312 // Must be a 32-bit sign extended value.
313 if (isInt<32>(CI->getSExtValue()))
314 Opc = X86::MOV64mi32;
319 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
320 DL, TII.get(Opc)), AM)
321 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
327 unsigned ValReg = getRegForValue(Val);
331 return X86FastEmitStore(VT, ValReg, AM, Aligned);
334 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
335 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
336 /// ISD::SIGN_EXTEND).
337 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
338 unsigned Src, EVT SrcVT,
339 unsigned &ResultReg) {
340 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
341 Src, /*TODO: Kill=*/false);
349 bool X86FastISel::handleConstantAddresses(const Value *V, X86AddressMode &AM) {
350 // Handle constant address.
351 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
352 // Can't handle alternate code models yet.
353 if (TM.getCodeModel() != CodeModel::Small)
356 // Can't handle TLS yet.
357 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
358 if (GVar->isThreadLocal())
361 // Can't handle TLS yet, part 2 (this is slightly crazy, but this is how
363 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
364 if (const GlobalVariable *GVar =
365 dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false)))
366 if (GVar->isThreadLocal())
369 // RIP-relative addresses can't have additional register operands, so if
370 // we've already folded stuff into the addressing mode, just force the
371 // global value into its own register, which we can use as the basereg.
372 if (!Subtarget->isPICStyleRIPRel() ||
373 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
374 // Okay, we've committed to selecting this global. Set up the address.
377 // Allow the subtarget to classify the global.
378 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
380 // If this reference is relative to the pic base, set it now.
381 if (isGlobalRelativeToPICBase(GVFlags)) {
382 // FIXME: How do we know Base.Reg is free??
383 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
386 // Unless the ABI requires an extra load, return a direct reference to
388 if (!isGlobalStubReference(GVFlags)) {
389 if (Subtarget->isPICStyleRIPRel()) {
390 // Use rip-relative addressing if we can. Above we verified that the
391 // base and index registers are unused.
392 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
393 AM.Base.Reg = X86::RIP;
395 AM.GVOpFlags = GVFlags;
399 // Ok, we need to do a load from a stub. If we've already loaded from
400 // this stub, reuse the loaded pointer, otherwise emit the load now.
401 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
403 if (I != LocalValueMap.end() && I->second != 0) {
406 // Issue load from stub.
408 const TargetRegisterClass *RC = NULL;
409 X86AddressMode StubAM;
410 StubAM.Base.Reg = AM.Base.Reg;
412 StubAM.GVOpFlags = GVFlags;
414 // Prepare for inserting code in the local-value area.
415 SavePoint SaveInsertPt = enterLocalValueArea();
417 if (TLI.getPointerTy() == MVT::i64) {
419 RC = &X86::GR64RegClass;
421 if (Subtarget->isPICStyleRIPRel())
422 StubAM.Base.Reg = X86::RIP;
425 RC = &X86::GR32RegClass;
428 LoadReg = createResultReg(RC);
429 MachineInstrBuilder LoadMI =
430 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg);
431 addFullAddress(LoadMI, StubAM);
433 // Ok, back to normal mode.
434 leaveLocalValueArea(SaveInsertPt);
436 // Prevent loading GV stub multiple times in same MBB.
437 LocalValueMap[V] = LoadReg;
440 // Now construct the final address. Note that the Disp, Scale,
441 // and Index values may already be set here.
442 AM.Base.Reg = LoadReg;
448 // If all else fails, try to materialize the value in a register.
449 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
450 if (AM.Base.Reg == 0) {
451 AM.Base.Reg = getRegForValue(V);
452 return AM.Base.Reg != 0;
454 if (AM.IndexReg == 0) {
455 assert(AM.Scale == 1 && "Scale with no index!");
456 AM.IndexReg = getRegForValue(V);
457 return AM.IndexReg != 0;
464 /// X86SelectAddress - Attempt to fill in an address from the given value.
466 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
467 SmallVector<const Value *, 32> GEPs;
469 const User *U = NULL;
470 unsigned Opcode = Instruction::UserOp1;
471 if (const Instruction *I = dyn_cast<Instruction>(V)) {
472 // Don't walk into other basic blocks; it's possible we haven't
473 // visited them yet, so the instructions may not yet be assigned
474 // virtual registers.
475 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(V)) ||
476 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
477 Opcode = I->getOpcode();
480 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
481 Opcode = C->getOpcode();
485 if (PointerType *Ty = dyn_cast<PointerType>(V->getType()))
486 if (Ty->getAddressSpace() > 255)
487 // Fast instruction selection doesn't support the special
493 case Instruction::BitCast:
494 // Look past bitcasts.
495 return X86SelectAddress(U->getOperand(0), AM);
497 case Instruction::IntToPtr:
498 // Look past no-op inttoptrs.
499 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
500 return X86SelectAddress(U->getOperand(0), AM);
503 case Instruction::PtrToInt:
504 // Look past no-op ptrtoints.
505 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
506 return X86SelectAddress(U->getOperand(0), AM);
509 case Instruction::Alloca: {
510 // Do static allocas.
511 const AllocaInst *A = cast<AllocaInst>(V);
512 DenseMap<const AllocaInst*, int>::iterator SI =
513 FuncInfo.StaticAllocaMap.find(A);
514 if (SI != FuncInfo.StaticAllocaMap.end()) {
515 AM.BaseType = X86AddressMode::FrameIndexBase;
516 AM.Base.FrameIndex = SI->second;
522 case Instruction::Add: {
523 // Adds of constants are common and easy enough.
524 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
525 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
526 // They have to fit in the 32-bit signed displacement field though.
527 if (isInt<32>(Disp)) {
528 AM.Disp = (uint32_t)Disp;
529 return X86SelectAddress(U->getOperand(0), AM);
535 case Instruction::GetElementPtr: {
536 X86AddressMode SavedAM = AM;
538 // Pattern-match simple GEPs.
539 uint64_t Disp = (int32_t)AM.Disp;
540 unsigned IndexReg = AM.IndexReg;
541 unsigned Scale = AM.Scale;
542 gep_type_iterator GTI = gep_type_begin(U);
543 // Iterate through the indices, folding what we can. Constants can be
544 // folded, and one dynamic index can be handled, if the scale is supported.
545 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
546 i != e; ++i, ++GTI) {
547 const Value *Op = *i;
548 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
549 const StructLayout *SL = TD.getStructLayout(STy);
550 Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue());
554 // A array/variable index is always of the form i*S where S is the
555 // constant scale size. See if we can push the scale into immediates.
556 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
558 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
559 // Constant-offset addressing.
560 Disp += CI->getSExtValue() * S;
563 if (isa<AddOperator>(Op) &&
564 (!isa<Instruction>(Op) ||
565 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
567 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
568 // An add (in the same block) with a constant operand. Fold the
571 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
572 Disp += CI->getSExtValue() * S;
573 // Iterate on the other operand.
574 Op = cast<AddOperator>(Op)->getOperand(0);
578 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
579 (S == 1 || S == 2 || S == 4 || S == 8)) {
580 // Scaled-index addressing.
582 IndexReg = getRegForGEPIndex(Op).first;
588 goto unsupported_gep;
592 // Check for displacement overflow.
593 if (!isInt<32>(Disp))
596 AM.IndexReg = IndexReg;
598 AM.Disp = (uint32_t)Disp;
601 if (const GetElementPtrInst *GEP =
602 dyn_cast<GetElementPtrInst>(U->getOperand(0))) {
603 // Ok, the GEP indices were covered by constant-offset and scaled-index
604 // addressing. Update the address state and move on to examining the base.
607 } else if (X86SelectAddress(U->getOperand(0), AM)) {
611 // If we couldn't merge the gep value into this addr mode, revert back to
612 // our address and just match the value instead of completely failing.
615 for (SmallVectorImpl<const Value *>::reverse_iterator
616 I = GEPs.rbegin(), E = GEPs.rend(); I != E; ++I)
617 if (handleConstantAddresses(*I, AM))
622 // Ok, the GEP indices weren't all covered.
627 return handleConstantAddresses(V, AM);
630 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
632 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
633 const User *U = NULL;
634 unsigned Opcode = Instruction::UserOp1;
635 if (const Instruction *I = dyn_cast<Instruction>(V)) {
636 Opcode = I->getOpcode();
638 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
639 Opcode = C->getOpcode();
645 case Instruction::BitCast:
646 // Look past bitcasts.
647 return X86SelectCallAddress(U->getOperand(0), AM);
649 case Instruction::IntToPtr:
650 // Look past no-op inttoptrs.
651 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
652 return X86SelectCallAddress(U->getOperand(0), AM);
655 case Instruction::PtrToInt:
656 // Look past no-op ptrtoints.
657 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
658 return X86SelectCallAddress(U->getOperand(0), AM);
662 // Handle constant address.
663 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
664 // Can't handle alternate code models yet.
665 if (TM.getCodeModel() != CodeModel::Small)
668 // RIP-relative addresses can't have additional register operands.
669 if (Subtarget->isPICStyleRIPRel() &&
670 (AM.Base.Reg != 0 || AM.IndexReg != 0))
673 // Can't handle DLLImport.
674 if (GV->hasDLLImportLinkage())
678 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
679 if (GVar->isThreadLocal())
682 // Okay, we've committed to selecting this global. Set up the basic address.
685 // No ABI requires an extra load for anything other than DLLImport, which
686 // we rejected above. Return a direct reference to the global.
687 if (Subtarget->isPICStyleRIPRel()) {
688 // Use rip-relative addressing if we can. Above we verified that the
689 // base and index registers are unused.
690 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
691 AM.Base.Reg = X86::RIP;
692 } else if (Subtarget->isPICStyleStubPIC()) {
693 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
694 } else if (Subtarget->isPICStyleGOT()) {
695 AM.GVOpFlags = X86II::MO_GOTOFF;
701 // If all else fails, try to materialize the value in a register.
702 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
703 if (AM.Base.Reg == 0) {
704 AM.Base.Reg = getRegForValue(V);
705 return AM.Base.Reg != 0;
707 if (AM.IndexReg == 0) {
708 assert(AM.Scale == 1 && "Scale with no index!");
709 AM.IndexReg = getRegForValue(V);
710 return AM.IndexReg != 0;
718 /// X86SelectStore - Select and emit code to implement store instructions.
719 bool X86FastISel::X86SelectStore(const Instruction *I) {
720 // Atomic stores need special handling.
721 const StoreInst *S = cast<StoreInst>(I);
726 unsigned SABIAlignment =
727 TD.getABITypeAlignment(S->getValueOperand()->getType());
728 bool Aligned = S->getAlignment() == 0 || S->getAlignment() >= SABIAlignment;
731 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
735 if (!X86SelectAddress(I->getOperand(1), AM))
738 return X86FastEmitStore(VT, I->getOperand(0), AM, Aligned);
741 /// X86SelectRet - Select and emit code to implement ret instructions.
742 bool X86FastISel::X86SelectRet(const Instruction *I) {
743 const ReturnInst *Ret = cast<ReturnInst>(I);
744 const Function &F = *I->getParent()->getParent();
745 const X86MachineFunctionInfo *X86MFInfo =
746 FuncInfo.MF->getInfo<X86MachineFunctionInfo>();
748 if (!FuncInfo.CanLowerReturn)
751 CallingConv::ID CC = F.getCallingConv();
752 if (CC != CallingConv::C &&
753 CC != CallingConv::Fast &&
754 CC != CallingConv::X86_FastCall &&
755 CC != CallingConv::X86_64_SysV)
758 if (Subtarget->isCallingConvWin64(CC))
761 // Don't handle popping bytes on return for now.
762 if (X86MFInfo->getBytesToPopOnReturn() != 0)
765 // fastcc with -tailcallopt is intended to provide a guaranteed
766 // tail call optimization. Fastisel doesn't know how to do that.
767 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt)
770 // Let SDISel handle vararg functions.
774 // Build a list of return value registers.
775 SmallVector<unsigned, 4> RetRegs;
777 if (Ret->getNumOperands() > 0) {
778 SmallVector<ISD::OutputArg, 4> Outs;
779 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
781 // Analyze operands of the call, assigning locations to each operand.
782 SmallVector<CCValAssign, 16> ValLocs;
783 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,
785 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
787 const Value *RV = Ret->getOperand(0);
788 unsigned Reg = getRegForValue(RV);
792 // Only handle a single return value for now.
793 if (ValLocs.size() != 1)
796 CCValAssign &VA = ValLocs[0];
798 // Don't bother handling odd stuff for now.
799 if (VA.getLocInfo() != CCValAssign::Full)
801 // Only handle register returns for now.
805 // The calling-convention tables for x87 returns don't tell
807 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
810 unsigned SrcReg = Reg + VA.getValNo();
811 EVT SrcVT = TLI.getValueType(RV->getType());
812 EVT DstVT = VA.getValVT();
813 // Special handling for extended integers.
814 if (SrcVT != DstVT) {
815 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
818 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
821 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
823 if (SrcVT == MVT::i1) {
824 if (Outs[0].Flags.isSExt())
826 SrcReg = FastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
829 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
831 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
832 SrcReg, /*TODO: Kill=*/false);
836 unsigned DstReg = VA.getLocReg();
837 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
838 // Avoid a cross-class copy. This is very unlikely.
839 if (!SrcRC->contains(DstReg))
841 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
842 DstReg).addReg(SrcReg);
844 // Add register to return instruction.
845 RetRegs.push_back(VA.getLocReg());
848 // The x86-64 ABI for returning structs by value requires that we copy
849 // the sret argument into %rax for the return. We saved the argument into
850 // a virtual register in the entry block, so now we copy the value out
851 // and into %rax. We also do the same with %eax for Win32.
852 if (F.hasStructRetAttr() &&
853 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
854 unsigned Reg = X86MFInfo->getSRetReturnReg();
856 "SRetReturnReg should have been set in LowerFormalArguments()!");
857 unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
858 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
860 RetRegs.push_back(RetReg);
864 MachineInstrBuilder MIB =
865 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
866 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
867 MIB.addReg(RetRegs[i], RegState::Implicit);
871 /// X86SelectLoad - Select and emit code to implement load instructions.
873 bool X86FastISel::X86SelectLoad(const Instruction *I) {
874 // Atomic loads need special handling.
875 if (cast<LoadInst>(I)->isAtomic())
879 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
883 if (!X86SelectAddress(I->getOperand(0), AM))
886 unsigned ResultReg = 0;
887 if (X86FastEmitLoad(VT, AM, ResultReg)) {
888 UpdateValueMap(I, ResultReg);
894 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) {
895 bool HasAVX = Subtarget->hasAVX();
896 bool X86ScalarSSEf32 = Subtarget->hasSSE1();
897 bool X86ScalarSSEf64 = Subtarget->hasSSE2();
899 switch (VT.getSimpleVT().SimpleTy) {
901 case MVT::i8: return X86::CMP8rr;
902 case MVT::i16: return X86::CMP16rr;
903 case MVT::i32: return X86::CMP32rr;
904 case MVT::i64: return X86::CMP64rr;
906 return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0;
908 return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0;
912 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
913 /// of the comparison, return an opcode that works for the compare (e.g.
914 /// CMP32ri) otherwise return 0.
915 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
916 switch (VT.getSimpleVT().SimpleTy) {
917 // Otherwise, we can't fold the immediate into this comparison.
919 case MVT::i8: return X86::CMP8ri;
920 case MVT::i16: return X86::CMP16ri;
921 case MVT::i32: return X86::CMP32ri;
923 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
925 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
926 return X86::CMP64ri32;
931 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
933 unsigned Op0Reg = getRegForValue(Op0);
934 if (Op0Reg == 0) return false;
936 // Handle 'null' like i32/i64 0.
937 if (isa<ConstantPointerNull>(Op1))
938 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
940 // We have two options: compare with register or immediate. If the RHS of
941 // the compare is an immediate that we can fold into this compare, use
942 // CMPri, otherwise use CMPrr.
943 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
944 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
945 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
947 .addImm(Op1C->getSExtValue());
952 unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget);
953 if (CompareOpc == 0) return false;
955 unsigned Op1Reg = getRegForValue(Op1);
956 if (Op1Reg == 0) return false;
957 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc))
964 bool X86FastISel::X86SelectCmp(const Instruction *I) {
965 const CmpInst *CI = cast<CmpInst>(I);
968 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
971 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
973 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
974 switch (CI->getPredicate()) {
975 case CmpInst::FCMP_OEQ: {
976 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
979 unsigned EReg = createResultReg(&X86::GR8RegClass);
980 unsigned NPReg = createResultReg(&X86::GR8RegClass);
981 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
982 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
983 TII.get(X86::SETNPr), NPReg);
984 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
985 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
986 UpdateValueMap(I, ResultReg);
989 case CmpInst::FCMP_UNE: {
990 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
993 unsigned NEReg = createResultReg(&X86::GR8RegClass);
994 unsigned PReg = createResultReg(&X86::GR8RegClass);
995 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETNEr), NEReg);
996 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETPr), PReg);
997 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::OR8rr),ResultReg)
998 .addReg(PReg).addReg(NEReg);
999 UpdateValueMap(I, ResultReg);
1002 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
1003 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
1004 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
1005 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
1006 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
1007 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
1008 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
1009 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
1010 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
1011 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
1012 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
1013 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
1015 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
1016 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
1017 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
1018 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
1019 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
1020 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
1021 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
1022 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
1023 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
1024 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
1029 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
1031 std::swap(Op0, Op1);
1033 // Emit a compare of Op0/Op1.
1034 if (!X86FastEmitCompare(Op0, Op1, VT))
1037 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg);
1038 UpdateValueMap(I, ResultReg);
1042 bool X86FastISel::X86SelectZExt(const Instruction *I) {
1043 EVT DstVT = TLI.getValueType(I->getType());
1044 if (!TLI.isTypeLegal(DstVT))
1047 unsigned ResultReg = getRegForValue(I->getOperand(0));
1051 // Handle zero-extension from i1 to i8, which is common.
1052 MVT SrcVT = TLI.getSimpleValueType(I->getOperand(0)->getType());
1053 if (SrcVT.SimpleTy == MVT::i1) {
1054 // Set the high bits to zero.
1055 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
1062 if (DstVT == MVT::i64) {
1063 // Handle extension to 64-bits via sub-register shenanigans.
1066 switch (SrcVT.SimpleTy) {
1067 case MVT::i8: MovInst = X86::MOVZX32rr8; break;
1068 case MVT::i16: MovInst = X86::MOVZX32rr16; break;
1069 case MVT::i32: MovInst = X86::MOV32rr; break;
1070 default: llvm_unreachable("Unexpected zext to i64 source type");
1073 unsigned Result32 = createResultReg(&X86::GR32RegClass);
1074 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovInst), Result32)
1077 ResultReg = createResultReg(&X86::GR64RegClass);
1078 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::SUBREG_TO_REG),
1080 .addImm(0).addReg(Result32).addImm(X86::sub_32bit);
1081 } else if (DstVT != MVT::i8) {
1082 ResultReg = FastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND,
1083 ResultReg, /*Kill=*/true);
1088 UpdateValueMap(I, ResultReg);
1093 bool X86FastISel::X86SelectBranch(const Instruction *I) {
1094 // Unconditional branches are selected by tablegen-generated code.
1095 // Handle a conditional branch.
1096 const BranchInst *BI = cast<BranchInst>(I);
1097 MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1098 MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1100 // Fold the common case of a conditional branch with a comparison
1101 // in the same block (values defined on other blocks may not have
1102 // initialized registers).
1103 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1104 if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
1105 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
1107 // Try to take advantage of fallthrough opportunities.
1108 CmpInst::Predicate Predicate = CI->getPredicate();
1109 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
1110 std::swap(TrueMBB, FalseMBB);
1111 Predicate = CmpInst::getInversePredicate(Predicate);
1114 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
1115 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
1117 switch (Predicate) {
1118 case CmpInst::FCMP_OEQ:
1119 std::swap(TrueMBB, FalseMBB);
1120 Predicate = CmpInst::FCMP_UNE;
1122 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1123 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1124 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1125 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
1126 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
1127 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1128 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
1129 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
1130 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1131 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
1132 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
1133 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1134 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1136 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1137 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1138 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1139 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1140 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1141 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1142 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
1143 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
1144 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
1145 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
1150 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
1152 std::swap(Op0, Op1);
1154 // Emit a compare of the LHS and RHS, setting the flags.
1155 if (!X86FastEmitCompare(Op0, Op1, VT))
1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc))
1161 if (Predicate == CmpInst::FCMP_UNE) {
1162 // X86 requires a second branch to handle UNE (and OEQ,
1163 // which is mapped to UNE above).
1164 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
1168 FastEmitBranch(FalseMBB, DL);
1169 FuncInfo.MBB->addSuccessor(TrueMBB);
1172 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1173 // Handle things like "%cond = trunc i32 %X to i1 / br i1 %cond", which
1174 // typically happen for _Bool and C++ bools.
1176 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1177 isTypeLegal(TI->getOperand(0)->getType(), SourceVT)) {
1178 unsigned TestOpc = 0;
1179 switch (SourceVT.SimpleTy) {
1181 case MVT::i8: TestOpc = X86::TEST8ri; break;
1182 case MVT::i16: TestOpc = X86::TEST16ri; break;
1183 case MVT::i32: TestOpc = X86::TEST32ri; break;
1184 case MVT::i64: TestOpc = X86::TEST64ri32; break;
1187 unsigned OpReg = getRegForValue(TI->getOperand(0));
1188 if (OpReg == 0) return false;
1189 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TestOpc))
1190 .addReg(OpReg).addImm(1);
1192 unsigned JmpOpc = X86::JNE_4;
1193 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
1194 std::swap(TrueMBB, FalseMBB);
1198 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(JmpOpc))
1200 FastEmitBranch(FalseMBB, DL);
1201 FuncInfo.MBB->addSuccessor(TrueMBB);
1207 // Otherwise do a clumsy setcc and re-test it.
1208 // Note that i1 essentially gets ANY_EXTEND'ed to i8 where it isn't used
1209 // in an explicit cast, so make sure to handle that correctly.
1210 unsigned OpReg = getRegForValue(BI->getCondition());
1211 if (OpReg == 0) return false;
1213 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
1214 .addReg(OpReg).addImm(1);
1215 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1217 FastEmitBranch(FalseMBB, DL);
1218 FuncInfo.MBB->addSuccessor(TrueMBB);
1222 bool X86FastISel::X86SelectShift(const Instruction *I) {
1223 unsigned CReg = 0, OpReg = 0;
1224 const TargetRegisterClass *RC = NULL;
1225 if (I->getType()->isIntegerTy(8)) {
1227 RC = &X86::GR8RegClass;
1228 switch (I->getOpcode()) {
1229 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1230 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1231 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1232 default: return false;
1234 } else if (I->getType()->isIntegerTy(16)) {
1236 RC = &X86::GR16RegClass;
1237 switch (I->getOpcode()) {
1238 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1239 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1240 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1241 default: return false;
1243 } else if (I->getType()->isIntegerTy(32)) {
1245 RC = &X86::GR32RegClass;
1246 switch (I->getOpcode()) {
1247 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1248 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1249 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1250 default: return false;
1252 } else if (I->getType()->isIntegerTy(64)) {
1254 RC = &X86::GR64RegClass;
1255 switch (I->getOpcode()) {
1256 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1257 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1258 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1259 default: return false;
1266 if (!isTypeLegal(I->getType(), VT))
1269 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1270 if (Op0Reg == 0) return false;
1272 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1273 if (Op1Reg == 0) return false;
1274 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1275 CReg).addReg(Op1Reg);
1277 // The shift instruction uses X86::CL. If we defined a super-register
1278 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1279 if (CReg != X86::CL)
1280 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1281 TII.get(TargetOpcode::KILL), X86::CL)
1282 .addReg(CReg, RegState::Kill);
1284 unsigned ResultReg = createResultReg(RC);
1285 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg)
1287 UpdateValueMap(I, ResultReg);
1291 bool X86FastISel::X86SelectDivRem(const Instruction *I) {
1292 const static unsigned NumTypes = 4; // i8, i16, i32, i64
1293 const static unsigned NumOps = 4; // SDiv, SRem, UDiv, URem
1294 const static bool S = true; // IsSigned
1295 const static bool U = false; // !IsSigned
1296 const static unsigned Copy = TargetOpcode::COPY;
1297 // For the X86 DIV/IDIV instruction, in most cases the dividend
1298 // (numerator) must be in a specific register pair highreg:lowreg,
1299 // producing the quotient in lowreg and the remainder in highreg.
1300 // For most data types, to set up the instruction, the dividend is
1301 // copied into lowreg, and lowreg is sign-extended or zero-extended
1302 // into highreg. The exception is i8, where the dividend is defined
1303 // as a single register rather than a register pair, and we
1304 // therefore directly sign-extend or zero-extend the dividend into
1305 // lowreg, instead of copying, and ignore the highreg.
1306 const static struct DivRemEntry {
1307 // The following portion depends only on the data type.
1308 const TargetRegisterClass *RC;
1309 unsigned LowInReg; // low part of the register pair
1310 unsigned HighInReg; // high part of the register pair
1311 // The following portion depends on both the data type and the operation.
1312 struct DivRemResult {
1313 unsigned OpDivRem; // The specific DIV/IDIV opcode to use.
1314 unsigned OpSignExtend; // Opcode for sign-extending lowreg into
1315 // highreg, or copying a zero into highreg.
1316 unsigned OpCopy; // Opcode for copying dividend into lowreg, or
1317 // zero/sign-extending into lowreg for i8.
1318 unsigned DivRemResultReg; // Register containing the desired result.
1319 bool IsOpSigned; // Whether to use signed or unsigned form.
1320 } ResultTable[NumOps];
1321 } OpTable[NumTypes] = {
1322 { &X86::GR8RegClass, X86::AX, 0, {
1323 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S }, // SDiv
1324 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S }, // SRem
1325 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U }, // UDiv
1326 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U }, // URem
1329 { &X86::GR16RegClass, X86::AX, X86::DX, {
1330 { X86::IDIV16r, X86::CWD, Copy, X86::AX, S }, // SDiv
1331 { X86::IDIV16r, X86::CWD, Copy, X86::DX, S }, // SRem
1332 { X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U }, // UDiv
1333 { X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U }, // URem
1336 { &X86::GR32RegClass, X86::EAX, X86::EDX, {
1337 { X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S }, // SDiv
1338 { X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S }, // SRem
1339 { X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv
1340 { X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U }, // URem
1343 { &X86::GR64RegClass, X86::RAX, X86::RDX, {
1344 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv
1345 { X86::IDIV64r, X86::CQO, Copy, X86::RDX, S }, // SRem
1346 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv
1347 { X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U }, // URem
1353 if (!isTypeLegal(I->getType(), VT))
1356 unsigned TypeIndex, OpIndex;
1357 switch (VT.SimpleTy) {
1358 default: return false;
1359 case MVT::i8: TypeIndex = 0; break;
1360 case MVT::i16: TypeIndex = 1; break;
1361 case MVT::i32: TypeIndex = 2; break;
1362 case MVT::i64: TypeIndex = 3;
1363 if (!Subtarget->is64Bit())
1368 switch (I->getOpcode()) {
1369 default: llvm_unreachable("Unexpected div/rem opcode");
1370 case Instruction::SDiv: OpIndex = 0; break;
1371 case Instruction::SRem: OpIndex = 1; break;
1372 case Instruction::UDiv: OpIndex = 2; break;
1373 case Instruction::URem: OpIndex = 3; break;
1376 const DivRemEntry &TypeEntry = OpTable[TypeIndex];
1377 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
1378 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1381 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1385 // Move op0 into low-order input register.
1386 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1387 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg);
1388 // Zero-extend or sign-extend into high-order input register.
1389 if (OpEntry.OpSignExtend) {
1390 if (OpEntry.IsOpSigned)
1391 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1392 TII.get(OpEntry.OpSignExtend));
1394 unsigned Zero32 = createResultReg(&X86::GR32RegClass);
1395 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1396 TII.get(X86::MOV32r0), Zero32);
1398 // Copy the zero into the appropriate sub/super/identical physical
1399 // register. Unfortunately the operations needed are not uniform enough to
1400 // fit neatly into the table above.
1401 if (VT.SimpleTy == MVT::i16) {
1402 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1403 TII.get(Copy), TypeEntry.HighInReg)
1404 .addReg(Zero32, 0, X86::sub_16bit);
1405 } else if (VT.SimpleTy == MVT::i32) {
1406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1407 TII.get(Copy), TypeEntry.HighInReg)
1409 } else if (VT.SimpleTy == MVT::i64) {
1410 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1411 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg)
1412 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
1416 // Generate the DIV/IDIV instruction.
1417 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1418 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg);
1419 // For i8 remainder, we can't reference AH directly, as we'll end
1420 // up with bogus copies like %R9B = COPY %AH. Reference AX
1421 // instead to prevent AH references in a REX instruction.
1423 // The current assumption of the fast register allocator is that isel
1424 // won't generate explicit references to the GPR8_NOREX registers. If
1425 // the allocator and/or the backend get enhanced to be more robust in
1426 // that regard, this can be, and should be, removed.
1427 unsigned ResultReg = 0;
1428 if ((I->getOpcode() == Instruction::SRem ||
1429 I->getOpcode() == Instruction::URem) &&
1430 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) {
1431 unsigned SourceSuperReg = createResultReg(&X86::GR16RegClass);
1432 unsigned ResultSuperReg = createResultReg(&X86::GR16RegClass);
1433 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1434 TII.get(Copy), SourceSuperReg).addReg(X86::AX);
1436 // Shift AX right by 8 bits instead of using AH.
1437 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SHR16ri),
1438 ResultSuperReg).addReg(SourceSuperReg).addImm(8);
1440 // Now reference the 8-bit subreg of the result.
1441 ResultReg = FastEmitInst_extractsubreg(MVT::i8, ResultSuperReg,
1442 /*Kill=*/true, X86::sub_8bit);
1444 // Copy the result out of the physreg if we haven't already.
1446 ResultReg = createResultReg(TypeEntry.RC);
1447 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Copy), ResultReg)
1448 .addReg(OpEntry.DivRemResultReg);
1450 UpdateValueMap(I, ResultReg);
1455 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1457 if (!isTypeLegal(I->getType(), VT))
1460 // We only use cmov here, if we don't have a cmov instruction bail.
1461 if (!Subtarget->hasCMov()) return false;
1464 const TargetRegisterClass *RC = NULL;
1465 if (VT == MVT::i16) {
1466 Opc = X86::CMOVE16rr;
1467 RC = &X86::GR16RegClass;
1468 } else if (VT == MVT::i32) {
1469 Opc = X86::CMOVE32rr;
1470 RC = &X86::GR32RegClass;
1471 } else if (VT == MVT::i64) {
1472 Opc = X86::CMOVE64rr;
1473 RC = &X86::GR64RegClass;
1478 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1479 if (Op0Reg == 0) return false;
1480 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1481 if (Op1Reg == 0) return false;
1482 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1483 if (Op2Reg == 0) return false;
1485 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1486 .addReg(Op0Reg).addReg(Op0Reg);
1487 unsigned ResultReg = createResultReg(RC);
1488 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1489 .addReg(Op1Reg).addReg(Op2Reg);
1490 UpdateValueMap(I, ResultReg);
1494 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
1495 // fpext from float to double.
1496 if (X86ScalarSSEf64 &&
1497 I->getType()->isDoubleTy()) {
1498 const Value *V = I->getOperand(0);
1499 if (V->getType()->isFloatTy()) {
1500 unsigned OpReg = getRegForValue(V);
1501 if (OpReg == 0) return false;
1502 unsigned ResultReg = createResultReg(&X86::FR64RegClass);
1503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1504 TII.get(X86::CVTSS2SDrr), ResultReg)
1506 UpdateValueMap(I, ResultReg);
1514 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
1515 if (X86ScalarSSEf64) {
1516 if (I->getType()->isFloatTy()) {
1517 const Value *V = I->getOperand(0);
1518 if (V->getType()->isDoubleTy()) {
1519 unsigned OpReg = getRegForValue(V);
1520 if (OpReg == 0) return false;
1521 unsigned ResultReg = createResultReg(&X86::FR32RegClass);
1522 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1523 TII.get(X86::CVTSD2SSrr), ResultReg)
1525 UpdateValueMap(I, ResultReg);
1534 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
1535 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1536 EVT DstVT = TLI.getValueType(I->getType());
1538 // This code only handles truncation to byte.
1539 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1541 if (!TLI.isTypeLegal(SrcVT))
1544 unsigned InputReg = getRegForValue(I->getOperand(0));
1546 // Unhandled operand. Halt "fast" selection and bail.
1549 if (SrcVT == MVT::i8) {
1550 // Truncate from i8 to i1; no code needed.
1551 UpdateValueMap(I, InputReg);
1555 if (!Subtarget->is64Bit()) {
1556 // If we're on x86-32; we can't extract an i8 from a general register.
1557 // First issue a copy to GR16_ABCD or GR32_ABCD.
1558 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) ?
1559 (const TargetRegisterClass*)&X86::GR16_ABCDRegClass :
1560 (const TargetRegisterClass*)&X86::GR32_ABCDRegClass;
1561 unsigned CopyReg = createResultReg(CopyRC);
1562 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1563 CopyReg).addReg(InputReg);
1567 // Issue an extract_subreg.
1568 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1569 InputReg, /*Kill=*/true,
1574 UpdateValueMap(I, ResultReg);
1578 bool X86FastISel::IsMemcpySmall(uint64_t Len) {
1579 return Len <= (Subtarget->is64Bit() ? 32 : 16);
1582 bool X86FastISel::TryEmitSmallMemcpy(X86AddressMode DestAM,
1583 X86AddressMode SrcAM, uint64_t Len) {
1585 // Make sure we don't bloat code by inlining very large memcpy's.
1586 if (!IsMemcpySmall(Len))
1589 bool i64Legal = Subtarget->is64Bit();
1591 // We don't care about alignment here since we just emit integer accesses.
1594 if (Len >= 8 && i64Legal)
1605 bool RV = X86FastEmitLoad(VT, SrcAM, Reg);
1606 RV &= X86FastEmitStore(VT, Reg, DestAM);
1607 assert(RV && "Failed to emit load or store??");
1609 unsigned Size = VT.getSizeInBits()/8;
1611 DestAM.Disp += Size;
1618 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
1619 // FIXME: Handle more intrinsics.
1620 switch (I.getIntrinsicID()) {
1621 default: return false;
1622 case Intrinsic::memcpy: {
1623 const MemCpyInst &MCI = cast<MemCpyInst>(I);
1624 // Don't handle volatile or variable length memcpys.
1625 if (MCI.isVolatile())
1628 if (isa<ConstantInt>(MCI.getLength())) {
1629 // Small memcpy's are common enough that we want to do them
1630 // without a call if possible.
1631 uint64_t Len = cast<ConstantInt>(MCI.getLength())->getZExtValue();
1632 if (IsMemcpySmall(Len)) {
1633 X86AddressMode DestAM, SrcAM;
1634 if (!X86SelectAddress(MCI.getRawDest(), DestAM) ||
1635 !X86SelectAddress(MCI.getRawSource(), SrcAM))
1637 TryEmitSmallMemcpy(DestAM, SrcAM, Len);
1642 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32;
1643 if (!MCI.getLength()->getType()->isIntegerTy(SizeWidth))
1646 if (MCI.getSourceAddressSpace() > 255 || MCI.getDestAddressSpace() > 255)
1649 return DoSelectCall(&I, "memcpy");
1651 case Intrinsic::memset: {
1652 const MemSetInst &MSI = cast<MemSetInst>(I);
1654 if (MSI.isVolatile())
1657 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32;
1658 if (!MSI.getLength()->getType()->isIntegerTy(SizeWidth))
1661 if (MSI.getDestAddressSpace() > 255)
1664 return DoSelectCall(&I, "memset");
1666 case Intrinsic::stackprotector: {
1667 // Emit code to store the stack guard onto the stack.
1668 EVT PtrTy = TLI.getPointerTy();
1670 const Value *Op1 = I.getArgOperand(0); // The guard's value.
1671 const AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
1673 // Grab the frame index.
1675 if (!X86SelectAddress(Slot, AM)) return false;
1676 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
1679 case Intrinsic::dbg_declare: {
1680 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I);
1682 assert(DI->getAddress() && "Null address should be checked earlier!");
1683 if (!X86SelectAddress(DI->getAddress(), AM))
1685 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1686 // FIXME may need to add RegState::Debug to any registers produced,
1687 // although ESP/EBP should be the only ones at the moment.
1688 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM).
1689 addImm(0).addMetadata(DI->getVariable());
1692 case Intrinsic::trap: {
1693 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1696 case Intrinsic::sadd_with_overflow:
1697 case Intrinsic::uadd_with_overflow: {
1698 // FIXME: Should fold immediates.
1700 // Replace "add with overflow" intrinsics with an "add" instruction followed
1701 // by a seto/setc instruction.
1702 const Function *Callee = I.getCalledFunction();
1704 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1707 if (!isTypeLegal(RetTy, VT))
1710 const Value *Op1 = I.getArgOperand(0);
1711 const Value *Op2 = I.getArgOperand(1);
1712 unsigned Reg1 = getRegForValue(Op1);
1713 unsigned Reg2 = getRegForValue(Op2);
1715 if (Reg1 == 0 || Reg2 == 0)
1716 // FIXME: Handle values *not* in registers.
1722 else if (VT == MVT::i64)
1727 // The call to CreateRegs builds two sequential registers, to store the
1728 // both the returned values.
1729 unsigned ResultReg = FuncInfo.CreateRegs(I.getType());
1730 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg)
1731 .addReg(Reg1).addReg(Reg2);
1733 unsigned Opc = X86::SETBr;
1734 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1736 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg+1);
1738 UpdateValueMap(&I, ResultReg, 2);
1744 bool X86FastISel::FastLowerArguments() {
1745 if (!FuncInfo.CanLowerReturn)
1748 const Function *F = FuncInfo.Fn;
1752 CallingConv::ID CC = F->getCallingConv();
1753 if (CC != CallingConv::C)
1756 if (Subtarget->isCallingConvWin64(CC))
1759 if (!Subtarget->is64Bit())
1762 // Only handle simple cases. i.e. Up to 6 i32/i64 scalar arguments.
1764 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1765 I != E; ++I, ++Idx) {
1769 if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
1770 F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
1771 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
1772 F->getAttributes().hasAttribute(Idx, Attribute::Nest))
1775 Type *ArgTy = I->getType();
1776 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
1779 EVT ArgVT = TLI.getValueType(ArgTy);
1780 if (!ArgVT.isSimple()) return false;
1781 switch (ArgVT.getSimpleVT().SimpleTy) {
1790 static const uint16_t GPR32ArgRegs[] = {
1791 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1793 static const uint16_t GPR64ArgRegs[] = {
1794 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
1798 const TargetRegisterClass *RC32 = TLI.getRegClassFor(MVT::i32);
1799 const TargetRegisterClass *RC64 = TLI.getRegClassFor(MVT::i64);
1800 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1801 I != E; ++I, ++Idx) {
1802 bool is32Bit = TLI.getValueType(I->getType()) == MVT::i32;
1803 const TargetRegisterClass *RC = is32Bit ? RC32 : RC64;
1804 unsigned SrcReg = is32Bit ? GPR32ArgRegs[Idx] : GPR64ArgRegs[Idx];
1805 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
1806 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1807 // Without this, EmitLiveInCopies may eliminate the livein if its only
1808 // use is a bitcast (which isn't turned into an instruction).
1809 unsigned ResultReg = createResultReg(RC);
1810 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1811 ResultReg).addReg(DstReg, getKillRegState(true));
1812 UpdateValueMap(I, ResultReg);
1817 bool X86FastISel::X86SelectCall(const Instruction *I) {
1818 const CallInst *CI = cast<CallInst>(I);
1819 const Value *Callee = CI->getCalledValue();
1821 // Can't handle inline asm yet.
1822 if (isa<InlineAsm>(Callee))
1825 // Handle intrinsic calls.
1826 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1827 return X86VisitIntrinsicCall(*II);
1829 // Allow SelectionDAG isel to handle tail calls.
1830 if (cast<CallInst>(I)->isTailCall())
1833 return DoSelectCall(I, 0);
1836 static unsigned computeBytesPoppedByCallee(const X86Subtarget &Subtarget,
1837 const ImmutableCallSite &CS) {
1838 if (Subtarget.is64Bit())
1840 if (Subtarget.isTargetWindows())
1842 CallingConv::ID CC = CS.getCallingConv();
1843 if (CC == CallingConv::Fast || CC == CallingConv::GHC)
1845 if (!CS.paramHasAttr(1, Attribute::StructRet))
1847 if (CS.paramHasAttr(1, Attribute::InReg))
1852 // Select either a call, or an llvm.memcpy/memmove/memset intrinsic
1853 bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
1854 const CallInst *CI = cast<CallInst>(I);
1855 const Value *Callee = CI->getCalledValue();
1857 // Handle only C and fastcc calling conventions for now.
1858 ImmutableCallSite CS(CI);
1859 CallingConv::ID CC = CS.getCallingConv();
1860 bool isWin64 = Subtarget->isCallingConvWin64(CC);
1861 if (CC != CallingConv::C && CC != CallingConv::Fast &&
1862 CC != CallingConv::X86_FastCall && CC != CallingConv::X86_64_Win64 &&
1863 CC != CallingConv::X86_64_SysV)
1866 // fastcc with -tailcallopt is intended to provide a guaranteed
1867 // tail call optimization. Fastisel doesn't know how to do that.
1868 if (CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt)
1871 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1872 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1873 bool isVarArg = FTy->isVarArg();
1875 // Don't know how to handle Win64 varargs yet. Nothing special needed for
1876 // x86-32. Special handling for x86-64 is implemented.
1877 if (isVarArg && isWin64)
1880 // Fast-isel doesn't know about callee-pop yet.
1881 if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg,
1882 TM.Options.GuaranteedTailCallOpt))
1885 // Check whether the function can return without sret-demotion.
1886 SmallVector<ISD::OutputArg, 4> Outs;
1887 GetReturnInfo(I->getType(), CS.getAttributes(), Outs, TLI);
1888 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
1889 *FuncInfo.MF, FTy->isVarArg(),
1890 Outs, FTy->getContext());
1891 if (!CanLowerReturn)
1894 // Materialize callee address in a register. FIXME: GV address can be
1895 // handled with a CALLpcrel32 instead.
1896 X86AddressMode CalleeAM;
1897 if (!X86SelectCallAddress(Callee, CalleeAM))
1899 unsigned CalleeOp = 0;
1900 const GlobalValue *GV = 0;
1901 if (CalleeAM.GV != 0) {
1903 } else if (CalleeAM.Base.Reg != 0) {
1904 CalleeOp = CalleeAM.Base.Reg;
1908 // Deal with call operands first.
1909 SmallVector<const Value *, 8> ArgVals;
1910 SmallVector<unsigned, 8> Args;
1911 SmallVector<MVT, 8> ArgVTs;
1912 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1913 unsigned arg_size = CS.arg_size();
1914 Args.reserve(arg_size);
1915 ArgVals.reserve(arg_size);
1916 ArgVTs.reserve(arg_size);
1917 ArgFlags.reserve(arg_size);
1918 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1920 // If we're lowering a mem intrinsic instead of a regular call, skip the
1921 // last two arguments, which should not passed to the underlying functions.
1922 if (MemIntName && e-i <= 2)
1925 ISD::ArgFlagsTy Flags;
1926 unsigned AttrInd = i - CS.arg_begin() + 1;
1927 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1929 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1932 if (CS.paramHasAttr(AttrInd, Attribute::ByVal)) {
1933 PointerType *Ty = cast<PointerType>(ArgVal->getType());
1934 Type *ElementTy = Ty->getElementType();
1935 unsigned FrameSize = TD.getTypeAllocSize(ElementTy);
1936 unsigned FrameAlign = CS.getParamAlignment(AttrInd);
1938 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
1940 Flags.setByValSize(FrameSize);
1941 Flags.setByValAlign(FrameAlign);
1942 if (!IsMemcpySmall(FrameSize))
1946 if (CS.paramHasAttr(AttrInd, Attribute::InReg))
1948 if (CS.paramHasAttr(AttrInd, Attribute::Nest))
1951 // If this is an i1/i8/i16 argument, promote to i32 to avoid an extra
1952 // instruction. This is safe because it is common to all fastisel supported
1953 // calling conventions on x86.
1954 if (ConstantInt *CI = dyn_cast<ConstantInt>(ArgVal)) {
1955 if (CI->getBitWidth() == 1 || CI->getBitWidth() == 8 ||
1956 CI->getBitWidth() == 16) {
1958 ArgVal = ConstantExpr::getSExt(CI,Type::getInt32Ty(CI->getContext()));
1960 ArgVal = ConstantExpr::getZExt(CI,Type::getInt32Ty(CI->getContext()));
1966 // Passing bools around ends up doing a trunc to i1 and passing it.
1967 // Codegen this as an argument + "and 1".
1968 if (ArgVal->getType()->isIntegerTy(1) && isa<TruncInst>(ArgVal) &&
1969 cast<TruncInst>(ArgVal)->getParent() == I->getParent() &&
1970 ArgVal->hasOneUse()) {
1971 ArgVal = cast<TruncInst>(ArgVal)->getOperand(0);
1972 ArgReg = getRegForValue(ArgVal);
1973 if (ArgReg == 0) return false;
1976 if (!isTypeLegal(ArgVal->getType(), ArgVT)) return false;
1978 ArgReg = FastEmit_ri(ArgVT, ArgVT, ISD::AND, ArgReg,
1979 ArgVal->hasOneUse(), 1);
1981 ArgReg = getRegForValue(ArgVal);
1984 if (ArgReg == 0) return false;
1986 Type *ArgTy = ArgVal->getType();
1988 if (!isTypeLegal(ArgTy, ArgVT))
1990 if (ArgVT == MVT::x86mmx)
1992 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1993 Flags.setOrigAlign(OriginalAlignment);
1995 Args.push_back(ArgReg);
1996 ArgVals.push_back(ArgVal);
1997 ArgVTs.push_back(ArgVT);
1998 ArgFlags.push_back(Flags);
2001 // Analyze operands of the call, assigning locations to each operand.
2002 SmallVector<CCValAssign, 16> ArgLocs;
2003 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs,
2004 I->getParent()->getContext());
2006 // Allocate shadow area for Win64
2008 CCInfo.AllocateStack(32, 8);
2010 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_X86);
2012 // Get a count of how many bytes are to be pushed on the stack.
2013 unsigned NumBytes = CCInfo.getNextStackOffset();
2015 // Issue CALLSEQ_START
2016 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2017 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
2020 // Process argument: walk the register/memloc assignments, inserting
2022 SmallVector<unsigned, 4> RegArgs;
2023 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2024 CCValAssign &VA = ArgLocs[i];
2025 unsigned Arg = Args[VA.getValNo()];
2026 EVT ArgVT = ArgVTs[VA.getValNo()];
2028 // Promote the value if needed.
2029 switch (VA.getLocInfo()) {
2030 case CCValAssign::Full: break;
2031 case CCValAssign::SExt: {
2032 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
2033 "Unexpected extend");
2034 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
2036 assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
2037 ArgVT = VA.getLocVT();
2040 case CCValAssign::ZExt: {
2041 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
2042 "Unexpected extend");
2043 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
2045 assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
2046 ArgVT = VA.getLocVT();
2049 case CCValAssign::AExt: {
2050 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
2051 "Unexpected extend");
2052 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
2055 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
2058 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
2061 assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
2062 ArgVT = VA.getLocVT();
2065 case CCValAssign::BCvt: {
2066 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT(),
2067 ISD::BITCAST, Arg, /*TODO: Kill=*/false);
2068 assert(BC != 0 && "Failed to emit a bitcast!");
2070 ArgVT = VA.getLocVT();
2073 case CCValAssign::VExt:
2074 // VExt has not been implemented, so this should be impossible to reach
2075 // for now. However, fallback to Selection DAG isel once implemented.
2077 case CCValAssign::Indirect:
2078 // FIXME: Indirect doesn't need extending, but fast-isel doesn't fully
2083 if (VA.isRegLoc()) {
2084 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2085 VA.getLocReg()).addReg(Arg);
2086 RegArgs.push_back(VA.getLocReg());
2088 unsigned LocMemOffset = VA.getLocMemOffset();
2090 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo*>(
2091 getTargetMachine()->getRegisterInfo());
2092 AM.Base.Reg = RegInfo->getStackRegister();
2093 AM.Disp = LocMemOffset;
2094 const Value *ArgVal = ArgVals[VA.getValNo()];
2095 ISD::ArgFlagsTy Flags = ArgFlags[VA.getValNo()];
2097 if (Flags.isByVal()) {
2098 X86AddressMode SrcAM;
2099 SrcAM.Base.Reg = Arg;
2100 bool Res = TryEmitSmallMemcpy(AM, SrcAM, Flags.getByValSize());
2101 assert(Res && "memcpy length already checked!"); (void)Res;
2102 } else if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) {
2103 // If this is a really simple value, emit this with the Value* version
2104 // of X86FastEmitStore. If it isn't simple, we don't want to do this,
2105 // as it can cause us to reevaluate the argument.
2106 if (!X86FastEmitStore(ArgVT, ArgVal, AM))
2109 if (!X86FastEmitStore(ArgVT, Arg, AM))
2115 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2117 if (Subtarget->isPICStyleGOT()) {
2118 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
2119 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2120 X86::EBX).addReg(Base);
2123 if (Subtarget->is64Bit() && isVarArg && !isWin64) {
2124 // Count the number of XMM registers allocated.
2125 static const uint16_t XMMArgRegs[] = {
2126 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2127 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2129 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2130 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::MOV8ri),
2131 X86::AL).addImm(NumXMMRegs);
2135 MachineInstrBuilder MIB;
2137 // Register-indirect call.
2139 if (Subtarget->is64Bit())
2140 CallOpc = X86::CALL64r;
2142 CallOpc = X86::CALL32r;
2143 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
2148 assert(GV && "Not a direct call");
2150 if (Subtarget->is64Bit())
2151 CallOpc = X86::CALL64pcrel32;
2153 CallOpc = X86::CALLpcrel32;
2155 // See if we need any target-specific flags on the GV operand.
2156 unsigned char OpFlags = 0;
2158 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2159 // external symbols most go through the PLT in PIC mode. If the symbol
2160 // has hidden or protected visibility, or if it is static or local, then
2161 // we don't need to use the PLT - we can directly call it.
2162 if (Subtarget->isTargetELF() &&
2163 TM.getRelocationModel() == Reloc::PIC_ &&
2164 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2165 OpFlags = X86II::MO_PLT;
2166 } else if (Subtarget->isPICStyleStubAny() &&
2167 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2168 (!Subtarget->getTargetTriple().isMacOSX() ||
2169 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2170 // PC-relative references to external symbols should go through $stub,
2171 // unless we're building with the leopard linker or later, which
2172 // automatically synthesizes these stubs.
2173 OpFlags = X86II::MO_DARWIN_STUB;
2177 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc));
2179 MIB.addExternalSymbol(MemIntName, OpFlags);
2181 MIB.addGlobalAddress(GV, 0, OpFlags);
2184 // Add a register mask with the call-preserved registers.
2185 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2186 MIB.addRegMask(TRI.getCallPreservedMask(CS.getCallingConv()));
2188 // Add an implicit use GOT pointer in EBX.
2189 if (Subtarget->isPICStyleGOT())
2190 MIB.addReg(X86::EBX, RegState::Implicit);
2192 if (Subtarget->is64Bit() && isVarArg && !isWin64)
2193 MIB.addReg(X86::AL, RegState::Implicit);
2195 // Add implicit physical register uses to the call.
2196 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2197 MIB.addReg(RegArgs[i], RegState::Implicit);
2199 // Issue CALLSEQ_END
2200 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2201 const unsigned NumBytesCallee = computeBytesPoppedByCallee(*Subtarget, CS);
2202 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
2203 .addImm(NumBytes).addImm(NumBytesCallee);
2205 // Build info for return calling conv lowering code.
2206 // FIXME: This is practically a copy-paste from TargetLowering::LowerCallTo.
2207 SmallVector<ISD::InputArg, 32> Ins;
2208 SmallVector<EVT, 4> RetTys;
2209 ComputeValueVTs(TLI, I->getType(), RetTys);
2210 for (unsigned i = 0, e = RetTys.size(); i != e; ++i) {
2212 MVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT);
2213 unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT);
2214 for (unsigned j = 0; j != NumRegs; ++j) {
2215 ISD::InputArg MyFlags;
2216 MyFlags.VT = RegisterVT;
2217 MyFlags.Used = !CS.getInstruction()->use_empty();
2218 if (CS.paramHasAttr(0, Attribute::SExt))
2219 MyFlags.Flags.setSExt();
2220 if (CS.paramHasAttr(0, Attribute::ZExt))
2221 MyFlags.Flags.setZExt();
2222 if (CS.paramHasAttr(0, Attribute::InReg))
2223 MyFlags.Flags.setInReg();
2224 Ins.push_back(MyFlags);
2228 // Now handle call return values.
2229 SmallVector<unsigned, 4> UsedRegs;
2230 SmallVector<CCValAssign, 16> RVLocs;
2231 CCState CCRetInfo(CC, false, *FuncInfo.MF, TM, RVLocs,
2232 I->getParent()->getContext());
2233 unsigned ResultReg = FuncInfo.CreateRegs(I->getType());
2234 CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86);
2235 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2236 EVT CopyVT = RVLocs[i].getValVT();
2237 unsigned CopyReg = ResultReg + i;
2239 // If this is a call to a function that returns an fp value on the x87 fp
2240 // stack, but where we prefer to use the value in xmm registers, copy it
2241 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
2242 if ((RVLocs[i].getLocReg() == X86::ST0 ||
2243 RVLocs[i].getLocReg() == X86::ST1)) {
2244 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
2246 CopyReg = createResultReg(&X86::RFP80RegClass);
2248 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL),
2251 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2252 CopyReg).addReg(RVLocs[i].getLocReg());
2253 UsedRegs.push_back(RVLocs[i].getLocReg());
2256 if (CopyVT != RVLocs[i].getValVT()) {
2257 // Round the F80 the right size, which also moves to the appropriate xmm
2258 // register. This is accomplished by storing the F80 value in memory and
2259 // then loading it back. Ewww...
2260 EVT ResVT = RVLocs[i].getValVT();
2261 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
2262 unsigned MemSize = ResVT.getSizeInBits()/8;
2263 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
2264 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2267 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
2268 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2269 TII.get(Opc), ResultReg + i), FI);
2274 UpdateValueMap(I, ResultReg, RVLocs.size());
2276 // Set all unused physreg defs as dead.
2277 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2284 X86FastISel::TargetSelectInstruction(const Instruction *I) {
2285 switch (I->getOpcode()) {
2287 case Instruction::Load:
2288 return X86SelectLoad(I);
2289 case Instruction::Store:
2290 return X86SelectStore(I);
2291 case Instruction::Ret:
2292 return X86SelectRet(I);
2293 case Instruction::ICmp:
2294 case Instruction::FCmp:
2295 return X86SelectCmp(I);
2296 case Instruction::ZExt:
2297 return X86SelectZExt(I);
2298 case Instruction::Br:
2299 return X86SelectBranch(I);
2300 case Instruction::Call:
2301 return X86SelectCall(I);
2302 case Instruction::LShr:
2303 case Instruction::AShr:
2304 case Instruction::Shl:
2305 return X86SelectShift(I);
2306 case Instruction::SDiv:
2307 case Instruction::UDiv:
2308 case Instruction::SRem:
2309 case Instruction::URem:
2310 return X86SelectDivRem(I);
2311 case Instruction::Select:
2312 return X86SelectSelect(I);
2313 case Instruction::Trunc:
2314 return X86SelectTrunc(I);
2315 case Instruction::FPExt:
2316 return X86SelectFPExt(I);
2317 case Instruction::FPTrunc:
2318 return X86SelectFPTrunc(I);
2319 case Instruction::IntToPtr: // Deliberate fall-through.
2320 case Instruction::PtrToInt: {
2321 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
2322 EVT DstVT = TLI.getValueType(I->getType());
2323 if (DstVT.bitsGT(SrcVT))
2324 return X86SelectZExt(I);
2325 if (DstVT.bitsLT(SrcVT))
2326 return X86SelectTrunc(I);
2327 unsigned Reg = getRegForValue(I->getOperand(0));
2328 if (Reg == 0) return false;
2329 UpdateValueMap(I, Reg);
2337 unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
2339 if (!isTypeLegal(C->getType(), VT))
2342 // Can't handle alternate code models yet.
2343 if (TM.getCodeModel() != CodeModel::Small)
2346 // Get opcode and regclass of the output for the given load instruction.
2348 const TargetRegisterClass *RC = NULL;
2349 switch (VT.SimpleTy) {
2353 RC = &X86::GR8RegClass;
2357 RC = &X86::GR16RegClass;
2361 RC = &X86::GR32RegClass;
2364 // Must be in x86-64 mode.
2366 RC = &X86::GR64RegClass;
2369 if (X86ScalarSSEf32) {
2370 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
2371 RC = &X86::FR32RegClass;
2373 Opc = X86::LD_Fp32m;
2374 RC = &X86::RFP32RegClass;
2378 if (X86ScalarSSEf64) {
2379 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
2380 RC = &X86::FR64RegClass;
2382 Opc = X86::LD_Fp64m;
2383 RC = &X86::RFP64RegClass;
2387 // No f80 support yet.
2391 // Materialize addresses with LEA instructions.
2392 if (isa<GlobalValue>(C)) {
2394 if (X86SelectAddress(C, AM)) {
2395 // If the expression is just a basereg, then we're done, otherwise we need
2397 if (AM.BaseType == X86AddressMode::RegBase &&
2398 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == 0)
2401 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
2402 unsigned ResultReg = createResultReg(RC);
2403 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2404 TII.get(Opc), ResultReg), AM);
2410 // MachineConstantPool wants an explicit alignment.
2411 unsigned Align = TD.getPrefTypeAlignment(C->getType());
2413 // Alignment of vector types. FIXME!
2414 Align = TD.getTypeAllocSize(C->getType());
2417 // x86-32 PIC requires a PIC base register for constant pools.
2418 unsigned PICBase = 0;
2419 unsigned char OpFlag = 0;
2420 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
2421 OpFlag = X86II::MO_PIC_BASE_OFFSET;
2422 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
2423 } else if (Subtarget->isPICStyleGOT()) {
2424 OpFlag = X86II::MO_GOTOFF;
2425 PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
2426 } else if (Subtarget->isPICStyleRIPRel() &&
2427 TM.getCodeModel() == CodeModel::Small) {
2431 // Create the load from the constant pool.
2432 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
2433 unsigned ResultReg = createResultReg(RC);
2434 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2435 TII.get(Opc), ResultReg),
2436 MCPOffset, PICBase, OpFlag);
2441 unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
2442 // Fail on dynamic allocas. At this point, getRegForValue has already
2443 // checked its CSE maps, so if we're here trying to handle a dynamic
2444 // alloca, we're not going to succeed. X86SelectAddress has a
2445 // check for dynamic allocas, because it's called directly from
2446 // various places, but TargetMaterializeAlloca also needs a check
2447 // in order to avoid recursion between getRegForValue,
2448 // X86SelectAddrss, and TargetMaterializeAlloca.
2449 if (!FuncInfo.StaticAllocaMap.count(C))
2453 if (!X86SelectAddress(C, AM))
2455 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
2456 const TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
2457 unsigned ResultReg = createResultReg(RC);
2458 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2459 TII.get(Opc), ResultReg), AM);
2463 unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
2465 if (!isTypeLegal(CF->getType(), VT))
2468 // Get opcode and regclass for the given zero.
2470 const TargetRegisterClass *RC = NULL;
2471 switch (VT.SimpleTy) {
2474 if (X86ScalarSSEf32) {
2475 Opc = X86::FsFLD0SS;
2476 RC = &X86::FR32RegClass;
2478 Opc = X86::LD_Fp032;
2479 RC = &X86::RFP32RegClass;
2483 if (X86ScalarSSEf64) {
2484 Opc = X86::FsFLD0SD;
2485 RC = &X86::FR64RegClass;
2487 Opc = X86::LD_Fp064;
2488 RC = &X86::RFP64RegClass;
2492 // No f80 support yet.
2496 unsigned ResultReg = createResultReg(RC);
2497 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg);
2502 bool X86FastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2503 const LoadInst *LI) {
2505 if (!X86SelectAddress(LI->getOperand(0), AM))
2508 const X86InstrInfo &XII = (const X86InstrInfo&)TII;
2510 unsigned Size = TD.getTypeAllocSize(LI->getType());
2511 unsigned Alignment = LI->getAlignment();
2513 SmallVector<MachineOperand, 8> AddrOps;
2514 AM.getFullAddress(AddrOps);
2516 MachineInstr *Result =
2517 XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment);
2518 if (Result == 0) return false;
2520 FuncInfo.MBB->insert(FuncInfo.InsertPt, Result);
2521 MI->eraseFromParent();
2527 FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo,
2528 const TargetLibraryInfo *libInfo) {
2529 return new X86FastISel(funcInfo, libInfo);