1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/Support/CallSite.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/GetElementPtrTypeIterator.h"
33 #include "llvm/Target/TargetOptions.h"
38 class X86FastISel : public FastISel {
39 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
40 /// make the right decision when generating code for different targets.
41 const X86Subtarget *Subtarget;
43 /// StackPtr - Register used as the stack pointer.
47 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
48 /// floating point ops.
49 /// When SSE is available, use it for f32 operations.
50 /// When SSE2 is available, use it for f64 operations.
55 explicit X86FastISel(MachineFunction &mf,
56 DenseMap<const Value *, unsigned> &vm,
57 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
58 DenseMap<const AllocaInst *, int> &am,
59 std::vector<std::pair<MachineInstr*, unsigned> > &pn
61 , SmallSet<const Instruction *, 8> &cil
64 : FastISel(mf, vm, bm, am, pn
69 Subtarget = &TM.getSubtarget<X86Subtarget>();
70 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
71 X86ScalarSSEf64 = Subtarget->hasSSE2();
72 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 virtual bool TargetSelectInstruction(const Instruction *I);
77 #include "X86GenFastISel.inc"
80 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
82 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
84 bool X86FastEmitStore(EVT VT, const Value *Val,
85 const X86AddressMode &AM);
86 bool X86FastEmitStore(EVT VT, unsigned Val,
87 const X86AddressMode &AM);
89 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
92 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
93 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
95 bool X86SelectLoad(const Instruction *I);
97 bool X86SelectStore(const Instruction *I);
99 bool X86SelectCmp(const Instruction *I);
101 bool X86SelectZExt(const Instruction *I);
103 bool X86SelectBranch(const Instruction *I);
105 bool X86SelectShift(const Instruction *I);
107 bool X86SelectSelect(const Instruction *I);
109 bool X86SelectTrunc(const Instruction *I);
111 bool X86SelectFPExt(const Instruction *I);
112 bool X86SelectFPTrunc(const Instruction *I);
114 bool X86SelectExtractValue(const Instruction *I);
116 bool X86VisitIntrinsicCall(const IntrinsicInst &I);
117 bool X86SelectCall(const Instruction *I);
119 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false);
121 const X86InstrInfo *getInstrInfo() const {
122 return getTargetMachine()->getInstrInfo();
124 const X86TargetMachine *getTargetMachine() const {
125 return static_cast<const X86TargetMachine *>(&TM);
128 unsigned TargetMaterializeConstant(const Constant *C);
130 unsigned TargetMaterializeAlloca(const AllocaInst *C);
132 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
133 /// computed in an SSE register, not on the X87 floating point stack.
134 bool isScalarFPTypeInSSEReg(EVT VT) const {
135 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
136 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
139 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false);
142 } // end anonymous namespace.
144 bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
145 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
146 if (VT == MVT::Other || !VT.isSimple())
147 // Unhandled type. Halt "fast" selection and bail.
150 // For now, require SSE/SSE2 for performing floating-point operations,
151 // since x87 requires additional work.
152 if (VT == MVT::f64 && !X86ScalarSSEf64)
154 if (VT == MVT::f32 && !X86ScalarSSEf32)
156 // Similarly, no f80 support yet.
159 // We only handle legal types. For example, on x86-32 the instruction
160 // selector contains all of the 64-bit instructions from x86-64,
161 // under the assumption that i64 won't be used if the target doesn't
163 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
166 #include "X86GenCallingConv.inc"
168 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
170 CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC,
172 if (Subtarget->is64Bit()) {
173 if (CC == CallingConv::GHC)
174 return CC_X86_64_GHC;
175 else if (Subtarget->isTargetWin64())
176 return CC_X86_Win64_C;
181 if (CC == CallingConv::X86_FastCall)
182 return CC_X86_32_FastCall;
183 else if (CC == CallingConv::Fast)
184 return CC_X86_32_FastCC;
185 else if (CC == CallingConv::GHC)
186 return CC_X86_32_GHC;
191 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
192 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
193 /// Return true and the result register by reference if it is possible.
194 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
195 unsigned &ResultReg) {
196 // Get opcode and regclass of the output for the given load instruction.
198 const TargetRegisterClass *RC = NULL;
199 switch (VT.getSimpleVT().SimpleTy) {
200 default: return false;
204 RC = X86::GR8RegisterClass;
208 RC = X86::GR16RegisterClass;
212 RC = X86::GR32RegisterClass;
215 // Must be in x86-64 mode.
217 RC = X86::GR64RegisterClass;
220 if (Subtarget->hasSSE1()) {
222 RC = X86::FR32RegisterClass;
225 RC = X86::RFP32RegisterClass;
229 if (Subtarget->hasSSE2()) {
231 RC = X86::FR64RegisterClass;
234 RC = X86::RFP64RegisterClass;
238 // No f80 support yet.
242 ResultReg = createResultReg(RC);
243 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
247 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
248 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
249 /// and a displacement offset, or a GlobalAddress,
250 /// i.e. V. Return true if it is possible.
252 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val,
253 const X86AddressMode &AM) {
254 // Get opcode and regclass of the output for the given store instruction.
256 switch (VT.getSimpleVT().SimpleTy) {
257 case MVT::f80: // No f80 support yet.
258 default: return false;
260 // Mask out all but lowest bit.
261 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
263 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
266 // FALLTHROUGH, handling i1 as i8.
267 case MVT::i8: Opc = X86::MOV8mr; break;
268 case MVT::i16: Opc = X86::MOV16mr; break;
269 case MVT::i32: Opc = X86::MOV32mr; break;
270 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
272 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
275 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
279 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
283 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
284 const X86AddressMode &AM) {
285 // Handle 'null' like i32/i64 0.
286 if (isa<ConstantPointerNull>(Val))
287 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
289 // If this is a store of a simple constant, fold the constant into the store.
290 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
293 switch (VT.getSimpleVT().SimpleTy) {
295 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
296 case MVT::i8: Opc = X86::MOV8mi; break;
297 case MVT::i16: Opc = X86::MOV16mi; break;
298 case MVT::i32: Opc = X86::MOV32mi; break;
300 // Must be a 32-bit sign extended value.
301 if ((int)CI->getSExtValue() == CI->getSExtValue())
302 Opc = X86::MOV64mi32;
307 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
308 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
314 unsigned ValReg = getRegForValue(Val);
318 return X86FastEmitStore(VT, ValReg, AM);
321 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
322 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
323 /// ISD::SIGN_EXTEND).
324 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
325 unsigned Src, EVT SrcVT,
326 unsigned &ResultReg) {
327 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
336 /// X86SelectAddress - Attempt to fill in an address from the given value.
338 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
339 const User *U = NULL;
340 unsigned Opcode = Instruction::UserOp1;
341 if (const Instruction *I = dyn_cast<Instruction>(V)) {
342 Opcode = I->getOpcode();
344 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
345 Opcode = C->getOpcode();
351 case Instruction::BitCast:
352 // Look past bitcasts.
353 return X86SelectAddress(U->getOperand(0), AM);
355 case Instruction::IntToPtr:
356 // Look past no-op inttoptrs.
357 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
358 return X86SelectAddress(U->getOperand(0), AM);
361 case Instruction::PtrToInt:
362 // Look past no-op ptrtoints.
363 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
364 return X86SelectAddress(U->getOperand(0), AM);
367 case Instruction::Alloca: {
368 // Do static allocas.
369 const AllocaInst *A = cast<AllocaInst>(V);
370 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
371 if (SI != StaticAllocaMap.end()) {
372 AM.BaseType = X86AddressMode::FrameIndexBase;
373 AM.Base.FrameIndex = SI->second;
379 case Instruction::Add: {
380 // Adds of constants are common and easy enough.
381 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
382 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
383 // They have to fit in the 32-bit signed displacement field though.
384 if (isInt<32>(Disp)) {
385 AM.Disp = (uint32_t)Disp;
386 return X86SelectAddress(U->getOperand(0), AM);
392 case Instruction::GetElementPtr: {
393 X86AddressMode SavedAM = AM;
395 // Pattern-match simple GEPs.
396 uint64_t Disp = (int32_t)AM.Disp;
397 unsigned IndexReg = AM.IndexReg;
398 unsigned Scale = AM.Scale;
399 gep_type_iterator GTI = gep_type_begin(U);
400 // Iterate through the indices, folding what we can. Constants can be
401 // folded, and one dynamic index can be handled, if the scale is supported.
402 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
403 i != e; ++i, ++GTI) {
404 const Value *Op = *i;
405 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
406 const StructLayout *SL = TD.getStructLayout(STy);
407 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
408 Disp += SL->getElementOffset(Idx);
410 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
411 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
412 // Constant-offset addressing.
413 Disp += CI->getSExtValue() * S;
414 } else if (IndexReg == 0 &&
415 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
416 (S == 1 || S == 2 || S == 4 || S == 8)) {
417 // Scaled-index addressing.
419 IndexReg = getRegForGEPIndex(Op);
424 goto unsupported_gep;
427 // Check for displacement overflow.
428 if (!isInt<32>(Disp))
430 // Ok, the GEP indices were covered by constant-offset and scaled-index
431 // addressing. Update the address state and move on to examining the base.
432 AM.IndexReg = IndexReg;
434 AM.Disp = (uint32_t)Disp;
435 if (X86SelectAddress(U->getOperand(0), AM))
438 // If we couldn't merge the sub value into this addr mode, revert back to
439 // our address and just match the value instead of completely failing.
443 // Ok, the GEP indices weren't all covered.
448 // Handle constant address.
449 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
450 // Can't handle alternate code models yet.
451 if (TM.getCodeModel() != CodeModel::Small)
454 // RIP-relative addresses can't have additional register operands.
455 if (Subtarget->isPICStyleRIPRel() &&
456 (AM.Base.Reg != 0 || AM.IndexReg != 0))
459 // Can't handle TLS yet.
460 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
461 if (GVar->isThreadLocal())
464 // Okay, we've committed to selecting this global. Set up the basic address.
467 // Allow the subtarget to classify the global.
468 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
470 // If this reference is relative to the pic base, set it now.
471 if (isGlobalRelativeToPICBase(GVFlags)) {
472 // FIXME: How do we know Base.Reg is free??
473 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
476 // Unless the ABI requires an extra load, return a direct reference to
478 if (!isGlobalStubReference(GVFlags)) {
479 if (Subtarget->isPICStyleRIPRel()) {
480 // Use rip-relative addressing if we can. Above we verified that the
481 // base and index registers are unused.
482 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
483 AM.Base.Reg = X86::RIP;
485 AM.GVOpFlags = GVFlags;
489 // Ok, we need to do a load from a stub. If we've already loaded from this
490 // stub, reuse the loaded pointer, otherwise emit the load now.
491 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
493 if (I != LocalValueMap.end() && I->second != 0) {
496 // Issue load from stub.
498 const TargetRegisterClass *RC = NULL;
499 X86AddressMode StubAM;
500 StubAM.Base.Reg = AM.Base.Reg;
502 StubAM.GVOpFlags = GVFlags;
504 if (TLI.getPointerTy() == MVT::i64) {
506 RC = X86::GR64RegisterClass;
508 if (Subtarget->isPICStyleRIPRel())
509 StubAM.Base.Reg = X86::RIP;
512 RC = X86::GR32RegisterClass;
515 LoadReg = createResultReg(RC);
516 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM);
518 // Prevent loading GV stub multiple times in same MBB.
519 LocalValueMap[V] = LoadReg;
522 // Now construct the final address. Note that the Disp, Scale,
523 // and Index values may already be set here.
524 AM.Base.Reg = LoadReg;
529 // If all else fails, try to materialize the value in a register.
530 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
531 if (AM.Base.Reg == 0) {
532 AM.Base.Reg = getRegForValue(V);
533 return AM.Base.Reg != 0;
535 if (AM.IndexReg == 0) {
536 assert(AM.Scale == 1 && "Scale with no index!");
537 AM.IndexReg = getRegForValue(V);
538 return AM.IndexReg != 0;
545 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
547 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
548 const User *U = NULL;
549 unsigned Opcode = Instruction::UserOp1;
550 if (const Instruction *I = dyn_cast<Instruction>(V)) {
551 Opcode = I->getOpcode();
553 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
554 Opcode = C->getOpcode();
560 case Instruction::BitCast:
561 // Look past bitcasts.
562 return X86SelectCallAddress(U->getOperand(0), AM);
564 case Instruction::IntToPtr:
565 // Look past no-op inttoptrs.
566 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
567 return X86SelectCallAddress(U->getOperand(0), AM);
570 case Instruction::PtrToInt:
571 // Look past no-op ptrtoints.
572 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
573 return X86SelectCallAddress(U->getOperand(0), AM);
577 // Handle constant address.
578 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
579 // Can't handle alternate code models yet.
580 if (TM.getCodeModel() != CodeModel::Small)
583 // RIP-relative addresses can't have additional register operands.
584 if (Subtarget->isPICStyleRIPRel() &&
585 (AM.Base.Reg != 0 || AM.IndexReg != 0))
588 // Can't handle TLS or DLLImport.
589 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
590 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage())
593 // Okay, we've committed to selecting this global. Set up the basic address.
596 // No ABI requires an extra load for anything other than DLLImport, which
597 // we rejected above. Return a direct reference to the global.
598 if (Subtarget->isPICStyleRIPRel()) {
599 // Use rip-relative addressing if we can. Above we verified that the
600 // base and index registers are unused.
601 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
602 AM.Base.Reg = X86::RIP;
603 } else if (Subtarget->isPICStyleStubPIC()) {
604 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
605 } else if (Subtarget->isPICStyleGOT()) {
606 AM.GVOpFlags = X86II::MO_GOTOFF;
612 // If all else fails, try to materialize the value in a register.
613 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
614 if (AM.Base.Reg == 0) {
615 AM.Base.Reg = getRegForValue(V);
616 return AM.Base.Reg != 0;
618 if (AM.IndexReg == 0) {
619 assert(AM.Scale == 1 && "Scale with no index!");
620 AM.IndexReg = getRegForValue(V);
621 return AM.IndexReg != 0;
629 /// X86SelectStore - Select and emit code to implement store instructions.
630 bool X86FastISel::X86SelectStore(const Instruction *I) {
632 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
636 if (!X86SelectAddress(I->getOperand(1), AM))
639 return X86FastEmitStore(VT, I->getOperand(0), AM);
642 /// X86SelectLoad - Select and emit code to implement load instructions.
644 bool X86FastISel::X86SelectLoad(const Instruction *I) {
646 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
650 if (!X86SelectAddress(I->getOperand(0), AM))
653 unsigned ResultReg = 0;
654 if (X86FastEmitLoad(VT, AM, ResultReg)) {
655 UpdateValueMap(I, ResultReg);
661 static unsigned X86ChooseCmpOpcode(EVT VT) {
662 switch (VT.getSimpleVT().SimpleTy) {
664 case MVT::i8: return X86::CMP8rr;
665 case MVT::i16: return X86::CMP16rr;
666 case MVT::i32: return X86::CMP32rr;
667 case MVT::i64: return X86::CMP64rr;
668 case MVT::f32: return X86::UCOMISSrr;
669 case MVT::f64: return X86::UCOMISDrr;
673 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
674 /// of the comparison, return an opcode that works for the compare (e.g.
675 /// CMP32ri) otherwise return 0.
676 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
677 switch (VT.getSimpleVT().SimpleTy) {
678 // Otherwise, we can't fold the immediate into this comparison.
680 case MVT::i8: return X86::CMP8ri;
681 case MVT::i16: return X86::CMP16ri;
682 case MVT::i32: return X86::CMP32ri;
684 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
686 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
687 return X86::CMP64ri32;
692 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
694 unsigned Op0Reg = getRegForValue(Op0);
695 if (Op0Reg == 0) return false;
697 // Handle 'null' like i32/i64 0.
698 if (isa<ConstantPointerNull>(Op1))
699 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
701 // We have two options: compare with register or immediate. If the RHS of
702 // the compare is an immediate that we can fold into this compare, use
703 // CMPri, otherwise use CMPrr.
704 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
705 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
706 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
707 .addImm(Op1C->getSExtValue());
712 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
713 if (CompareOpc == 0) return false;
715 unsigned Op1Reg = getRegForValue(Op1);
716 if (Op1Reg == 0) return false;
717 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
722 bool X86FastISel::X86SelectCmp(const Instruction *I) {
723 const CmpInst *CI = cast<CmpInst>(I);
726 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
729 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
731 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
732 switch (CI->getPredicate()) {
733 case CmpInst::FCMP_OEQ: {
734 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
737 unsigned EReg = createResultReg(&X86::GR8RegClass);
738 unsigned NPReg = createResultReg(&X86::GR8RegClass);
739 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
740 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
742 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
743 UpdateValueMap(I, ResultReg);
746 case CmpInst::FCMP_UNE: {
747 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
750 unsigned NEReg = createResultReg(&X86::GR8RegClass);
751 unsigned PReg = createResultReg(&X86::GR8RegClass);
752 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
753 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
754 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
755 UpdateValueMap(I, ResultReg);
758 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
759 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
760 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
761 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
762 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
763 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
764 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
765 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
766 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
767 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
768 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
769 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
771 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
772 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
773 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
774 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
775 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
776 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
777 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
778 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
779 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
780 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
785 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
789 // Emit a compare of Op0/Op1.
790 if (!X86FastEmitCompare(Op0, Op1, VT))
793 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
794 UpdateValueMap(I, ResultReg);
798 bool X86FastISel::X86SelectZExt(const Instruction *I) {
799 // Handle zero-extension from i1 to i8, which is common.
800 if (I->getType()->isIntegerTy(8) &&
801 I->getOperand(0)->getType()->isIntegerTy(1)) {
802 unsigned ResultReg = getRegForValue(I->getOperand(0));
803 if (ResultReg == 0) return false;
804 // Set the high bits to zero.
805 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
806 if (ResultReg == 0) return false;
807 UpdateValueMap(I, ResultReg);
815 bool X86FastISel::X86SelectBranch(const Instruction *I) {
816 // Unconditional branches are selected by tablegen-generated code.
817 // Handle a conditional branch.
818 const BranchInst *BI = cast<BranchInst>(I);
819 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
820 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
822 // Fold the common case of a conditional branch with a comparison.
823 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
824 if (CI->hasOneUse()) {
825 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
827 // Try to take advantage of fallthrough opportunities.
828 CmpInst::Predicate Predicate = CI->getPredicate();
829 if (MBB->isLayoutSuccessor(TrueMBB)) {
830 std::swap(TrueMBB, FalseMBB);
831 Predicate = CmpInst::getInversePredicate(Predicate);
834 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
835 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
838 case CmpInst::FCMP_OEQ:
839 std::swap(TrueMBB, FalseMBB);
840 Predicate = CmpInst::FCMP_UNE;
842 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
843 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
844 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
845 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
846 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
847 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
848 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
849 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
850 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
851 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
852 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
853 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
854 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
856 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
857 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
858 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
859 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
860 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
861 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
862 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
863 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
864 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
865 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
870 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
874 // Emit a compare of the LHS and RHS, setting the flags.
875 if (!X86FastEmitCompare(Op0, Op1, VT))
878 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
880 if (Predicate == CmpInst::FCMP_UNE) {
881 // X86 requires a second branch to handle UNE (and OEQ,
882 // which is mapped to UNE above).
883 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
886 FastEmitBranch(FalseMBB);
887 MBB->addSuccessor(TrueMBB);
890 } else if (ExtractValueInst *EI =
891 dyn_cast<ExtractValueInst>(BI->getCondition())) {
892 // Check to see if the branch instruction is from an "arithmetic with
893 // overflow" intrinsic. The main way these intrinsics are used is:
895 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
896 // %sum = extractvalue { i32, i1 } %t, 0
897 // %obit = extractvalue { i32, i1 } %t, 1
898 // br i1 %obit, label %overflow, label %normal
900 // The %sum and %obit are converted in an ADD and a SETO/SETB before
901 // reaching the branch. Therefore, we search backwards through the MBB
902 // looking for the SETO/SETB instruction. If an instruction modifies the
903 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
904 // convert the branch into a JO/JB instruction.
905 if (const IntrinsicInst *CI =
906 dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
907 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
908 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
909 const MachineInstr *SetMI = 0;
910 unsigned Reg = lookUpRegForValue(EI);
912 for (MachineBasicBlock::const_reverse_iterator
913 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
914 const MachineInstr &MI = *RI;
916 if (MI.modifiesRegister(Reg)) {
917 unsigned Src, Dst, SrcSR, DstSR;
919 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
928 const TargetInstrDesc &TID = MI.getDesc();
929 if (TID.hasUnmodeledSideEffects() ||
930 TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
935 unsigned OpCode = SetMI->getOpcode();
937 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
938 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
939 X86::JO_4 : X86::JB_4))
941 FastEmitBranch(FalseMBB);
942 MBB->addSuccessor(TrueMBB);
950 // Otherwise do a clumsy setcc and re-test it.
951 unsigned OpReg = getRegForValue(BI->getCondition());
952 if (OpReg == 0) return false;
954 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
955 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
956 FastEmitBranch(FalseMBB);
957 MBB->addSuccessor(TrueMBB);
961 bool X86FastISel::X86SelectShift(const Instruction *I) {
962 unsigned CReg = 0, OpReg = 0, OpImm = 0;
963 const TargetRegisterClass *RC = NULL;
964 if (I->getType()->isIntegerTy(8)) {
966 RC = &X86::GR8RegClass;
967 switch (I->getOpcode()) {
968 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
969 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
970 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
971 default: return false;
973 } else if (I->getType()->isIntegerTy(16)) {
975 RC = &X86::GR16RegClass;
976 switch (I->getOpcode()) {
977 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
978 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
979 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
980 default: return false;
982 } else if (I->getType()->isIntegerTy(32)) {
984 RC = &X86::GR32RegClass;
985 switch (I->getOpcode()) {
986 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
987 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
988 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
989 default: return false;
991 } else if (I->getType()->isIntegerTy(64)) {
993 RC = &X86::GR64RegClass;
994 switch (I->getOpcode()) {
995 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
996 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
997 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
998 default: return false;
1004 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1005 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1008 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1009 if (Op0Reg == 0) return false;
1011 // Fold immediate in shl(x,3).
1012 if (const ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
1013 unsigned ResultReg = createResultReg(RC);
1014 BuildMI(MBB, DL, TII.get(OpImm),
1015 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
1016 UpdateValueMap(I, ResultReg);
1020 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1021 if (Op1Reg == 0) return false;
1022 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
1024 // The shift instruction uses X86::CL. If we defined a super-register
1025 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
1026 // we're doing here.
1027 if (CReg != X86::CL)
1028 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL)
1029 .addReg(CReg).addImm(X86::SUBREG_8BIT);
1031 unsigned ResultReg = createResultReg(RC);
1032 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
1033 UpdateValueMap(I, ResultReg);
1037 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1038 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1039 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1043 const TargetRegisterClass *RC = NULL;
1044 if (VT.getSimpleVT() == MVT::i16) {
1045 Opc = X86::CMOVE16rr;
1046 RC = &X86::GR16RegClass;
1047 } else if (VT.getSimpleVT() == MVT::i32) {
1048 Opc = X86::CMOVE32rr;
1049 RC = &X86::GR32RegClass;
1050 } else if (VT.getSimpleVT() == MVT::i64) {
1051 Opc = X86::CMOVE64rr;
1052 RC = &X86::GR64RegClass;
1057 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1058 if (Op0Reg == 0) return false;
1059 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1060 if (Op1Reg == 0) return false;
1061 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1062 if (Op2Reg == 0) return false;
1064 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
1065 unsigned ResultReg = createResultReg(RC);
1066 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
1067 UpdateValueMap(I, ResultReg);
1071 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
1072 // fpext from float to double.
1073 if (Subtarget->hasSSE2() &&
1074 I->getType()->isDoubleTy()) {
1075 const Value *V = I->getOperand(0);
1076 if (V->getType()->isFloatTy()) {
1077 unsigned OpReg = getRegForValue(V);
1078 if (OpReg == 0) return false;
1079 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1080 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
1081 UpdateValueMap(I, ResultReg);
1089 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
1090 if (Subtarget->hasSSE2()) {
1091 if (I->getType()->isFloatTy()) {
1092 const Value *V = I->getOperand(0);
1093 if (V->getType()->isDoubleTy()) {
1094 unsigned OpReg = getRegForValue(V);
1095 if (OpReg == 0) return false;
1096 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1097 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
1098 UpdateValueMap(I, ResultReg);
1107 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
1108 if (Subtarget->is64Bit())
1109 // All other cases should be handled by the tblgen generated code.
1111 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1112 EVT DstVT = TLI.getValueType(I->getType());
1114 // This code only handles truncation to byte right now.
1115 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1116 // All other cases should be handled by the tblgen generated code.
1118 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
1119 // All other cases should be handled by the tblgen generated code.
1122 unsigned InputReg = getRegForValue(I->getOperand(0));
1124 // Unhandled operand. Halt "fast" selection and bail.
1127 // First issue a copy to GR16_ABCD or GR32_ABCD.
1128 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
1129 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1130 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1131 unsigned CopyReg = createResultReg(CopyRC);
1132 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1134 // Then issue an extract_subreg.
1135 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1136 CopyReg, X86::SUBREG_8BIT);
1140 UpdateValueMap(I, ResultReg);
1144 bool X86FastISel::X86SelectExtractValue(const Instruction *I) {
1145 const ExtractValueInst *EI = cast<ExtractValueInst>(I);
1146 const Value *Agg = EI->getAggregateOperand();
1148 if (const IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1149 switch (CI->getIntrinsicID()) {
1151 case Intrinsic::sadd_with_overflow:
1152 case Intrinsic::uadd_with_overflow:
1153 // Cheat a little. We know that the registers for "add" and "seto" are
1154 // allocated sequentially. However, we only keep track of the register
1155 // for "add" in the value map. Use extractvalue's index to get the
1156 // correct register for "seto".
1157 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1165 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
1166 // FIXME: Handle more intrinsics.
1167 switch (I.getIntrinsicID()) {
1168 default: return false;
1169 case Intrinsic::stackprotector: {
1170 // Emit code inline code to store the stack guard onto the stack.
1171 EVT PtrTy = TLI.getPointerTy();
1173 const Value *Op1 = I.getOperand(1); // The guard's value.
1174 const AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
1176 // Grab the frame index.
1178 if (!X86SelectAddress(Slot, AM)) return false;
1180 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
1184 case Intrinsic::objectsize: {
1185 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
1186 const Type *Ty = I.getCalledFunction()->getReturnType();
1188 assert(CI && "Non-constant type in Intrinsic::objectsize?");
1191 if (!isTypeLegal(Ty, VT))
1197 else if (VT == MVT::i64)
1202 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1203 BuildMI(MBB, DL, TII.get(OpC), ResultReg).
1204 addImm(CI->getZExtValue() == 0 ? -1ULL : 0);
1205 UpdateValueMap(&I, ResultReg);
1208 case Intrinsic::dbg_declare: {
1209 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I);
1211 assert(DI->getAddress() && "Null address should be checked earlier!");
1212 if (!X86SelectAddress(DI->getAddress(), AM))
1214 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1215 // FIXME may need to add RegState::Debug to any registers produced,
1216 // although ESP/EBP should be the only ones at the moment.
1217 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0).
1218 addMetadata(DI->getVariable());
1221 case Intrinsic::trap: {
1222 BuildMI(MBB, DL, TII.get(X86::TRAP));
1225 case Intrinsic::sadd_with_overflow:
1226 case Intrinsic::uadd_with_overflow: {
1227 // Replace "add with overflow" intrinsics with an "add" instruction followed
1228 // by a seto/setc instruction. Later on, when the "extractvalue"
1229 // instructions are encountered, we use the fact that two registers were
1230 // created sequentially to get the correct registers for the "sum" and the
1232 const Function *Callee = I.getCalledFunction();
1234 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1237 if (!isTypeLegal(RetTy, VT))
1240 const Value *Op1 = I.getOperand(1);
1241 const Value *Op2 = I.getOperand(2);
1242 unsigned Reg1 = getRegForValue(Op1);
1243 unsigned Reg2 = getRegForValue(Op2);
1245 if (Reg1 == 0 || Reg2 == 0)
1246 // FIXME: Handle values *not* in registers.
1252 else if (VT == MVT::i64)
1257 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1258 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1259 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1261 // If the add with overflow is an intra-block value then we just want to
1262 // create temporaries for it like normal. If it is a cross-block value then
1263 // UpdateValueMap will return the cross-block register used. Since we
1264 // *really* want the value to be live in the register pair known by
1265 // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1266 // the cross block case. In the non-cross-block case, we should just make
1267 // another register for the value.
1268 if (DestReg1 != ResultReg)
1269 ResultReg = DestReg1+1;
1271 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1273 unsigned Opc = X86::SETBr;
1274 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1276 BuildMI(MBB, DL, TII.get(Opc), ResultReg);
1282 bool X86FastISel::X86SelectCall(const Instruction *I) {
1283 const CallInst *CI = cast<CallInst>(I);
1284 const Value *Callee = I->getOperand(0);
1286 // Can't handle inline asm yet.
1287 if (isa<InlineAsm>(Callee))
1290 // Handle intrinsic calls.
1291 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1292 return X86VisitIntrinsicCall(*II);
1294 // Handle only C and fastcc calling conventions for now.
1295 ImmutableCallSite CS(CI);
1296 CallingConv::ID CC = CS.getCallingConv();
1297 if (CC != CallingConv::C &&
1298 CC != CallingConv::Fast &&
1299 CC != CallingConv::X86_FastCall)
1302 // fastcc with -tailcallopt is intended to provide a guaranteed
1303 // tail call optimization. Fastisel doesn't know how to do that.
1304 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
1307 // Let SDISel handle vararg functions.
1308 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1309 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1310 if (FTy->isVarArg())
1313 // Handle *simple* calls for now.
1314 const Type *RetTy = CS.getType();
1316 if (RetTy->isVoidTy())
1317 RetVT = MVT::isVoid;
1318 else if (!isTypeLegal(RetTy, RetVT, true))
1321 // Materialize callee address in a register. FIXME: GV address can be
1322 // handled with a CALLpcrel32 instead.
1323 X86AddressMode CalleeAM;
1324 if (!X86SelectCallAddress(Callee, CalleeAM))
1326 unsigned CalleeOp = 0;
1327 const GlobalValue *GV = 0;
1328 if (CalleeAM.GV != 0) {
1330 } else if (CalleeAM.Base.Reg != 0) {
1331 CalleeOp = CalleeAM.Base.Reg;
1335 // Allow calls which produce i1 results.
1336 bool AndToI1 = false;
1337 if (RetVT == MVT::i1) {
1342 // Deal with call operands first.
1343 SmallVector<const Value *, 8> ArgVals;
1344 SmallVector<unsigned, 8> Args;
1345 SmallVector<EVT, 8> ArgVTs;
1346 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1347 Args.reserve(CS.arg_size());
1348 ArgVals.reserve(CS.arg_size());
1349 ArgVTs.reserve(CS.arg_size());
1350 ArgFlags.reserve(CS.arg_size());
1351 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1353 unsigned Arg = getRegForValue(*i);
1356 ISD::ArgFlagsTy Flags;
1357 unsigned AttrInd = i - CS.arg_begin() + 1;
1358 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1360 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1363 // FIXME: Only handle *easy* calls for now.
1364 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1365 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1366 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1367 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1370 const Type *ArgTy = (*i)->getType();
1372 if (!isTypeLegal(ArgTy, ArgVT))
1374 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1375 Flags.setOrigAlign(OriginalAlignment);
1377 Args.push_back(Arg);
1378 ArgVals.push_back(*i);
1379 ArgVTs.push_back(ArgVT);
1380 ArgFlags.push_back(Flags);
1383 // Analyze operands of the call, assigning locations to each operand.
1384 SmallVector<CCValAssign, 16> ArgLocs;
1385 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext());
1386 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1388 // Get a count of how many bytes are to be pushed on the stack.
1389 unsigned NumBytes = CCInfo.getNextStackOffset();
1391 // Issue CALLSEQ_START
1392 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1393 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1395 // Process argument: walk the register/memloc assignments, inserting
1397 SmallVector<unsigned, 4> RegArgs;
1398 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1399 CCValAssign &VA = ArgLocs[i];
1400 unsigned Arg = Args[VA.getValNo()];
1401 EVT ArgVT = ArgVTs[VA.getValNo()];
1403 // Promote the value if needed.
1404 switch (VA.getLocInfo()) {
1405 default: llvm_unreachable("Unknown loc info!");
1406 case CCValAssign::Full: break;
1407 case CCValAssign::SExt: {
1408 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1410 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1412 ArgVT = VA.getLocVT();
1415 case CCValAssign::ZExt: {
1416 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1418 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1420 ArgVT = VA.getLocVT();
1423 case CCValAssign::AExt: {
1424 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1427 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1430 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1433 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1434 ArgVT = VA.getLocVT();
1437 case CCValAssign::BCvt: {
1438 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(),
1439 ISD::BIT_CONVERT, Arg);
1440 assert(BC != 0 && "Failed to emit a bitcast!");
1442 ArgVT = VA.getLocVT();
1447 if (VA.isRegLoc()) {
1448 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1449 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1451 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1453 RegArgs.push_back(VA.getLocReg());
1455 unsigned LocMemOffset = VA.getLocMemOffset();
1457 AM.Base.Reg = StackPtr;
1458 AM.Disp = LocMemOffset;
1459 const Value *ArgVal = ArgVals[VA.getValNo()];
1461 // If this is a really simple value, emit this with the Value* version of
1462 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1463 // can cause us to reevaluate the argument.
1464 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1465 X86FastEmitStore(ArgVT, ArgVal, AM);
1467 X86FastEmitStore(ArgVT, Arg, AM);
1471 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1473 if (Subtarget->isPICStyleGOT()) {
1474 TargetRegisterClass *RC = X86::GR32RegisterClass;
1475 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1476 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1477 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1482 MachineInstrBuilder MIB;
1484 // Register-indirect call.
1485 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r;
1486 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp);
1490 assert(GV && "Not a direct call");
1492 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
1494 // See if we need any target-specific flags on the GV operand.
1495 unsigned char OpFlags = 0;
1497 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1498 // external symbols most go through the PLT in PIC mode. If the symbol
1499 // has hidden or protected visibility, or if it is static or local, then
1500 // we don't need to use the PLT - we can directly call it.
1501 if (Subtarget->isTargetELF() &&
1502 TM.getRelocationModel() == Reloc::PIC_ &&
1503 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1504 OpFlags = X86II::MO_PLT;
1505 } else if (Subtarget->isPICStyleStubAny() &&
1506 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1507 Subtarget->getDarwinVers() < 9) {
1508 // PC-relative references to external symbols should go through $stub,
1509 // unless we're building with the leopard linker or later, which
1510 // automatically synthesizes these stubs.
1511 OpFlags = X86II::MO_DARWIN_STUB;
1515 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags);
1518 // Add an implicit use GOT pointer in EBX.
1519 if (Subtarget->isPICStyleGOT())
1520 MIB.addReg(X86::EBX);
1522 // Add implicit physical register uses to the call.
1523 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1524 MIB.addReg(RegArgs[i]);
1526 // Issue CALLSEQ_END
1527 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1528 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1530 // Now handle call return value (if any).
1531 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1532 SmallVector<CCValAssign, 16> RVLocs;
1533 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
1534 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1536 // Copy all of the result registers out of their specified physreg.
1537 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1538 EVT CopyVT = RVLocs[0].getValVT();
1539 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1540 TargetRegisterClass *SrcRC = DstRC;
1542 // If this is a call to a function that returns an fp value on the x87 fp
1543 // stack, but where we prefer to use the value in xmm registers, copy it
1544 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1545 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1546 RVLocs[0].getLocReg() == X86::ST1) &&
1547 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1549 SrcRC = X86::RSTRegisterClass;
1550 DstRC = X86::RFP80RegisterClass;
1553 unsigned ResultReg = createResultReg(DstRC);
1554 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1555 RVLocs[0].getLocReg(), DstRC, SrcRC);
1556 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1558 if (CopyVT != RVLocs[0].getValVT()) {
1559 // Round the F80 the right size, which also moves to the appropriate xmm
1560 // register. This is accomplished by storing the F80 value in memory and
1561 // then loading it back. Ewww...
1562 EVT ResVT = RVLocs[0].getValVT();
1563 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1564 unsigned MemSize = ResVT.getSizeInBits()/8;
1565 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
1566 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1567 DstRC = ResVT == MVT::f32
1568 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1569 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1570 ResultReg = createResultReg(DstRC);
1571 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1575 // Mask out all but lowest bit for some call which produces an i1.
1576 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1578 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1579 ResultReg = AndResult;
1582 UpdateValueMap(I, ResultReg);
1590 X86FastISel::TargetSelectInstruction(const Instruction *I) {
1591 switch (I->getOpcode()) {
1593 case Instruction::Load:
1594 return X86SelectLoad(I);
1595 case Instruction::Store:
1596 return X86SelectStore(I);
1597 case Instruction::ICmp:
1598 case Instruction::FCmp:
1599 return X86SelectCmp(I);
1600 case Instruction::ZExt:
1601 return X86SelectZExt(I);
1602 case Instruction::Br:
1603 return X86SelectBranch(I);
1604 case Instruction::Call:
1605 return X86SelectCall(I);
1606 case Instruction::LShr:
1607 case Instruction::AShr:
1608 case Instruction::Shl:
1609 return X86SelectShift(I);
1610 case Instruction::Select:
1611 return X86SelectSelect(I);
1612 case Instruction::Trunc:
1613 return X86SelectTrunc(I);
1614 case Instruction::FPExt:
1615 return X86SelectFPExt(I);
1616 case Instruction::FPTrunc:
1617 return X86SelectFPTrunc(I);
1618 case Instruction::ExtractValue:
1619 return X86SelectExtractValue(I);
1620 case Instruction::IntToPtr: // Deliberate fall-through.
1621 case Instruction::PtrToInt: {
1622 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1623 EVT DstVT = TLI.getValueType(I->getType());
1624 if (DstVT.bitsGT(SrcVT))
1625 return X86SelectZExt(I);
1626 if (DstVT.bitsLT(SrcVT))
1627 return X86SelectTrunc(I);
1628 unsigned Reg = getRegForValue(I->getOperand(0));
1629 if (Reg == 0) return false;
1630 UpdateValueMap(I, Reg);
1638 unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
1640 if (!isTypeLegal(C->getType(), VT))
1643 // Get opcode and regclass of the output for the given load instruction.
1645 const TargetRegisterClass *RC = NULL;
1646 switch (VT.getSimpleVT().SimpleTy) {
1647 default: return false;
1650 RC = X86::GR8RegisterClass;
1654 RC = X86::GR16RegisterClass;
1658 RC = X86::GR32RegisterClass;
1661 // Must be in x86-64 mode.
1663 RC = X86::GR64RegisterClass;
1666 if (Subtarget->hasSSE1()) {
1668 RC = X86::FR32RegisterClass;
1670 Opc = X86::LD_Fp32m;
1671 RC = X86::RFP32RegisterClass;
1675 if (Subtarget->hasSSE2()) {
1677 RC = X86::FR64RegisterClass;
1679 Opc = X86::LD_Fp64m;
1680 RC = X86::RFP64RegisterClass;
1684 // No f80 support yet.
1688 // Materialize addresses with LEA instructions.
1689 if (isa<GlobalValue>(C)) {
1691 if (X86SelectAddress(C, AM)) {
1692 if (TLI.getPointerTy() == MVT::i32)
1696 unsigned ResultReg = createResultReg(RC);
1697 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1703 // MachineConstantPool wants an explicit alignment.
1704 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1706 // Alignment of vector types. FIXME!
1707 Align = TD.getTypeAllocSize(C->getType());
1710 // x86-32 PIC requires a PIC base register for constant pools.
1711 unsigned PICBase = 0;
1712 unsigned char OpFlag = 0;
1713 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
1714 OpFlag = X86II::MO_PIC_BASE_OFFSET;
1715 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1716 } else if (Subtarget->isPICStyleGOT()) {
1717 OpFlag = X86II::MO_GOTOFF;
1718 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1719 } else if (Subtarget->isPICStyleRIPRel() &&
1720 TM.getCodeModel() == CodeModel::Small) {
1724 // Create the load from the constant pool.
1725 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1726 unsigned ResultReg = createResultReg(RC);
1727 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg),
1728 MCPOffset, PICBase, OpFlag);
1733 unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
1734 // Fail on dynamic allocas. At this point, getRegForValue has already
1735 // checked its CSE maps, so if we're here trying to handle a dynamic
1736 // alloca, we're not going to succeed. X86SelectAddress has a
1737 // check for dynamic allocas, because it's called directly from
1738 // various places, but TargetMaterializeAlloca also needs a check
1739 // in order to avoid recursion between getRegForValue,
1740 // X86SelectAddrss, and TargetMaterializeAlloca.
1741 if (!StaticAllocaMap.count(C))
1745 if (!X86SelectAddress(C, AM))
1747 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1748 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1749 unsigned ResultReg = createResultReg(RC);
1750 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1755 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1756 DenseMap<const Value *, unsigned> &vm,
1757 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1758 DenseMap<const AllocaInst *, int> &am,
1759 std::vector<std::pair<MachineInstr*, unsigned> > &pn
1761 , SmallSet<const Instruction *, 8> &cil
1764 return new X86FastISel(mf, vm, bm, am, pn