1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 class X86FastISel : public FastISel {
28 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
29 /// make the right decision when generating code for different targets.
30 const X86Subtarget *Subtarget;
33 explicit X86FastISel(MachineFunction &mf,
34 DenseMap<const Value *, unsigned> &vm,
35 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm)
36 : FastISel(mf, vm, bm) {
37 Subtarget = &TM.getSubtarget<X86Subtarget>();
40 virtual bool TargetSelectInstruction(Instruction *I);
42 #include "X86GenFastISel.inc"
45 bool X86SelectConstAddr(Value *V, unsigned &Op0);
47 bool X86SelectLoad(Instruction *I);
50 /// X86SelectConstAddr - Select and emit code to materialize constant address.
52 bool X86FastISel::X86SelectConstAddr(Value *V,
54 // FIXME: Only GlobalAddress for now.
55 GlobalValue *GV = dyn_cast<GlobalValue>(V);
59 if (Subtarget->GVRequiresExtraLoad(GV, TM, false)) {
60 // Issue load from stub if necessary.
62 const TargetRegisterClass *RC = NULL;
63 if (TLI.getPointerTy() == MVT::i32) {
65 RC = X86::GR32RegisterClass;
68 RC = X86::GR64RegisterClass;
70 Op0 = createResultReg(RC);
73 addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
74 // Prevent loading GV stub multiple times in same MBB.
75 LocalValueMap[V] = Op0;
80 /// X86SelectLoad - Select and emit code to implement load instructions.
82 bool X86FastISel::X86SelectLoad(Instruction *I) {
83 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
84 if (VT == MVT::Other || !VT.isSimple())
85 // Unhandled type. Halt "fast" selection and bail.
89 VT = TLI.getPointerTy();
90 // We only handle legal types. For example, on x86-32 the instruction
91 // selector contains all of the 64-bit instructions from x86-64,
92 // under the assumption that i64 won't be used if the target doesn't
94 if (!TLI.isTypeLegal(VT))
97 Value *V = I->getOperand(0);
98 unsigned Op0 = getRegForValue(V);
100 // Handle constant load address.
101 if (!isa<Constant>(V) || !X86SelectConstAddr(V, Op0))
102 // Unhandled operand. Halt "fast" selection and bail.
106 // Get opcode and regclass of the output for the given load instruction.
108 const TargetRegisterClass *RC = NULL;
109 switch (VT.getSimpleVT()) {
110 default: return false;
113 RC = X86::GR8RegisterClass;
117 RC = X86::GR16RegisterClass;
121 RC = X86::GR32RegisterClass;
124 // Must be in x86-64 mode.
126 RC = X86::GR64RegisterClass;
129 if (Subtarget->hasSSE1()) {
131 RC = X86::FR32RegisterClass;
134 RC = X86::RFP32RegisterClass;
138 if (Subtarget->hasSSE2()) {
140 RC = X86::FR64RegisterClass;
143 RC = X86::RFP64RegisterClass;
148 RC = X86::RFP80RegisterClass;
152 unsigned ResultReg = createResultReg(RC);
155 // Address is in register.
158 AM.GV = cast<GlobalValue>(V);
159 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
160 UpdateValueMap(I, ResultReg);
166 X86FastISel::TargetSelectInstruction(Instruction *I) {
167 switch (I->getOpcode()) {
169 case Instruction::Load:
170 return X86SelectLoad(I);
177 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
178 DenseMap<const Value *, unsigned> &vm,
179 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm) {
180 return new X86FastISel(mf, vm, bm);