1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 class X86FastISel : public FastISel {
31 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
32 /// make the right decision when generating code for different targets.
33 const X86Subtarget *Subtarget;
36 explicit X86FastISel(MachineFunction &mf,
37 DenseMap<const Value *, unsigned> &vm,
38 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm)
39 : FastISel(mf, vm, bm) {
40 Subtarget = &TM.getSubtarget<X86Subtarget>();
43 virtual bool TargetSelectInstruction(Instruction *I);
45 #include "X86GenFastISel.inc"
48 bool X86FastEmitLoad(MVT VT, unsigned Op0, Value *V, unsigned &RR);
50 bool X86FastEmitStore(MVT VT, unsigned Op0, unsigned Op1, Value *V);
52 bool X86SelectConstAddr(Value *V, unsigned &Op0);
54 bool X86SelectLoad(Instruction *I);
56 bool X86SelectStore(Instruction *I);
58 bool X86SelectCmp(Instruction *I);
60 bool X86SelectZExt(Instruction *I);
62 bool X86SelectBranch(Instruction *I);
64 bool X86SelectShift(Instruction *I);
66 bool X86SelectSelect(Instruction *I);
68 unsigned TargetMaterializeConstant(Constant *C, MachineConstantPool* MCP);
71 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
72 /// The address is either pre-computed, i.e. Op0, or a GlobalAddress, i.e. V.
73 /// Return true and the result register by reference if it is possible.
74 bool X86FastISel::X86FastEmitLoad(MVT VT, unsigned Op0, Value *V,
75 unsigned &ResultReg) {
76 // Get opcode and regclass of the output for the given load instruction.
78 const TargetRegisterClass *RC = NULL;
79 switch (VT.getSimpleVT()) {
80 default: return false;
83 RC = X86::GR8RegisterClass;
87 RC = X86::GR16RegisterClass;
91 RC = X86::GR32RegisterClass;
94 // Must be in x86-64 mode.
96 RC = X86::GR64RegisterClass;
99 if (Subtarget->hasSSE1()) {
101 RC = X86::FR32RegisterClass;
104 RC = X86::RFP32RegisterClass;
108 if (Subtarget->hasSSE2()) {
110 RC = X86::FR64RegisterClass;
113 RC = X86::RFP64RegisterClass;
118 RC = X86::RFP80RegisterClass;
122 ResultReg = createResultReg(RC);
125 // Address is in register.
128 AM.GV = cast<GlobalValue>(V);
129 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
133 /// X86FastEmitStore - Emit a machine instruction to store a value Op0 of
134 /// type VT. The address is either pre-computed, i.e. Op1, or a GlobalAddress,
135 /// i.e. V. Return true if it is possible.
137 X86FastISel::X86FastEmitStore(MVT VT, unsigned Op0, unsigned Op1, Value *V) {
138 // Get opcode and regclass of the output for the given load instruction.
140 const TargetRegisterClass *RC = NULL;
141 switch (VT.getSimpleVT()) {
142 default: return false;
145 RC = X86::GR8RegisterClass;
149 RC = X86::GR16RegisterClass;
153 RC = X86::GR32RegisterClass;
156 // Must be in x86-64 mode.
158 RC = X86::GR64RegisterClass;
161 if (Subtarget->hasSSE1()) {
163 RC = X86::FR32RegisterClass;
166 RC = X86::RFP32RegisterClass;
170 if (Subtarget->hasSSE2()) {
172 RC = X86::FR64RegisterClass;
175 RC = X86::RFP64RegisterClass;
180 RC = X86::RFP80RegisterClass;
186 // Address is in register.
189 AM.GV = cast<GlobalValue>(V);
190 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Op0);
194 /// X86SelectConstAddr - Select and emit code to materialize constant address.
196 bool X86FastISel::X86SelectConstAddr(Value *V,
198 // FIXME: Only GlobalAddress for now.
199 GlobalValue *GV = dyn_cast<GlobalValue>(V);
203 if (Subtarget->GVRequiresExtraLoad(GV, TM, false)) {
204 // Issue load from stub if necessary.
206 const TargetRegisterClass *RC = NULL;
207 if (TLI.getPointerTy() == MVT::i32) {
209 RC = X86::GR32RegisterClass;
212 RC = X86::GR64RegisterClass;
214 Op0 = createResultReg(RC);
217 addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
218 // Prevent loading GV stub multiple times in same MBB.
219 LocalValueMap[V] = Op0;
224 /// X86SelectStore - Select and emit code to implement store instructions.
225 bool X86FastISel::X86SelectStore(Instruction* I) {
226 MVT VT = MVT::getMVT(I->getOperand(0)->getType());
227 if (VT == MVT::Other || !VT.isSimple())
228 // Unhandled type. Halt "fast" selection and bail.
232 VT = TLI.getPointerTy();
233 // We only handle legal types. For example, on x86-32 the instruction
234 // selector contains all of the 64-bit instructions from x86-64,
235 // under the assumption that i64 won't be used if the target doesn't
237 if (!TLI.isTypeLegal(VT))
239 unsigned Op0 = getRegForValue(I->getOperand(0));
241 // Unhandled operand. Halt "fast" selection and bail.
244 Value *V = I->getOperand(1);
245 unsigned Op1 = getRegForValue(V);
247 // Handle constant load address.
248 if (!isa<Constant>(V) || !X86SelectConstAddr(V, Op1))
249 // Unhandled operand. Halt "fast" selection and bail.
253 return X86FastEmitStore(VT, Op0, Op1, V);
256 /// X86SelectLoad - Select and emit code to implement load instructions.
258 bool X86FastISel::X86SelectLoad(Instruction *I) {
259 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
260 if (VT == MVT::Other || !VT.isSimple())
261 // Unhandled type. Halt "fast" selection and bail.
265 VT = TLI.getPointerTy();
266 // We only handle legal types. For example, on x86-32 the instruction
267 // selector contains all of the 64-bit instructions from x86-64,
268 // under the assumption that i64 won't be used if the target doesn't
270 if (!TLI.isTypeLegal(VT))
273 Value *V = I->getOperand(0);
274 unsigned Op0 = getRegForValue(V);
276 // Handle constant load address.
277 // FIXME: If load type is something we can't handle, this can result in
278 // a dead stub load instruction.
279 if (!isa<Constant>(V) || !X86SelectConstAddr(V, Op0))
280 // Unhandled operand. Halt "fast" selection and bail.
284 unsigned ResultReg = 0;
285 if (X86FastEmitLoad(VT, Op0, V, ResultReg)) {
286 UpdateValueMap(I, ResultReg);
292 bool X86FastISel::X86SelectCmp(Instruction *I) {
293 CmpInst *CI = cast<CmpInst>(I);
295 MVT VT = TLI.getValueType(I->getOperand(0)->getType());
296 if (!TLI.isTypeLegal(VT))
299 unsigned Op0Reg = getRegForValue(CI->getOperand(0));
300 if (Op0Reg == 0) return false;
301 unsigned Op1Reg = getRegForValue(CI->getOperand(1));
302 if (Op1Reg == 0) return false;
305 switch (VT.getSimpleVT()) {
306 case MVT::i8: Opc = X86::CMP8rr; break;
307 case MVT::i16: Opc = X86::CMP16rr; break;
308 case MVT::i32: Opc = X86::CMP32rr; break;
309 case MVT::i64: Opc = X86::CMP64rr; break;
310 case MVT::f32: Opc = X86::UCOMISSrr; break;
311 case MVT::f64: Opc = X86::UCOMISDrr; break;
312 default: return false;
315 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
316 switch (CI->getPredicate()) {
317 case CmpInst::FCMP_OEQ: {
318 unsigned EReg = createResultReg(&X86::GR8RegClass);
319 unsigned NPReg = createResultReg(&X86::GR8RegClass);
320 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
321 BuildMI(MBB, TII.get(X86::SETEr), EReg);
322 BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
323 BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
326 case CmpInst::FCMP_UNE: {
327 unsigned NEReg = createResultReg(&X86::GR8RegClass);
328 unsigned PReg = createResultReg(&X86::GR8RegClass);
329 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
330 BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
331 BuildMI(MBB, TII.get(X86::SETPr), PReg);
332 BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
335 case CmpInst::FCMP_OGT:
336 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
337 BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
339 case CmpInst::FCMP_OGE:
340 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
341 BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
343 case CmpInst::FCMP_OLT:
344 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
345 BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
347 case CmpInst::FCMP_OLE:
348 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
349 BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
351 case CmpInst::FCMP_ONE:
352 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
353 BuildMI(MBB, TII.get(X86::SETNEr), ResultReg);
355 case CmpInst::FCMP_ORD:
356 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
357 BuildMI(MBB, TII.get(X86::SETNPr), ResultReg);
359 case CmpInst::FCMP_UNO:
360 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
361 BuildMI(MBB, TII.get(X86::SETPr), ResultReg);
363 case CmpInst::FCMP_UEQ:
364 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
365 BuildMI(MBB, TII.get(X86::SETEr), ResultReg);
367 case CmpInst::FCMP_UGT:
368 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
369 BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
371 case CmpInst::FCMP_UGE:
372 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
373 BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
375 case CmpInst::FCMP_ULT:
376 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
377 BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
379 case CmpInst::FCMP_ULE:
380 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
381 BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
383 case CmpInst::ICMP_EQ:
384 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
385 BuildMI(MBB, TII.get(X86::SETEr), ResultReg);
387 case CmpInst::ICMP_NE:
388 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
389 BuildMI(MBB, TII.get(X86::SETNEr), ResultReg);
391 case CmpInst::ICMP_UGT:
392 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
393 BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
395 case CmpInst::ICMP_UGE:
396 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
397 BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
399 case CmpInst::ICMP_ULT:
400 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
401 BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
403 case CmpInst::ICMP_ULE:
404 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
405 BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
407 case CmpInst::ICMP_SGT:
408 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
409 BuildMI(MBB, TII.get(X86::SETGr), ResultReg);
411 case CmpInst::ICMP_SGE:
412 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
413 BuildMI(MBB, TII.get(X86::SETGEr), ResultReg);
415 case CmpInst::ICMP_SLT:
416 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
417 BuildMI(MBB, TII.get(X86::SETLr), ResultReg);
419 case CmpInst::ICMP_SLE:
420 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
421 BuildMI(MBB, TII.get(X86::SETLEr), ResultReg);
427 UpdateValueMap(I, ResultReg);
431 bool X86FastISel::X86SelectZExt(Instruction *I) {
432 // Special-case hack: The only i1 values we know how to produce currently
433 // set the upper bits of an i8 value to zero.
434 if (I->getType() == Type::Int8Ty &&
435 I->getOperand(0)->getType() == Type::Int1Ty) {
436 unsigned ResultReg = getRegForValue(I->getOperand(0));
437 if (ResultReg == 0) return false;
438 UpdateValueMap(I, ResultReg);
445 bool X86FastISel::X86SelectBranch(Instruction *I) {
446 BranchInst *BI = cast<BranchInst>(I);
447 // Unconditional branches are selected by tablegen-generated code.
448 unsigned OpReg = getRegForValue(BI->getCondition());
449 if (OpReg == 0) return false;
450 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
451 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
453 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
454 BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
455 BuildMI(MBB, TII.get(X86::JMP)).addMBB(FalseMBB);
457 MBB->addSuccessor(TrueMBB);
458 MBB->addSuccessor(FalseMBB);
463 bool X86FastISel::X86SelectShift(Instruction *I) {
466 const TargetRegisterClass *RC = NULL;
467 if (I->getType() == Type::Int8Ty) {
469 RC = &X86::GR8RegClass;
470 switch (I->getOpcode()) {
471 case Instruction::LShr: Opc = X86::SHR8rCL; break;
472 case Instruction::AShr: Opc = X86::SAR8rCL; break;
473 case Instruction::Shl: Opc = X86::SHL8rCL; break;
474 default: return false;
476 } else if (I->getType() == Type::Int16Ty) {
478 RC = &X86::GR16RegClass;
479 switch (I->getOpcode()) {
480 case Instruction::LShr: Opc = X86::SHR16rCL; break;
481 case Instruction::AShr: Opc = X86::SAR16rCL; break;
482 case Instruction::Shl: Opc = X86::SHL16rCL; break;
483 default: return false;
485 } else if (I->getType() == Type::Int32Ty) {
487 RC = &X86::GR32RegClass;
488 switch (I->getOpcode()) {
489 case Instruction::LShr: Opc = X86::SHR32rCL; break;
490 case Instruction::AShr: Opc = X86::SAR32rCL; break;
491 case Instruction::Shl: Opc = X86::SHL32rCL; break;
492 default: return false;
494 } else if (I->getType() == Type::Int64Ty) {
496 RC = &X86::GR64RegClass;
497 switch (I->getOpcode()) {
498 case Instruction::LShr: Opc = X86::SHR64rCL; break;
499 case Instruction::AShr: Opc = X86::SAR64rCL; break;
500 case Instruction::Shl: Opc = X86::SHL64rCL; break;
501 default: return false;
507 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
508 if (VT == MVT::Other || !TLI.isTypeLegal(VT))
511 unsigned Op0Reg = getRegForValue(I->getOperand(0));
512 if (Op0Reg == 0) return false;
513 unsigned Op1Reg = getRegForValue(I->getOperand(1));
514 if (Op1Reg == 0) return false;
515 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
516 unsigned ResultReg = createResultReg(RC);
517 BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op0Reg);
518 UpdateValueMap(I, ResultReg);
522 bool X86FastISel::X86SelectSelect(Instruction *I) {
523 const Type *Ty = I->getType();
524 if (isa<PointerType>(Ty))
525 Ty = TLI.getTargetData()->getIntPtrType();
528 const TargetRegisterClass *RC = NULL;
529 if (Ty == Type::Int16Ty) {
530 Opc = X86::CMOVE16rr;
531 RC = &X86::GR16RegClass;
532 } else if (Ty == Type::Int32Ty) {
533 Opc = X86::CMOVE32rr;
534 RC = &X86::GR32RegClass;
535 } else if (Ty == Type::Int64Ty) {
536 Opc = X86::CMOVE64rr;
537 RC = &X86::GR64RegClass;
542 MVT VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
543 if (VT == MVT::Other || !TLI.isTypeLegal(VT))
546 unsigned Op0Reg = getRegForValue(I->getOperand(0));
547 if (Op0Reg == 0) return false;
548 unsigned Op1Reg = getRegForValue(I->getOperand(1));
549 if (Op1Reg == 0) return false;
550 unsigned Op2Reg = getRegForValue(I->getOperand(2));
551 if (Op2Reg == 0) return false;
553 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
554 unsigned ResultReg = createResultReg(RC);
555 BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
556 UpdateValueMap(I, ResultReg);
561 X86FastISel::TargetSelectInstruction(Instruction *I) {
562 switch (I->getOpcode()) {
564 case Instruction::Load:
565 return X86SelectLoad(I);
566 case Instruction::Store:
567 return X86SelectStore(I);
568 case Instruction::ICmp:
569 case Instruction::FCmp:
570 return X86SelectCmp(I);
571 case Instruction::ZExt:
572 return X86SelectZExt(I);
573 case Instruction::Br:
574 return X86SelectBranch(I);
575 case Instruction::LShr:
576 case Instruction::AShr:
577 case Instruction::Shl:
578 return X86SelectShift(I);
579 case Instruction::Select:
580 return X86SelectSelect(I);
586 unsigned X86FastISel::TargetMaterializeConstant(Constant *C,
587 MachineConstantPool* MCP) {
588 // Can't handle PIC-mode yet.
589 if (TM.getRelocationModel() == Reloc::PIC_)
592 MVT VT = MVT::getMVT(C->getType(), /*HandleUnknown=*/true);
593 if (VT == MVT::Other || !VT.isSimple())
594 // Unhandled type. Halt "fast" selection and bail.
598 VT = TLI.getPointerTy();
599 // We only handle legal types. For example, on x86-32 the instruction
600 // selector contains all of the 64-bit instructions from x86-64,
601 // under the assumption that i64 won't be used if the target doesn't
603 if (!TLI.isTypeLegal(VT))
606 // Get opcode and regclass of the output for the given load instruction.
608 const TargetRegisterClass *RC = NULL;
609 switch (VT.getSimpleVT()) {
610 default: return false;
613 RC = X86::GR8RegisterClass;
617 RC = X86::GR16RegisterClass;
621 RC = X86::GR32RegisterClass;
624 // Must be in x86-64 mode.
626 RC = X86::GR64RegisterClass;
629 if (Subtarget->hasSSE1()) {
631 RC = X86::FR32RegisterClass;
634 RC = X86::RFP32RegisterClass;
638 if (Subtarget->hasSSE2()) {
640 RC = X86::FR64RegisterClass;
643 RC = X86::RFP64RegisterClass;
648 RC = X86::RFP80RegisterClass;
652 unsigned ResultReg = createResultReg(RC);
653 if (isa<GlobalValue>(C)) {
654 // FIXME: If store value type is something we can't handle, this can result
655 // in a dead stub load instruction.
656 if (X86SelectConstAddr(C, ResultReg))
661 // MachineConstantPool wants an explicit alignment.
663 TM.getTargetData()->getPreferredTypeAlignmentShift(C->getType());
665 // Alignment of vector types. FIXME!
666 Align = TM.getTargetData()->getABITypeSize(C->getType());
667 Align = Log2_64(Align);
670 unsigned MCPOffset = MCP->getConstantPoolIndex(C, Align);
671 addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset);
676 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
677 DenseMap<const Value *, unsigned> &vm,
678 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm) {
679 return new X86FastISel(mf, vm, bm);