1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 class X86FastISel : public FastISel {
28 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
29 /// make the right decision when generating code for different targets.
30 const X86Subtarget *Subtarget;
33 explicit X86FastISel(MachineFunction &mf,
34 DenseMap<const Value *, unsigned> &vm,
35 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm)
36 : FastISel(mf, vm, bm) {
37 Subtarget = &TM.getSubtarget<X86Subtarget>();
40 virtual bool TargetSelectInstruction(Instruction *I);
42 #include "X86GenFastISel.inc"
45 bool X86SelectConstAddr(Value *V, unsigned &Op0);
47 bool X86SelectLoad(Instruction *I);
50 /// X86SelectConstAddr - Select and emit code to materialize constant address.
52 bool X86FastISel::X86SelectConstAddr(Value *V,
54 // FIXME: Only GlobalAddress for now.
55 GlobalValue *GV = dyn_cast<GlobalValue>(V);
59 if (Subtarget->GVRequiresExtraLoad(GV, TM, false)) {
60 // Issue load from stub if necessary.
62 const TargetRegisterClass *RC = NULL;
63 if (TLI.getPointerTy() == MVT::i32) {
65 RC = X86::GR32RegisterClass;
68 RC = X86::GR64RegisterClass;
70 Op0 = createResultReg(RC);
73 addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
78 /// X86SelectLoad - Select and emit code to implement load instructions.
80 bool X86FastISel::X86SelectLoad(Instruction *I) {
81 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
82 if (VT == MVT::Other || !VT.isSimple())
83 // Unhandled type. Halt "fast" selection and bail.
87 VT = TLI.getPointerTy();
88 // We only handle legal types. For example, on x86-32 the instruction
89 // selector contains all of the 64-bit instructions from x86-64,
90 // under the assumption that i64 won't be used if the target doesn't
92 if (!TLI.isTypeLegal(VT))
95 Value *V = I->getOperand(0);
96 unsigned Op0 = getRegForValue(V);
98 // Handle constant load address.
99 if (!isa<Constant>(V) || !X86SelectConstAddr(V, Op0))
100 // Unhandled operand. Halt "fast" selection and bail.
104 // Get opcode and regclass of the output for the given load instruction.
106 const TargetRegisterClass *RC = NULL;
107 switch (VT.getSimpleVT()) {
108 default: return false;
111 RC = X86::GR8RegisterClass;
115 RC = X86::GR16RegisterClass;
119 RC = X86::GR32RegisterClass;
122 // Must be in x86-64 mode.
124 RC = X86::GR64RegisterClass;
127 if (Subtarget->hasSSE1()) {
129 RC = X86::FR32RegisterClass;
132 RC = X86::RFP32RegisterClass;
136 if (Subtarget->hasSSE2()) {
138 RC = X86::FR64RegisterClass;
141 RC = X86::RFP64RegisterClass;
146 RC = X86::RFP80RegisterClass;
150 unsigned ResultReg = createResultReg(RC);
153 // Address is in register.
156 AM.GV = cast<GlobalValue>(V);
157 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
158 UpdateValueMap(I, ResultReg);
164 X86FastISel::TargetSelectInstruction(Instruction *I) {
165 switch (I->getOpcode()) {
167 case Instruction::Load:
168 return X86SelectLoad(I);
175 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
176 DenseMap<const Value *, unsigned> &vm,
177 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm) {
178 return new X86FastISel(mf, vm, bm);