1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 class X86FastISel : public FastISel {
28 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
29 /// make the right decision when generating code for different targets.
30 const X86Subtarget *Subtarget;
33 explicit X86FastISel(MachineFunction &mf) : FastISel(mf) {
34 Subtarget = &TM.getSubtarget<X86Subtarget>();
38 TargetSelectInstruction(Instruction *I,
39 DenseMap<const Value *, unsigned> &ValueMap,
40 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
41 MachineBasicBlock *MBB);
43 #include "X86GenFastISel.inc"
46 bool X86SelectConstAddr(Value *V,
47 DenseMap<const Value *, unsigned> &ValueMap,
48 MachineBasicBlock *MBB, unsigned &Op0);
50 bool X86SelectLoad(Instruction *I,
51 DenseMap<const Value *, unsigned> &ValueMap,
52 MachineBasicBlock *MBB);
55 /// X86SelectConstAddr - Select and emit code to materialize constant address.
57 bool X86FastISel::X86SelectConstAddr(Value *V,
58 DenseMap<const Value *, unsigned> &ValueMap,
59 MachineBasicBlock *MBB,
61 // FIXME: Only GlobalAddress for now.
62 GlobalValue *GV = dyn_cast<GlobalValue>(V);
66 if (Subtarget->GVRequiresExtraLoad(GV, TM, false)) {
67 // Issue load from stub if necessary.
69 const TargetRegisterClass *RC = NULL;
70 if (TLI.getPointerTy() == MVT::i32) {
72 RC = X86::GR32RegisterClass;
75 RC = X86::GR64RegisterClass;
77 Op0 = createResultReg(RC);
80 addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
85 /// X86SelectLoad - Select and emit code to implement load instructions.
87 bool X86FastISel::X86SelectLoad(Instruction *I,
88 DenseMap<const Value *, unsigned> &ValueMap,
89 MachineBasicBlock *MBB) {
90 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
91 if (VT == MVT::Other || !VT.isSimple())
92 // Unhandled type. Halt "fast" selection and bail.
96 VT = TLI.getPointerTy();
97 // We only handle legal types. For example, on x86-32 the instruction
98 // selector contains all of the 64-bit instructions from x86-64,
99 // under the assumption that i64 won't be used if the target doesn't
101 if (!TLI.isTypeLegal(VT))
104 Value *V = I->getOperand(0);
105 unsigned Op0 = getRegForValue(V, ValueMap);
107 // Handle constant load address.
108 if (!isa<Constant>(V) || !X86SelectConstAddr(V, ValueMap, MBB, Op0))
109 // Unhandled operand. Halt "fast" selection and bail.
113 // Get opcode and regclass of the output for the given load instruction.
115 const TargetRegisterClass *RC = NULL;
116 switch (VT.getSimpleVT()) {
117 default: return false;
120 RC = X86::GR8RegisterClass;
124 RC = X86::GR16RegisterClass;
128 RC = X86::GR32RegisterClass;
131 // Must be in x86-64 mode.
133 RC = X86::GR64RegisterClass;
136 if (Subtarget->hasSSE1()) {
138 RC = X86::FR32RegisterClass;
141 RC = X86::RFP32RegisterClass;
145 if (Subtarget->hasSSE2()) {
147 RC = X86::FR64RegisterClass;
150 RC = X86::RFP64RegisterClass;
155 RC = X86::RFP80RegisterClass;
159 unsigned ResultReg = createResultReg(RC);
162 // Address is in register.
165 AM.GV = cast<GlobalValue>(V);
166 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
167 UpdateValueMap(I, ResultReg, ValueMap);
173 X86FastISel::TargetSelectInstruction(Instruction *I,
174 DenseMap<const Value *, unsigned> &ValueMap,
175 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
176 MachineBasicBlock *MBB) {
177 switch (I->getOpcode()) {
179 case Instruction::Load:
180 return X86SelectLoad(I, ValueMap, MBB);
187 llvm::FastISel *X86::createFastISel(MachineFunction &mf) {
188 return new X86FastISel(mf);