1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Support/CallSite.h"
32 #include "llvm/Support/GetElementPtrTypeIterator.h"
37 class X86FastISel : public FastISel {
38 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
39 /// make the right decision when generating code for different targets.
40 const X86Subtarget *Subtarget;
42 /// StackPtr - Register used as the stack pointer.
46 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
47 /// floating point ops.
48 /// When SSE is available, use it for f32 operations.
49 /// When SSE2 is available, use it for f64 operations.
54 explicit X86FastISel(MachineFunction &mf,
55 MachineModuleInfo *mmi,
57 DenseMap<const Value *, unsigned> &vm,
58 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
59 DenseMap<const AllocaInst *, int> &am
61 , SmallSet<Instruction*, 8> &cil
64 : FastISel(mf, mmi, dw, vm, bm, am
69 Subtarget = &TM.getSubtarget<X86Subtarget>();
70 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
71 X86ScalarSSEf64 = Subtarget->hasSSE2();
72 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 virtual bool TargetSelectInstruction(Instruction *I);
77 #include "X86GenFastISel.inc"
80 bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
82 bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
84 bool X86FastEmitStore(MVT VT, Value *Val,
85 const X86AddressMode &AM);
86 bool X86FastEmitStore(MVT VT, unsigned Val,
87 const X86AddressMode &AM);
89 bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
92 bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
94 bool X86SelectLoad(Instruction *I);
96 bool X86SelectStore(Instruction *I);
98 bool X86SelectCmp(Instruction *I);
100 bool X86SelectZExt(Instruction *I);
102 bool X86SelectBranch(Instruction *I);
104 bool X86SelectShift(Instruction *I);
106 bool X86SelectSelect(Instruction *I);
108 bool X86SelectTrunc(Instruction *I);
110 bool X86SelectFPExt(Instruction *I);
111 bool X86SelectFPTrunc(Instruction *I);
113 bool X86SelectExtractValue(Instruction *I);
115 bool X86VisitIntrinsicCall(IntrinsicInst &I);
116 bool X86SelectCall(Instruction *I);
118 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
120 const X86InstrInfo *getInstrInfo() const {
121 return getTargetMachine()->getInstrInfo();
123 const X86TargetMachine *getTargetMachine() const {
124 return static_cast<const X86TargetMachine *>(&TM);
127 unsigned TargetMaterializeConstant(Constant *C);
129 unsigned TargetMaterializeAlloca(AllocaInst *C);
131 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
132 /// computed in an SSE register, not on the X87 floating point stack.
133 bool isScalarFPTypeInSSEReg(MVT VT) const {
134 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
135 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
138 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
141 } // end anonymous namespace.
143 bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
144 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
145 if (VT == MVT::Other || !VT.isSimple())
146 // Unhandled type. Halt "fast" selection and bail.
149 // For now, require SSE/SSE2 for performing floating-point operations,
150 // since x87 requires additional work.
151 if (VT == MVT::f64 && !X86ScalarSSEf64)
153 if (VT == MVT::f32 && !X86ScalarSSEf32)
155 // Similarly, no f80 support yet.
158 // We only handle legal types. For example, on x86-32 the instruction
159 // selector contains all of the 64-bit instructions from x86-64,
160 // under the assumption that i64 won't be used if the target doesn't
162 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
165 #include "X86GenCallingConv.inc"
167 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
169 CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
170 if (Subtarget->is64Bit()) {
171 if (Subtarget->isTargetWin64())
172 return CC_X86_Win64_C;
173 else if (CC == CallingConv::Fast && isTaillCall)
174 return CC_X86_64_TailCall;
179 if (CC == CallingConv::X86_FastCall)
180 return CC_X86_32_FastCall;
181 else if (CC == CallingConv::Fast)
182 return CC_X86_32_FastCC;
187 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
188 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
189 /// Return true and the result register by reference if it is possible.
190 bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
191 unsigned &ResultReg) {
192 // Get opcode and regclass of the output for the given load instruction.
194 const TargetRegisterClass *RC = NULL;
195 switch (VT.getSimpleVT()) {
196 default: return false;
199 RC = X86::GR8RegisterClass;
203 RC = X86::GR16RegisterClass;
207 RC = X86::GR32RegisterClass;
210 // Must be in x86-64 mode.
212 RC = X86::GR64RegisterClass;
215 if (Subtarget->hasSSE1()) {
217 RC = X86::FR32RegisterClass;
220 RC = X86::RFP32RegisterClass;
224 if (Subtarget->hasSSE2()) {
226 RC = X86::FR64RegisterClass;
229 RC = X86::RFP64RegisterClass;
233 // No f80 support yet.
237 ResultReg = createResultReg(RC);
238 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
242 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
243 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
244 /// and a displacement offset, or a GlobalAddress,
245 /// i.e. V. Return true if it is possible.
247 X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
248 const X86AddressMode &AM) {
249 // Get opcode and regclass of the output for the given store instruction.
251 switch (VT.getSimpleVT()) {
252 case MVT::f80: // No f80 support yet.
253 default: return false;
254 case MVT::i8: Opc = X86::MOV8mr; break;
255 case MVT::i16: Opc = X86::MOV16mr; break;
256 case MVT::i32: Opc = X86::MOV32mr; break;
257 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
259 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
262 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
266 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
270 bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val,
271 const X86AddressMode &AM) {
272 // Handle 'null' like i32/i64 0.
273 if (isa<ConstantPointerNull>(Val))
274 Val = Constant::getNullValue(TD.getIntPtrType());
276 // If this is a store of a simple constant, fold the constant into the store.
277 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
279 switch (VT.getSimpleVT()) {
281 case MVT::i8: Opc = X86::MOV8mi; break;
282 case MVT::i16: Opc = X86::MOV16mi; break;
283 case MVT::i32: Opc = X86::MOV32mi; break;
285 // Must be a 32-bit sign extended value.
286 if ((int)CI->getSExtValue() == CI->getSExtValue())
287 Opc = X86::MOV64mi32;
292 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
293 .addImm(CI->getSExtValue());
298 unsigned ValReg = getRegForValue(Val);
302 return X86FastEmitStore(VT, ValReg, AM);
305 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
306 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
307 /// ISD::SIGN_EXTEND).
308 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
309 unsigned Src, MVT SrcVT,
310 unsigned &ResultReg) {
311 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
320 /// X86SelectAddress - Attempt to fill in an address from the given value.
322 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
324 unsigned Opcode = Instruction::UserOp1;
325 if (Instruction *I = dyn_cast<Instruction>(V)) {
326 Opcode = I->getOpcode();
328 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
329 Opcode = C->getOpcode();
335 case Instruction::BitCast:
336 // Look past bitcasts.
337 return X86SelectAddress(U->getOperand(0), AM, isCall);
339 case Instruction::IntToPtr:
340 // Look past no-op inttoptrs.
341 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
342 return X86SelectAddress(U->getOperand(0), AM, isCall);
345 case Instruction::PtrToInt:
346 // Look past no-op ptrtoints.
347 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
348 return X86SelectAddress(U->getOperand(0), AM, isCall);
351 case Instruction::Alloca: {
353 // Do static allocas.
354 const AllocaInst *A = cast<AllocaInst>(V);
355 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
356 if (SI != StaticAllocaMap.end()) {
357 AM.BaseType = X86AddressMode::FrameIndexBase;
358 AM.Base.FrameIndex = SI->second;
364 case Instruction::Add: {
366 // Adds of constants are common and easy enough.
367 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
368 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
369 // They have to fit in the 32-bit signed displacement field though.
371 AM.Disp = (uint32_t)Disp;
372 return X86SelectAddress(U->getOperand(0), AM, isCall);
378 case Instruction::GetElementPtr: {
380 // Pattern-match simple GEPs.
381 uint64_t Disp = (int32_t)AM.Disp;
382 unsigned IndexReg = AM.IndexReg;
383 unsigned Scale = AM.Scale;
384 gep_type_iterator GTI = gep_type_begin(U);
385 // Iterate through the indices, folding what we can. Constants can be
386 // folded, and one dynamic index can be handled, if the scale is supported.
387 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
388 i != e; ++i, ++GTI) {
390 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
391 const StructLayout *SL = TD.getStructLayout(STy);
392 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
393 Disp += SL->getElementOffset(Idx);
395 uint64_t S = TD.getTypePaddedSize(GTI.getIndexedType());
396 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
397 // Constant-offset addressing.
398 Disp += CI->getSExtValue() * S;
399 } else if (IndexReg == 0 &&
401 !getTargetMachine()->symbolicAddressesAreRIPRel()) &&
402 (S == 1 || S == 2 || S == 4 || S == 8)) {
403 // Scaled-index addressing.
405 IndexReg = getRegForGEPIndex(Op);
410 goto unsupported_gep;
413 // Check for displacement overflow.
416 // Ok, the GEP indices were covered by constant-offset and scaled-index
417 // addressing. Update the address state and move on to examining the base.
418 AM.IndexReg = IndexReg;
420 AM.Disp = (uint32_t)Disp;
421 return X86SelectAddress(U->getOperand(0), AM, isCall);
423 // Ok, the GEP indices weren't all covered.
428 // Handle constant address.
429 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
430 // Can't handle alternate code models yet.
431 if (TM.getCodeModel() != CodeModel::Default &&
432 TM.getCodeModel() != CodeModel::Small)
435 // RIP-relative addresses can't have additional register operands.
436 if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
437 (AM.Base.Reg != 0 || AM.IndexReg != 0))
440 // Can't handle TLS yet.
441 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
442 if (GVar->isThreadLocal())
445 // Set up the basic address.
448 TM.getRelocationModel() == Reloc::PIC_ &&
449 !Subtarget->is64Bit())
450 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
452 // Emit an extra load if the ABI requires it.
453 if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
454 // Check to see if we've already materialized this
455 // value in a register in this block.
456 if (unsigned Reg = LocalValueMap[V]) {
461 // Issue load from stub if necessary.
463 const TargetRegisterClass *RC = NULL;
464 if (TLI.getPointerTy() == MVT::i32) {
466 RC = X86::GR32RegisterClass;
469 RC = X86::GR64RegisterClass;
472 X86AddressMode StubAM;
473 StubAM.Base.Reg = AM.Base.Reg;
475 unsigned ResultReg = createResultReg(RC);
476 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), StubAM);
478 // Now construct the final address. Note that the Disp, Scale,
479 // and Index values may already be set here.
480 AM.Base.Reg = ResultReg;
483 // Prevent loading GV stub multiple times in same MBB.
484 LocalValueMap[V] = AM.Base.Reg;
489 // If all else fails, try to materialize the value in a register.
490 if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
491 if (AM.Base.Reg == 0) {
492 AM.Base.Reg = getRegForValue(V);
493 return AM.Base.Reg != 0;
495 if (AM.IndexReg == 0) {
496 assert(AM.Scale == 1 && "Scale with no index!");
497 AM.IndexReg = getRegForValue(V);
498 return AM.IndexReg != 0;
505 /// X86SelectStore - Select and emit code to implement store instructions.
506 bool X86FastISel::X86SelectStore(Instruction* I) {
508 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
512 if (!X86SelectAddress(I->getOperand(1), AM, false))
515 return X86FastEmitStore(VT, I->getOperand(0), AM);
518 /// X86SelectLoad - Select and emit code to implement load instructions.
520 bool X86FastISel::X86SelectLoad(Instruction *I) {
522 if (!isTypeLegal(I->getType(), VT))
526 if (!X86SelectAddress(I->getOperand(0), AM, false))
529 unsigned ResultReg = 0;
530 if (X86FastEmitLoad(VT, AM, ResultReg)) {
531 UpdateValueMap(I, ResultReg);
537 static unsigned X86ChooseCmpOpcode(MVT VT) {
538 switch (VT.getSimpleVT()) {
540 case MVT::i8: return X86::CMP8rr;
541 case MVT::i16: return X86::CMP16rr;
542 case MVT::i32: return X86::CMP32rr;
543 case MVT::i64: return X86::CMP64rr;
544 case MVT::f32: return X86::UCOMISSrr;
545 case MVT::f64: return X86::UCOMISDrr;
549 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
550 /// of the comparison, return an opcode that works for the compare (e.g.
551 /// CMP32ri) otherwise return 0.
552 static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
553 switch (VT.getSimpleVT()) {
554 // Otherwise, we can't fold the immediate into this comparison.
556 case MVT::i8: return X86::CMP8ri;
557 case MVT::i16: return X86::CMP16ri;
558 case MVT::i32: return X86::CMP32ri;
560 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
562 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
563 return X86::CMP64ri32;
568 bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
569 unsigned Op0Reg = getRegForValue(Op0);
570 if (Op0Reg == 0) return false;
572 // Handle 'null' like i32/i64 0.
573 if (isa<ConstantPointerNull>(Op1))
574 Op1 = Constant::getNullValue(TD.getIntPtrType());
576 // We have two options: compare with register or immediate. If the RHS of
577 // the compare is an immediate that we can fold into this compare, use
578 // CMPri, otherwise use CMPrr.
579 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
580 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
581 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
582 .addImm(Op1C->getSExtValue());
587 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
588 if (CompareOpc == 0) return false;
590 unsigned Op1Reg = getRegForValue(Op1);
591 if (Op1Reg == 0) return false;
592 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
597 bool X86FastISel::X86SelectCmp(Instruction *I) {
598 CmpInst *CI = cast<CmpInst>(I);
601 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
604 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
606 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
607 switch (CI->getPredicate()) {
608 case CmpInst::FCMP_OEQ: {
609 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
612 unsigned EReg = createResultReg(&X86::GR8RegClass);
613 unsigned NPReg = createResultReg(&X86::GR8RegClass);
614 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
615 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
617 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
618 UpdateValueMap(I, ResultReg);
621 case CmpInst::FCMP_UNE: {
622 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
625 unsigned NEReg = createResultReg(&X86::GR8RegClass);
626 unsigned PReg = createResultReg(&X86::GR8RegClass);
627 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
628 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
629 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
630 UpdateValueMap(I, ResultReg);
633 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
634 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
635 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
636 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
637 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
638 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
639 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
640 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
641 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
642 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
643 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
644 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
646 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
647 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
648 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
649 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
650 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
651 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
652 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
653 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
654 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
655 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
660 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
664 // Emit a compare of Op0/Op1.
665 if (!X86FastEmitCompare(Op0, Op1, VT))
668 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
669 UpdateValueMap(I, ResultReg);
673 bool X86FastISel::X86SelectZExt(Instruction *I) {
674 // Handle zero-extension from i1 to i8, which is common.
675 if (I->getType() == Type::Int8Ty &&
676 I->getOperand(0)->getType() == Type::Int1Ty) {
677 unsigned ResultReg = getRegForValue(I->getOperand(0));
678 if (ResultReg == 0) return false;
679 // Set the high bits to zero.
680 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
681 if (ResultReg == 0) return false;
682 UpdateValueMap(I, ResultReg);
690 bool X86FastISel::X86SelectBranch(Instruction *I) {
691 // Unconditional branches are selected by tablegen-generated code.
692 // Handle a conditional branch.
693 BranchInst *BI = cast<BranchInst>(I);
694 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
695 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
697 // Fold the common case of a conditional branch with a comparison.
698 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
699 if (CI->hasOneUse()) {
700 MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
702 // Try to take advantage of fallthrough opportunities.
703 CmpInst::Predicate Predicate = CI->getPredicate();
704 if (MBB->isLayoutSuccessor(TrueMBB)) {
705 std::swap(TrueMBB, FalseMBB);
706 Predicate = CmpInst::getInversePredicate(Predicate);
709 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
710 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
713 case CmpInst::FCMP_OEQ:
714 std::swap(TrueMBB, FalseMBB);
715 Predicate = CmpInst::FCMP_UNE;
717 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break;
718 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break;
719 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
720 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break;
721 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break;
722 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
723 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
724 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break;
725 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break;
726 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break;
727 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break;
728 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
729 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
731 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break;
732 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break;
733 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break;
734 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
735 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
736 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
737 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break;
738 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
739 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break;
740 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
745 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
749 // Emit a compare of the LHS and RHS, setting the flags.
750 if (!X86FastEmitCompare(Op0, Op1, VT))
753 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
755 if (Predicate == CmpInst::FCMP_UNE) {
756 // X86 requires a second branch to handle UNE (and OEQ,
757 // which is mapped to UNE above).
758 BuildMI(MBB, DL, TII.get(X86::JP)).addMBB(TrueMBB);
761 FastEmitBranch(FalseMBB);
762 MBB->addSuccessor(TrueMBB);
765 } else if (ExtractValueInst *EI =
766 dyn_cast<ExtractValueInst>(BI->getCondition())) {
767 // Check to see if the branch instruction is from an "arithmetic with
768 // overflow" intrinsic. The main way these intrinsics are used is:
770 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
771 // %sum = extractvalue { i32, i1 } %t, 0
772 // %obit = extractvalue { i32, i1 } %t, 1
773 // br i1 %obit, label %overflow, label %normal
775 // The %sum and %obit are converted in an ADD and a SETO/SETB before
776 // reaching the branch. Therefore, we search backwards through the MBB
777 // looking for the SETO/SETB instruction. If an instruction modifies the
778 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
779 // convert the branch into a JO/JB instruction.
780 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
781 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
782 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
783 const MachineInstr *SetMI = 0;
784 unsigned Reg = lookUpRegForValue(EI);
786 for (MachineBasicBlock::const_reverse_iterator
787 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
788 const MachineInstr &MI = *RI;
790 if (MI.modifiesRegister(Reg)) {
791 unsigned Src, Dst, SrcSR, DstSR;
793 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
802 const TargetInstrDesc &TID = MI.getDesc();
803 if (TID.hasUnmodeledSideEffects() ||
804 TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
809 unsigned OpCode = SetMI->getOpcode();
811 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
812 BuildMI(MBB, DL, TII.get((OpCode == X86::SETOr) ?
813 X86::JO : X86::JB)).addMBB(TrueMBB);
814 FastEmitBranch(FalseMBB);
815 MBB->addSuccessor(TrueMBB);
823 // Otherwise do a clumsy setcc and re-test it.
824 unsigned OpReg = getRegForValue(BI->getCondition());
825 if (OpReg == 0) return false;
827 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
828 BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(TrueMBB);
829 FastEmitBranch(FalseMBB);
830 MBB->addSuccessor(TrueMBB);
834 bool X86FastISel::X86SelectShift(Instruction *I) {
835 unsigned CReg = 0, OpReg = 0, OpImm = 0;
836 const TargetRegisterClass *RC = NULL;
837 if (I->getType() == Type::Int8Ty) {
839 RC = &X86::GR8RegClass;
840 switch (I->getOpcode()) {
841 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
842 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
843 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
844 default: return false;
846 } else if (I->getType() == Type::Int16Ty) {
848 RC = &X86::GR16RegClass;
849 switch (I->getOpcode()) {
850 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
851 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
852 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
853 default: return false;
855 } else if (I->getType() == Type::Int32Ty) {
857 RC = &X86::GR32RegClass;
858 switch (I->getOpcode()) {
859 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
860 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
861 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
862 default: return false;
864 } else if (I->getType() == Type::Int64Ty) {
866 RC = &X86::GR64RegClass;
867 switch (I->getOpcode()) {
868 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
869 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
870 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
871 default: return false;
877 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
878 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
881 unsigned Op0Reg = getRegForValue(I->getOperand(0));
882 if (Op0Reg == 0) return false;
884 // Fold immediate in shl(x,3).
885 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
886 unsigned ResultReg = createResultReg(RC);
887 BuildMI(MBB, DL, TII.get(OpImm),
888 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
889 UpdateValueMap(I, ResultReg);
893 unsigned Op1Reg = getRegForValue(I->getOperand(1));
894 if (Op1Reg == 0) return false;
895 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
897 // The shift instruction uses X86::CL. If we defined a super-register
898 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
901 BuildMI(MBB, DL, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
902 .addReg(CReg).addImm(X86::SUBREG_8BIT);
904 unsigned ResultReg = createResultReg(RC);
905 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
906 UpdateValueMap(I, ResultReg);
910 bool X86FastISel::X86SelectSelect(Instruction *I) {
911 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
912 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
916 const TargetRegisterClass *RC = NULL;
917 if (VT.getSimpleVT() == MVT::i16) {
918 Opc = X86::CMOVE16rr;
919 RC = &X86::GR16RegClass;
920 } else if (VT.getSimpleVT() == MVT::i32) {
921 Opc = X86::CMOVE32rr;
922 RC = &X86::GR32RegClass;
923 } else if (VT.getSimpleVT() == MVT::i64) {
924 Opc = X86::CMOVE64rr;
925 RC = &X86::GR64RegClass;
930 unsigned Op0Reg = getRegForValue(I->getOperand(0));
931 if (Op0Reg == 0) return false;
932 unsigned Op1Reg = getRegForValue(I->getOperand(1));
933 if (Op1Reg == 0) return false;
934 unsigned Op2Reg = getRegForValue(I->getOperand(2));
935 if (Op2Reg == 0) return false;
937 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
938 unsigned ResultReg = createResultReg(RC);
939 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
940 UpdateValueMap(I, ResultReg);
944 bool X86FastISel::X86SelectFPExt(Instruction *I) {
945 // fpext from float to double.
946 if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
947 Value *V = I->getOperand(0);
948 if (V->getType() == Type::FloatTy) {
949 unsigned OpReg = getRegForValue(V);
950 if (OpReg == 0) return false;
951 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
952 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
953 UpdateValueMap(I, ResultReg);
961 bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
962 if (Subtarget->hasSSE2()) {
963 if (I->getType() == Type::FloatTy) {
964 Value *V = I->getOperand(0);
965 if (V->getType() == Type::DoubleTy) {
966 unsigned OpReg = getRegForValue(V);
967 if (OpReg == 0) return false;
968 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
969 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
970 UpdateValueMap(I, ResultReg);
979 bool X86FastISel::X86SelectTrunc(Instruction *I) {
980 if (Subtarget->is64Bit())
981 // All other cases should be handled by the tblgen generated code.
983 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
984 MVT DstVT = TLI.getValueType(I->getType());
986 // This code only handles truncation to byte right now.
987 if (DstVT != MVT::i8 && DstVT != MVT::i1)
988 // All other cases should be handled by the tblgen generated code.
990 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
991 // All other cases should be handled by the tblgen generated code.
994 unsigned InputReg = getRegForValue(I->getOperand(0));
996 // Unhandled operand. Halt "fast" selection and bail.
999 // First issue a copy to GR16_ or GR32_.
1000 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16to16_ : X86::MOV32to32_;
1001 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1002 ? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
1003 unsigned CopyReg = createResultReg(CopyRC);
1004 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1006 // Then issue an extract_subreg.
1007 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1008 CopyReg, X86::SUBREG_8BIT);
1012 UpdateValueMap(I, ResultReg);
1016 bool X86FastISel::X86SelectExtractValue(Instruction *I) {
1017 ExtractValueInst *EI = cast<ExtractValueInst>(I);
1018 Value *Agg = EI->getAggregateOperand();
1020 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1021 switch (CI->getIntrinsicID()) {
1023 case Intrinsic::sadd_with_overflow:
1024 case Intrinsic::uadd_with_overflow:
1025 // Cheat a little. We know that the registers for "add" and "seto" are
1026 // allocated sequentially. However, we only keep track of the register
1027 // for "add" in the value map. Use extractvalue's index to get the
1028 // correct register for "seto".
1029 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1037 bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) {
1038 // FIXME: Handle more intrinsics.
1039 switch (I.getIntrinsicID()) {
1040 default: return false;
1041 case Intrinsic::sadd_with_overflow:
1042 case Intrinsic::uadd_with_overflow: {
1043 // Replace "add with overflow" intrinsics with an "add" instruction followed
1044 // by a seto/setc instruction. Later on, when the "extractvalue"
1045 // instructions are encountered, we use the fact that two registers were
1046 // created sequentially to get the correct registers for the "sum" and the
1048 const Function *Callee = I.getCalledFunction();
1050 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1053 if (!isTypeLegal(RetTy, VT))
1056 Value *Op1 = I.getOperand(1);
1057 Value *Op2 = I.getOperand(2);
1058 unsigned Reg1 = getRegForValue(Op1);
1059 unsigned Reg2 = getRegForValue(Op2);
1061 if (Reg1 == 0 || Reg2 == 0)
1062 // FIXME: Handle values *not* in registers.
1068 else if (VT == MVT::i64)
1073 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1074 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1075 UpdateValueMap(&I, ResultReg);
1077 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1078 unsigned Opc = X86::SETBr;
1079 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1081 BuildMI(MBB, DL, TII.get(Opc), ResultReg);
1087 bool X86FastISel::X86SelectCall(Instruction *I) {
1088 CallInst *CI = cast<CallInst>(I);
1089 Value *Callee = I->getOperand(0);
1091 // Can't handle inline asm yet.
1092 if (isa<InlineAsm>(Callee))
1095 // Handle intrinsic calls.
1096 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1097 return X86VisitIntrinsicCall(*II);
1099 // Handle only C and fastcc calling conventions for now.
1101 unsigned CC = CS.getCallingConv();
1102 if (CC != CallingConv::C &&
1103 CC != CallingConv::Fast &&
1104 CC != CallingConv::X86_FastCall)
1107 // Let SDISel handle vararg functions.
1108 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1109 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1110 if (FTy->isVarArg())
1113 // Handle *simple* calls for now.
1114 const Type *RetTy = CS.getType();
1116 if (RetTy == Type::VoidTy)
1117 RetVT = MVT::isVoid;
1118 else if (!isTypeLegal(RetTy, RetVT, true))
1121 // Materialize callee address in a register. FIXME: GV address can be
1122 // handled with a CALLpcrel32 instead.
1123 X86AddressMode CalleeAM;
1124 if (!X86SelectAddress(Callee, CalleeAM, true))
1126 unsigned CalleeOp = 0;
1127 GlobalValue *GV = 0;
1128 if (CalleeAM.Base.Reg != 0) {
1129 assert(CalleeAM.GV == 0);
1130 CalleeOp = CalleeAM.Base.Reg;
1131 } else if (CalleeAM.GV != 0) {
1132 assert(CalleeAM.GV != 0);
1137 // Allow calls which produce i1 results.
1138 bool AndToI1 = false;
1139 if (RetVT == MVT::i1) {
1144 // Deal with call operands first.
1145 SmallVector<Value*, 8> ArgVals;
1146 SmallVector<unsigned, 8> Args;
1147 SmallVector<MVT, 8> ArgVTs;
1148 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1149 Args.reserve(CS.arg_size());
1150 ArgVals.reserve(CS.arg_size());
1151 ArgVTs.reserve(CS.arg_size());
1152 ArgFlags.reserve(CS.arg_size());
1153 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1155 unsigned Arg = getRegForValue(*i);
1158 ISD::ArgFlagsTy Flags;
1159 unsigned AttrInd = i - CS.arg_begin() + 1;
1160 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1162 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1165 // FIXME: Only handle *easy* calls for now.
1166 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1167 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1168 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1169 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1172 const Type *ArgTy = (*i)->getType();
1174 if (!isTypeLegal(ArgTy, ArgVT))
1176 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1177 Flags.setOrigAlign(OriginalAlignment);
1179 Args.push_back(Arg);
1180 ArgVals.push_back(*i);
1181 ArgVTs.push_back(ArgVT);
1182 ArgFlags.push_back(Flags);
1185 // Analyze operands of the call, assigning locations to each operand.
1186 SmallVector<CCValAssign, 16> ArgLocs;
1187 CCState CCInfo(CC, false, TM, ArgLocs);
1188 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1190 // Get a count of how many bytes are to be pushed on the stack.
1191 unsigned NumBytes = CCInfo.getNextStackOffset();
1193 // Issue CALLSEQ_START
1194 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1195 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1197 // Process argument: walk the register/memloc assignments, inserting
1199 SmallVector<unsigned, 4> RegArgs;
1200 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1201 CCValAssign &VA = ArgLocs[i];
1202 unsigned Arg = Args[VA.getValNo()];
1203 MVT ArgVT = ArgVTs[VA.getValNo()];
1205 // Promote the value if needed.
1206 switch (VA.getLocInfo()) {
1207 default: assert(0 && "Unknown loc info!");
1208 case CCValAssign::Full: break;
1209 case CCValAssign::SExt: {
1210 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1212 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1214 ArgVT = VA.getLocVT();
1217 case CCValAssign::ZExt: {
1218 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1220 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1222 ArgVT = VA.getLocVT();
1225 case CCValAssign::AExt: {
1226 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1229 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1232 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1235 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1236 ArgVT = VA.getLocVT();
1241 if (VA.isRegLoc()) {
1242 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1243 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1245 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1247 RegArgs.push_back(VA.getLocReg());
1249 unsigned LocMemOffset = VA.getLocMemOffset();
1251 AM.Base.Reg = StackPtr;
1252 AM.Disp = LocMemOffset;
1253 Value *ArgVal = ArgVals[VA.getValNo()];
1255 // If this is a really simple value, emit this with the Value* version of
1256 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1257 // can cause us to reevaluate the argument.
1258 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1259 X86FastEmitStore(ArgVT, ArgVal, AM);
1261 X86FastEmitStore(ArgVT, Arg, AM);
1265 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1267 if (!Subtarget->is64Bit() &&
1268 TM.getRelocationModel() == Reloc::PIC_ &&
1269 Subtarget->isPICStyleGOT()) {
1270 TargetRegisterClass *RC = X86::GR32RegisterClass;
1271 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1272 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1273 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1278 unsigned CallOpc = CalleeOp
1279 ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
1280 : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
1281 MachineInstrBuilder MIB = CalleeOp
1282 ? BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp)
1283 : BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV);
1285 // Add an implicit use GOT pointer in EBX.
1286 if (!Subtarget->is64Bit() &&
1287 TM.getRelocationModel() == Reloc::PIC_ &&
1288 Subtarget->isPICStyleGOT())
1289 MIB.addReg(X86::EBX);
1291 // Add implicit physical register uses to the call.
1292 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1293 MIB.addReg(RegArgs[i]);
1295 // Issue CALLSEQ_END
1296 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1297 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1299 // Now handle call return value (if any).
1300 if (RetVT.getSimpleVT() != MVT::isVoid) {
1301 SmallVector<CCValAssign, 16> RVLocs;
1302 CCState CCInfo(CC, false, TM, RVLocs);
1303 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1305 // Copy all of the result registers out of their specified physreg.
1306 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1307 MVT CopyVT = RVLocs[0].getValVT();
1308 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1309 TargetRegisterClass *SrcRC = DstRC;
1311 // If this is a call to a function that returns an fp value on the x87 fp
1312 // stack, but where we prefer to use the value in xmm registers, copy it
1313 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1314 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1315 RVLocs[0].getLocReg() == X86::ST1) &&
1316 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1318 SrcRC = X86::RSTRegisterClass;
1319 DstRC = X86::RFP80RegisterClass;
1322 unsigned ResultReg = createResultReg(DstRC);
1323 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1324 RVLocs[0].getLocReg(), DstRC, SrcRC);
1325 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1327 if (CopyVT != RVLocs[0].getValVT()) {
1328 // Round the F80 the right size, which also moves to the appropriate xmm
1329 // register. This is accomplished by storing the F80 value in memory and
1330 // then loading it back. Ewww...
1331 MVT ResVT = RVLocs[0].getValVT();
1332 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1333 unsigned MemSize = ResVT.getSizeInBits()/8;
1334 int FI = MFI.CreateStackObject(MemSize, MemSize);
1335 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1336 DstRC = ResVT == MVT::f32
1337 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1338 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1339 ResultReg = createResultReg(DstRC);
1340 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1344 // Mask out all but lowest bit for some call which produces an i1.
1345 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1347 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1348 ResultReg = AndResult;
1351 UpdateValueMap(I, ResultReg);
1359 X86FastISel::TargetSelectInstruction(Instruction *I) {
1360 switch (I->getOpcode()) {
1362 case Instruction::Load:
1363 return X86SelectLoad(I);
1364 case Instruction::Store:
1365 return X86SelectStore(I);
1366 case Instruction::ICmp:
1367 case Instruction::FCmp:
1368 return X86SelectCmp(I);
1369 case Instruction::ZExt:
1370 return X86SelectZExt(I);
1371 case Instruction::Br:
1372 return X86SelectBranch(I);
1373 case Instruction::Call:
1374 return X86SelectCall(I);
1375 case Instruction::LShr:
1376 case Instruction::AShr:
1377 case Instruction::Shl:
1378 return X86SelectShift(I);
1379 case Instruction::Select:
1380 return X86SelectSelect(I);
1381 case Instruction::Trunc:
1382 return X86SelectTrunc(I);
1383 case Instruction::FPExt:
1384 return X86SelectFPExt(I);
1385 case Instruction::FPTrunc:
1386 return X86SelectFPTrunc(I);
1387 case Instruction::ExtractValue:
1388 return X86SelectExtractValue(I);
1389 case Instruction::IntToPtr: // Deliberate fall-through.
1390 case Instruction::PtrToInt: {
1391 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1392 MVT DstVT = TLI.getValueType(I->getType());
1393 if (DstVT.bitsGT(SrcVT))
1394 return X86SelectZExt(I);
1395 if (DstVT.bitsLT(SrcVT))
1396 return X86SelectTrunc(I);
1397 unsigned Reg = getRegForValue(I->getOperand(0));
1398 if (Reg == 0) return false;
1399 UpdateValueMap(I, Reg);
1407 unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
1409 if (!isTypeLegal(C->getType(), VT))
1412 // Get opcode and regclass of the output for the given load instruction.
1414 const TargetRegisterClass *RC = NULL;
1415 switch (VT.getSimpleVT()) {
1416 default: return false;
1419 RC = X86::GR8RegisterClass;
1423 RC = X86::GR16RegisterClass;
1427 RC = X86::GR32RegisterClass;
1430 // Must be in x86-64 mode.
1432 RC = X86::GR64RegisterClass;
1435 if (Subtarget->hasSSE1()) {
1437 RC = X86::FR32RegisterClass;
1439 Opc = X86::LD_Fp32m;
1440 RC = X86::RFP32RegisterClass;
1444 if (Subtarget->hasSSE2()) {
1446 RC = X86::FR64RegisterClass;
1448 Opc = X86::LD_Fp64m;
1449 RC = X86::RFP64RegisterClass;
1453 // No f80 support yet.
1457 // Materialize addresses with LEA instructions.
1458 if (isa<GlobalValue>(C)) {
1460 if (X86SelectAddress(C, AM, false)) {
1461 if (TLI.getPointerTy() == MVT::i32)
1465 unsigned ResultReg = createResultReg(RC);
1466 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1472 // MachineConstantPool wants an explicit alignment.
1473 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1475 // Alignment of vector types. FIXME!
1476 Align = TD.getTypePaddedSize(C->getType());
1479 // x86-32 PIC requires a PIC base register for constant pools.
1480 unsigned PICBase = 0;
1481 if (TM.getRelocationModel() == Reloc::PIC_ &&
1482 !Subtarget->is64Bit())
1483 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1485 // Create the load from the constant pool.
1486 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1487 unsigned ResultReg = createResultReg(RC);
1488 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), MCPOffset,
1494 unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
1495 // Fail on dynamic allocas. At this point, getRegForValue has already
1496 // checked its CSE maps, so if we're here trying to handle a dynamic
1497 // alloca, we're not going to succeed. X86SelectAddress has a
1498 // check for dynamic allocas, because it's called directly from
1499 // various places, but TargetMaterializeAlloca also needs a check
1500 // in order to avoid recursion between getRegForValue,
1501 // X86SelectAddrss, and TargetMaterializeAlloca.
1502 if (!StaticAllocaMap.count(C))
1506 if (!X86SelectAddress(C, AM, false))
1508 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1509 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1510 unsigned ResultReg = createResultReg(RC);
1511 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1516 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1517 MachineModuleInfo *mmi,
1519 DenseMap<const Value *, unsigned> &vm,
1520 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1521 DenseMap<const AllocaInst *, int> &am
1523 , SmallSet<Instruction*, 8> &cil
1526 return new X86FastISel(mf, mmi, dw, vm, bm, am