1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/CodeGen/FastISel.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/Support/CallSite.h"
32 #include "llvm/Support/GetElementPtrTypeIterator.h"
33 #include "llvm/Target/TargetOptions.h"
38 class X86FastISel : public FastISel {
39 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
40 /// make the right decision when generating code for different targets.
41 const X86Subtarget *Subtarget;
43 /// StackPtr - Register used as the stack pointer.
47 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
48 /// floating point ops.
49 /// When SSE is available, use it for f32 operations.
50 /// When SSE2 is available, use it for f64 operations.
55 explicit X86FastISel(MachineFunction &mf,
56 MachineModuleInfo *mmi,
58 DenseMap<const Value *, unsigned> &vm,
59 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
60 DenseMap<const AllocaInst *, int> &am
62 , SmallSet<Instruction*, 8> &cil
65 : FastISel(mf, mmi, dw, vm, bm, am
70 Subtarget = &TM.getSubtarget<X86Subtarget>();
71 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
72 X86ScalarSSEf64 = Subtarget->hasSSE2();
73 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 virtual bool TargetSelectInstruction(Instruction *I);
78 #include "X86GenFastISel.inc"
81 bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
83 bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
85 bool X86FastEmitStore(MVT VT, Value *Val,
86 const X86AddressMode &AM);
87 bool X86FastEmitStore(MVT VT, unsigned Val,
88 const X86AddressMode &AM);
90 bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
93 bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
95 bool X86SelectLoad(Instruction *I);
97 bool X86SelectStore(Instruction *I);
99 bool X86SelectCmp(Instruction *I);
101 bool X86SelectZExt(Instruction *I);
103 bool X86SelectBranch(Instruction *I);
105 bool X86SelectShift(Instruction *I);
107 bool X86SelectSelect(Instruction *I);
109 bool X86SelectTrunc(Instruction *I);
111 bool X86SelectFPExt(Instruction *I);
112 bool X86SelectFPTrunc(Instruction *I);
114 bool X86SelectExtractValue(Instruction *I);
116 bool X86VisitIntrinsicCall(IntrinsicInst &I);
117 bool X86SelectCall(Instruction *I);
119 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
121 const X86InstrInfo *getInstrInfo() const {
122 return getTargetMachine()->getInstrInfo();
124 const X86TargetMachine *getTargetMachine() const {
125 return static_cast<const X86TargetMachine *>(&TM);
128 unsigned TargetMaterializeConstant(Constant *C);
130 unsigned TargetMaterializeAlloca(AllocaInst *C);
132 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
133 /// computed in an SSE register, not on the X87 floating point stack.
134 bool isScalarFPTypeInSSEReg(MVT VT) const {
135 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
136 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
139 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
142 } // end anonymous namespace.
144 bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
145 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
146 if (VT == MVT::Other || !VT.isSimple())
147 // Unhandled type. Halt "fast" selection and bail.
150 // For now, require SSE/SSE2 for performing floating-point operations,
151 // since x87 requires additional work.
152 if (VT == MVT::f64 && !X86ScalarSSEf64)
154 if (VT == MVT::f32 && !X86ScalarSSEf32)
156 // Similarly, no f80 support yet.
159 // We only handle legal types. For example, on x86-32 the instruction
160 // selector contains all of the 64-bit instructions from x86-64,
161 // under the assumption that i64 won't be used if the target doesn't
163 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
166 #include "X86GenCallingConv.inc"
168 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
170 CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
171 if (Subtarget->is64Bit()) {
172 if (Subtarget->isTargetWin64())
173 return CC_X86_Win64_C;
178 if (CC == CallingConv::X86_FastCall)
179 return CC_X86_32_FastCall;
180 else if (CC == CallingConv::Fast)
181 return CC_X86_32_FastCC;
186 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
187 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
188 /// Return true and the result register by reference if it is possible.
189 bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
190 unsigned &ResultReg) {
191 // Get opcode and regclass of the output for the given load instruction.
193 const TargetRegisterClass *RC = NULL;
194 switch (VT.getSimpleVT()) {
195 default: return false;
198 RC = X86::GR8RegisterClass;
202 RC = X86::GR16RegisterClass;
206 RC = X86::GR32RegisterClass;
209 // Must be in x86-64 mode.
211 RC = X86::GR64RegisterClass;
214 if (Subtarget->hasSSE1()) {
216 RC = X86::FR32RegisterClass;
219 RC = X86::RFP32RegisterClass;
223 if (Subtarget->hasSSE2()) {
225 RC = X86::FR64RegisterClass;
228 RC = X86::RFP64RegisterClass;
232 // No f80 support yet.
236 ResultReg = createResultReg(RC);
237 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
241 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
242 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
243 /// and a displacement offset, or a GlobalAddress,
244 /// i.e. V. Return true if it is possible.
246 X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
247 const X86AddressMode &AM) {
248 // Get opcode and regclass of the output for the given store instruction.
250 switch (VT.getSimpleVT()) {
251 case MVT::f80: // No f80 support yet.
252 default: return false;
253 case MVT::i8: Opc = X86::MOV8mr; break;
254 case MVT::i16: Opc = X86::MOV16mr; break;
255 case MVT::i32: Opc = X86::MOV32mr; break;
256 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
258 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
261 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
265 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
269 bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val,
270 const X86AddressMode &AM) {
271 // Handle 'null' like i32/i64 0.
272 if (isa<ConstantPointerNull>(Val))
273 Val = Constant::getNullValue(TD.getIntPtrType());
275 // If this is a store of a simple constant, fold the constant into the store.
276 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
278 switch (VT.getSimpleVT()) {
280 case MVT::i8: Opc = X86::MOV8mi; break;
281 case MVT::i16: Opc = X86::MOV16mi; break;
282 case MVT::i32: Opc = X86::MOV32mi; break;
284 // Must be a 32-bit sign extended value.
285 if ((int)CI->getSExtValue() == CI->getSExtValue())
286 Opc = X86::MOV64mi32;
291 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
292 .addImm(CI->getSExtValue());
297 unsigned ValReg = getRegForValue(Val);
301 return X86FastEmitStore(VT, ValReg, AM);
304 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
305 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
306 /// ISD::SIGN_EXTEND).
307 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
308 unsigned Src, MVT SrcVT,
309 unsigned &ResultReg) {
310 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
319 /// X86SelectAddress - Attempt to fill in an address from the given value.
321 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
323 unsigned Opcode = Instruction::UserOp1;
324 if (Instruction *I = dyn_cast<Instruction>(V)) {
325 Opcode = I->getOpcode();
327 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
328 Opcode = C->getOpcode();
334 case Instruction::BitCast:
335 // Look past bitcasts.
336 return X86SelectAddress(U->getOperand(0), AM, isCall);
338 case Instruction::IntToPtr:
339 // Look past no-op inttoptrs.
340 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
341 return X86SelectAddress(U->getOperand(0), AM, isCall);
344 case Instruction::PtrToInt:
345 // Look past no-op ptrtoints.
346 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
347 return X86SelectAddress(U->getOperand(0), AM, isCall);
350 case Instruction::Alloca: {
352 // Do static allocas.
353 const AllocaInst *A = cast<AllocaInst>(V);
354 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
355 if (SI != StaticAllocaMap.end()) {
356 AM.BaseType = X86AddressMode::FrameIndexBase;
357 AM.Base.FrameIndex = SI->second;
363 case Instruction::Add: {
365 // Adds of constants are common and easy enough.
366 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
367 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
368 // They have to fit in the 32-bit signed displacement field though.
370 AM.Disp = (uint32_t)Disp;
371 return X86SelectAddress(U->getOperand(0), AM, isCall);
377 case Instruction::GetElementPtr: {
379 // Pattern-match simple GEPs.
380 uint64_t Disp = (int32_t)AM.Disp;
381 unsigned IndexReg = AM.IndexReg;
382 unsigned Scale = AM.Scale;
383 gep_type_iterator GTI = gep_type_begin(U);
384 // Iterate through the indices, folding what we can. Constants can be
385 // folded, and one dynamic index can be handled, if the scale is supported.
386 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
387 i != e; ++i, ++GTI) {
389 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
390 const StructLayout *SL = TD.getStructLayout(STy);
391 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
392 Disp += SL->getElementOffset(Idx);
394 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
395 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
396 // Constant-offset addressing.
397 Disp += CI->getSExtValue() * S;
398 } else if (IndexReg == 0 &&
400 !getTargetMachine()->symbolicAddressesAreRIPRel()) &&
401 (S == 1 || S == 2 || S == 4 || S == 8)) {
402 // Scaled-index addressing.
404 IndexReg = getRegForGEPIndex(Op);
409 goto unsupported_gep;
412 // Check for displacement overflow.
415 // Ok, the GEP indices were covered by constant-offset and scaled-index
416 // addressing. Update the address state and move on to examining the base.
417 AM.IndexReg = IndexReg;
419 AM.Disp = (uint32_t)Disp;
420 return X86SelectAddress(U->getOperand(0), AM, isCall);
422 // Ok, the GEP indices weren't all covered.
427 // Handle constant address.
428 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
429 // Can't handle alternate code models yet.
430 if (TM.getCodeModel() != CodeModel::Default &&
431 TM.getCodeModel() != CodeModel::Small)
434 // RIP-relative addresses can't have additional register operands.
435 if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
436 (AM.Base.Reg != 0 || AM.IndexReg != 0))
439 // Can't handle TLS yet.
440 if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
441 if (GVar->isThreadLocal())
444 // Set up the basic address.
447 TM.getRelocationModel() == Reloc::PIC_ &&
448 !Subtarget->is64Bit())
449 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
451 // Emit an extra load if the ABI requires it.
452 if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
453 // Check to see if we've already materialized this
454 // value in a register in this block.
455 if (unsigned Reg = LocalValueMap[V]) {
460 // Issue load from stub if necessary.
462 const TargetRegisterClass *RC = NULL;
463 if (TLI.getPointerTy() == MVT::i32) {
465 RC = X86::GR32RegisterClass;
468 RC = X86::GR64RegisterClass;
471 X86AddressMode StubAM;
472 StubAM.Base.Reg = AM.Base.Reg;
474 unsigned ResultReg = createResultReg(RC);
475 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), StubAM);
477 // Now construct the final address. Note that the Disp, Scale,
478 // and Index values may already be set here.
479 AM.Base.Reg = ResultReg;
482 // Prevent loading GV stub multiple times in same MBB.
483 LocalValueMap[V] = AM.Base.Reg;
488 // If all else fails, try to materialize the value in a register.
489 if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
490 if (AM.Base.Reg == 0) {
491 AM.Base.Reg = getRegForValue(V);
492 return AM.Base.Reg != 0;
494 if (AM.IndexReg == 0) {
495 assert(AM.Scale == 1 && "Scale with no index!");
496 AM.IndexReg = getRegForValue(V);
497 return AM.IndexReg != 0;
504 /// X86SelectStore - Select and emit code to implement store instructions.
505 bool X86FastISel::X86SelectStore(Instruction* I) {
507 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
511 if (!X86SelectAddress(I->getOperand(1), AM, false))
514 return X86FastEmitStore(VT, I->getOperand(0), AM);
517 /// X86SelectLoad - Select and emit code to implement load instructions.
519 bool X86FastISel::X86SelectLoad(Instruction *I) {
521 if (!isTypeLegal(I->getType(), VT))
525 if (!X86SelectAddress(I->getOperand(0), AM, false))
528 unsigned ResultReg = 0;
529 if (X86FastEmitLoad(VT, AM, ResultReg)) {
530 UpdateValueMap(I, ResultReg);
536 static unsigned X86ChooseCmpOpcode(MVT VT) {
537 switch (VT.getSimpleVT()) {
539 case MVT::i8: return X86::CMP8rr;
540 case MVT::i16: return X86::CMP16rr;
541 case MVT::i32: return X86::CMP32rr;
542 case MVT::i64: return X86::CMP64rr;
543 case MVT::f32: return X86::UCOMISSrr;
544 case MVT::f64: return X86::UCOMISDrr;
548 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
549 /// of the comparison, return an opcode that works for the compare (e.g.
550 /// CMP32ri) otherwise return 0.
551 static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
552 switch (VT.getSimpleVT()) {
553 // Otherwise, we can't fold the immediate into this comparison.
555 case MVT::i8: return X86::CMP8ri;
556 case MVT::i16: return X86::CMP16ri;
557 case MVT::i32: return X86::CMP32ri;
559 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
561 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
562 return X86::CMP64ri32;
567 bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
568 unsigned Op0Reg = getRegForValue(Op0);
569 if (Op0Reg == 0) return false;
571 // Handle 'null' like i32/i64 0.
572 if (isa<ConstantPointerNull>(Op1))
573 Op1 = Constant::getNullValue(TD.getIntPtrType());
575 // We have two options: compare with register or immediate. If the RHS of
576 // the compare is an immediate that we can fold into this compare, use
577 // CMPri, otherwise use CMPrr.
578 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
579 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
580 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
581 .addImm(Op1C->getSExtValue());
586 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
587 if (CompareOpc == 0) return false;
589 unsigned Op1Reg = getRegForValue(Op1);
590 if (Op1Reg == 0) return false;
591 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
596 bool X86FastISel::X86SelectCmp(Instruction *I) {
597 CmpInst *CI = cast<CmpInst>(I);
600 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
603 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
605 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
606 switch (CI->getPredicate()) {
607 case CmpInst::FCMP_OEQ: {
608 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
611 unsigned EReg = createResultReg(&X86::GR8RegClass);
612 unsigned NPReg = createResultReg(&X86::GR8RegClass);
613 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
614 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
616 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
617 UpdateValueMap(I, ResultReg);
620 case CmpInst::FCMP_UNE: {
621 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
624 unsigned NEReg = createResultReg(&X86::GR8RegClass);
625 unsigned PReg = createResultReg(&X86::GR8RegClass);
626 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
627 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
628 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
629 UpdateValueMap(I, ResultReg);
632 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
633 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
634 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
635 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
636 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
637 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
638 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
639 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
640 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
641 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
642 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
643 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
645 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
646 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
647 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
648 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
649 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
650 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
651 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
652 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
653 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
654 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
659 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
663 // Emit a compare of Op0/Op1.
664 if (!X86FastEmitCompare(Op0, Op1, VT))
667 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
668 UpdateValueMap(I, ResultReg);
672 bool X86FastISel::X86SelectZExt(Instruction *I) {
673 // Handle zero-extension from i1 to i8, which is common.
674 if (I->getType() == Type::Int8Ty &&
675 I->getOperand(0)->getType() == Type::Int1Ty) {
676 unsigned ResultReg = getRegForValue(I->getOperand(0));
677 if (ResultReg == 0) return false;
678 // Set the high bits to zero.
679 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
680 if (ResultReg == 0) return false;
681 UpdateValueMap(I, ResultReg);
689 bool X86FastISel::X86SelectBranch(Instruction *I) {
690 // Unconditional branches are selected by tablegen-generated code.
691 // Handle a conditional branch.
692 BranchInst *BI = cast<BranchInst>(I);
693 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
694 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
696 // Fold the common case of a conditional branch with a comparison.
697 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
698 if (CI->hasOneUse()) {
699 MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
701 // Try to take advantage of fallthrough opportunities.
702 CmpInst::Predicate Predicate = CI->getPredicate();
703 if (MBB->isLayoutSuccessor(TrueMBB)) {
704 std::swap(TrueMBB, FalseMBB);
705 Predicate = CmpInst::getInversePredicate(Predicate);
708 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
709 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
712 case CmpInst::FCMP_OEQ:
713 std::swap(TrueMBB, FalseMBB);
714 Predicate = CmpInst::FCMP_UNE;
716 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break;
717 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break;
718 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
719 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break;
720 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break;
721 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
722 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
723 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break;
724 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break;
725 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break;
726 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break;
727 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
728 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
730 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break;
731 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break;
732 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break;
733 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
734 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
735 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
736 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break;
737 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
738 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break;
739 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
744 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
748 // Emit a compare of the LHS and RHS, setting the flags.
749 if (!X86FastEmitCompare(Op0, Op1, VT))
752 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
754 if (Predicate == CmpInst::FCMP_UNE) {
755 // X86 requires a second branch to handle UNE (and OEQ,
756 // which is mapped to UNE above).
757 BuildMI(MBB, DL, TII.get(X86::JP)).addMBB(TrueMBB);
760 FastEmitBranch(FalseMBB);
761 MBB->addSuccessor(TrueMBB);
764 } else if (ExtractValueInst *EI =
765 dyn_cast<ExtractValueInst>(BI->getCondition())) {
766 // Check to see if the branch instruction is from an "arithmetic with
767 // overflow" intrinsic. The main way these intrinsics are used is:
769 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
770 // %sum = extractvalue { i32, i1 } %t, 0
771 // %obit = extractvalue { i32, i1 } %t, 1
772 // br i1 %obit, label %overflow, label %normal
774 // The %sum and %obit are converted in an ADD and a SETO/SETB before
775 // reaching the branch. Therefore, we search backwards through the MBB
776 // looking for the SETO/SETB instruction. If an instruction modifies the
777 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
778 // convert the branch into a JO/JB instruction.
779 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
780 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
781 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
782 const MachineInstr *SetMI = 0;
783 unsigned Reg = lookUpRegForValue(EI);
785 for (MachineBasicBlock::const_reverse_iterator
786 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
787 const MachineInstr &MI = *RI;
789 if (MI.modifiesRegister(Reg)) {
790 unsigned Src, Dst, SrcSR, DstSR;
792 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
801 const TargetInstrDesc &TID = MI.getDesc();
802 if (TID.hasUnmodeledSideEffects() ||
803 TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
808 unsigned OpCode = SetMI->getOpcode();
810 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
811 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? X86::JO : X86::JB))
813 FastEmitBranch(FalseMBB);
814 MBB->addSuccessor(TrueMBB);
822 // Otherwise do a clumsy setcc and re-test it.
823 unsigned OpReg = getRegForValue(BI->getCondition());
824 if (OpReg == 0) return false;
826 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
827 BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(TrueMBB);
828 FastEmitBranch(FalseMBB);
829 MBB->addSuccessor(TrueMBB);
833 bool X86FastISel::X86SelectShift(Instruction *I) {
834 unsigned CReg = 0, OpReg = 0, OpImm = 0;
835 const TargetRegisterClass *RC = NULL;
836 if (I->getType() == Type::Int8Ty) {
838 RC = &X86::GR8RegClass;
839 switch (I->getOpcode()) {
840 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
841 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
842 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
843 default: return false;
845 } else if (I->getType() == Type::Int16Ty) {
847 RC = &X86::GR16RegClass;
848 switch (I->getOpcode()) {
849 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
850 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
851 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
852 default: return false;
854 } else if (I->getType() == Type::Int32Ty) {
856 RC = &X86::GR32RegClass;
857 switch (I->getOpcode()) {
858 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
859 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
860 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
861 default: return false;
863 } else if (I->getType() == Type::Int64Ty) {
865 RC = &X86::GR64RegClass;
866 switch (I->getOpcode()) {
867 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
868 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
869 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
870 default: return false;
876 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
877 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
880 unsigned Op0Reg = getRegForValue(I->getOperand(0));
881 if (Op0Reg == 0) return false;
883 // Fold immediate in shl(x,3).
884 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
885 unsigned ResultReg = createResultReg(RC);
886 BuildMI(MBB, DL, TII.get(OpImm),
887 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
888 UpdateValueMap(I, ResultReg);
892 unsigned Op1Reg = getRegForValue(I->getOperand(1));
893 if (Op1Reg == 0) return false;
894 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
896 // The shift instruction uses X86::CL. If we defined a super-register
897 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
900 BuildMI(MBB, DL, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
901 .addReg(CReg).addImm(X86::SUBREG_8BIT);
903 unsigned ResultReg = createResultReg(RC);
904 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
905 UpdateValueMap(I, ResultReg);
909 bool X86FastISel::X86SelectSelect(Instruction *I) {
910 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
911 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
915 const TargetRegisterClass *RC = NULL;
916 if (VT.getSimpleVT() == MVT::i16) {
917 Opc = X86::CMOVE16rr;
918 RC = &X86::GR16RegClass;
919 } else if (VT.getSimpleVT() == MVT::i32) {
920 Opc = X86::CMOVE32rr;
921 RC = &X86::GR32RegClass;
922 } else if (VT.getSimpleVT() == MVT::i64) {
923 Opc = X86::CMOVE64rr;
924 RC = &X86::GR64RegClass;
929 unsigned Op0Reg = getRegForValue(I->getOperand(0));
930 if (Op0Reg == 0) return false;
931 unsigned Op1Reg = getRegForValue(I->getOperand(1));
932 if (Op1Reg == 0) return false;
933 unsigned Op2Reg = getRegForValue(I->getOperand(2));
934 if (Op2Reg == 0) return false;
936 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
937 unsigned ResultReg = createResultReg(RC);
938 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
939 UpdateValueMap(I, ResultReg);
943 bool X86FastISel::X86SelectFPExt(Instruction *I) {
944 // fpext from float to double.
945 if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
946 Value *V = I->getOperand(0);
947 if (V->getType() == Type::FloatTy) {
948 unsigned OpReg = getRegForValue(V);
949 if (OpReg == 0) return false;
950 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
951 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
952 UpdateValueMap(I, ResultReg);
960 bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
961 if (Subtarget->hasSSE2()) {
962 if (I->getType() == Type::FloatTy) {
963 Value *V = I->getOperand(0);
964 if (V->getType() == Type::DoubleTy) {
965 unsigned OpReg = getRegForValue(V);
966 if (OpReg == 0) return false;
967 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
968 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
969 UpdateValueMap(I, ResultReg);
978 bool X86FastISel::X86SelectTrunc(Instruction *I) {
979 if (Subtarget->is64Bit())
980 // All other cases should be handled by the tblgen generated code.
982 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
983 MVT DstVT = TLI.getValueType(I->getType());
985 // This code only handles truncation to byte right now.
986 if (DstVT != MVT::i8 && DstVT != MVT::i1)
987 // All other cases should be handled by the tblgen generated code.
989 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
990 // All other cases should be handled by the tblgen generated code.
993 unsigned InputReg = getRegForValue(I->getOperand(0));
995 // Unhandled operand. Halt "fast" selection and bail.
998 // First issue a copy to GR16_ABCD or GR32_ABCD.
999 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
1000 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1001 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1002 unsigned CopyReg = createResultReg(CopyRC);
1003 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1005 // Then issue an extract_subreg.
1006 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1007 CopyReg, X86::SUBREG_8BIT);
1011 UpdateValueMap(I, ResultReg);
1015 bool X86FastISel::X86SelectExtractValue(Instruction *I) {
1016 ExtractValueInst *EI = cast<ExtractValueInst>(I);
1017 Value *Agg = EI->getAggregateOperand();
1019 if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1020 switch (CI->getIntrinsicID()) {
1022 case Intrinsic::sadd_with_overflow:
1023 case Intrinsic::uadd_with_overflow:
1024 // Cheat a little. We know that the registers for "add" and "seto" are
1025 // allocated sequentially. However, we only keep track of the register
1026 // for "add" in the value map. Use extractvalue's index to get the
1027 // correct register for "seto".
1028 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1036 bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) {
1037 // FIXME: Handle more intrinsics.
1038 switch (I.getIntrinsicID()) {
1039 default: return false;
1040 case Intrinsic::sadd_with_overflow:
1041 case Intrinsic::uadd_with_overflow: {
1042 // Replace "add with overflow" intrinsics with an "add" instruction followed
1043 // by a seto/setc instruction. Later on, when the "extractvalue"
1044 // instructions are encountered, we use the fact that two registers were
1045 // created sequentially to get the correct registers for the "sum" and the
1047 const Function *Callee = I.getCalledFunction();
1049 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1052 if (!isTypeLegal(RetTy, VT))
1055 Value *Op1 = I.getOperand(1);
1056 Value *Op2 = I.getOperand(2);
1057 unsigned Reg1 = getRegForValue(Op1);
1058 unsigned Reg2 = getRegForValue(Op2);
1060 if (Reg1 == 0 || Reg2 == 0)
1061 // FIXME: Handle values *not* in registers.
1067 else if (VT == MVT::i64)
1072 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1073 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1074 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1076 // If the add with overflow is an intra-block value then we just want to
1077 // create temporaries for it like normal. If it is a cross-block value then
1078 // UpdateValueMap will return the cross-block register used. Since we
1079 // *really* want the value to be live in the register pair known by
1080 // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1081 // the cross block case. In the non-cross-block case, we should just make
1082 // another register for the value.
1083 if (DestReg1 != ResultReg)
1084 ResultReg = DestReg1+1;
1086 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1088 unsigned Opc = X86::SETBr;
1089 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1091 BuildMI(MBB, DL, TII.get(Opc), ResultReg);
1097 bool X86FastISel::X86SelectCall(Instruction *I) {
1098 CallInst *CI = cast<CallInst>(I);
1099 Value *Callee = I->getOperand(0);
1101 // Can't handle inline asm yet.
1102 if (isa<InlineAsm>(Callee))
1105 // Handle intrinsic calls.
1106 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1107 return X86VisitIntrinsicCall(*II);
1109 // Handle only C and fastcc calling conventions for now.
1111 unsigned CC = CS.getCallingConv();
1112 if (CC != CallingConv::C &&
1113 CC != CallingConv::Fast &&
1114 CC != CallingConv::X86_FastCall)
1117 // On X86, -tailcallopt changes the fastcc ABI. FastISel doesn't
1118 // handle this for now.
1119 if (CC == CallingConv::Fast && PerformTailCallOpt)
1122 // Let SDISel handle vararg functions.
1123 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1124 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1125 if (FTy->isVarArg())
1128 // Handle *simple* calls for now.
1129 const Type *RetTy = CS.getType();
1131 if (RetTy == Type::VoidTy)
1132 RetVT = MVT::isVoid;
1133 else if (!isTypeLegal(RetTy, RetVT, true))
1136 // Materialize callee address in a register. FIXME: GV address can be
1137 // handled with a CALLpcrel32 instead.
1138 X86AddressMode CalleeAM;
1139 if (!X86SelectAddress(Callee, CalleeAM, true))
1141 unsigned CalleeOp = 0;
1142 GlobalValue *GV = 0;
1143 if (CalleeAM.Base.Reg != 0) {
1144 assert(CalleeAM.GV == 0);
1145 CalleeOp = CalleeAM.Base.Reg;
1146 } else if (CalleeAM.GV != 0) {
1147 assert(CalleeAM.GV != 0);
1152 // Allow calls which produce i1 results.
1153 bool AndToI1 = false;
1154 if (RetVT == MVT::i1) {
1159 // Deal with call operands first.
1160 SmallVector<Value*, 8> ArgVals;
1161 SmallVector<unsigned, 8> Args;
1162 SmallVector<MVT, 8> ArgVTs;
1163 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1164 Args.reserve(CS.arg_size());
1165 ArgVals.reserve(CS.arg_size());
1166 ArgVTs.reserve(CS.arg_size());
1167 ArgFlags.reserve(CS.arg_size());
1168 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1170 unsigned Arg = getRegForValue(*i);
1173 ISD::ArgFlagsTy Flags;
1174 unsigned AttrInd = i - CS.arg_begin() + 1;
1175 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1177 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1180 // FIXME: Only handle *easy* calls for now.
1181 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1182 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1183 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1184 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1187 const Type *ArgTy = (*i)->getType();
1189 if (!isTypeLegal(ArgTy, ArgVT))
1191 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1192 Flags.setOrigAlign(OriginalAlignment);
1194 Args.push_back(Arg);
1195 ArgVals.push_back(*i);
1196 ArgVTs.push_back(ArgVT);
1197 ArgFlags.push_back(Flags);
1200 // Analyze operands of the call, assigning locations to each operand.
1201 SmallVector<CCValAssign, 16> ArgLocs;
1202 CCState CCInfo(CC, false, TM, ArgLocs);
1203 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1205 // Get a count of how many bytes are to be pushed on the stack.
1206 unsigned NumBytes = CCInfo.getNextStackOffset();
1208 // Issue CALLSEQ_START
1209 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1210 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1212 // Process argument: walk the register/memloc assignments, inserting
1214 SmallVector<unsigned, 4> RegArgs;
1215 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1216 CCValAssign &VA = ArgLocs[i];
1217 unsigned Arg = Args[VA.getValNo()];
1218 MVT ArgVT = ArgVTs[VA.getValNo()];
1220 // Promote the value if needed.
1221 switch (VA.getLocInfo()) {
1222 default: assert(0 && "Unknown loc info!");
1223 case CCValAssign::Full: break;
1224 case CCValAssign::SExt: {
1225 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1227 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1229 ArgVT = VA.getLocVT();
1232 case CCValAssign::ZExt: {
1233 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1235 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1237 ArgVT = VA.getLocVT();
1240 case CCValAssign::AExt: {
1241 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1244 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1247 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1250 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1251 ArgVT = VA.getLocVT();
1256 if (VA.isRegLoc()) {
1257 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1258 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1260 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1262 RegArgs.push_back(VA.getLocReg());
1264 unsigned LocMemOffset = VA.getLocMemOffset();
1266 AM.Base.Reg = StackPtr;
1267 AM.Disp = LocMemOffset;
1268 Value *ArgVal = ArgVals[VA.getValNo()];
1270 // If this is a really simple value, emit this with the Value* version of
1271 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1272 // can cause us to reevaluate the argument.
1273 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1274 X86FastEmitStore(ArgVT, ArgVal, AM);
1276 X86FastEmitStore(ArgVT, Arg, AM);
1280 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1282 if (!Subtarget->is64Bit() &&
1283 TM.getRelocationModel() == Reloc::PIC_ &&
1284 Subtarget->isPICStyleGOT()) {
1285 TargetRegisterClass *RC = X86::GR32RegisterClass;
1286 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1287 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1288 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1293 unsigned CallOpc = CalleeOp
1294 ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
1295 : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
1296 MachineInstrBuilder MIB = CalleeOp
1297 ? BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp)
1298 : BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV);
1300 // Add an implicit use GOT pointer in EBX.
1301 if (!Subtarget->is64Bit() &&
1302 TM.getRelocationModel() == Reloc::PIC_ &&
1303 Subtarget->isPICStyleGOT())
1304 MIB.addReg(X86::EBX);
1306 // Add implicit physical register uses to the call.
1307 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1308 MIB.addReg(RegArgs[i]);
1310 // Issue CALLSEQ_END
1311 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1312 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1314 // Now handle call return value (if any).
1315 if (RetVT.getSimpleVT() != MVT::isVoid) {
1316 SmallVector<CCValAssign, 16> RVLocs;
1317 CCState CCInfo(CC, false, TM, RVLocs);
1318 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1320 // Copy all of the result registers out of their specified physreg.
1321 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1322 MVT CopyVT = RVLocs[0].getValVT();
1323 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1324 TargetRegisterClass *SrcRC = DstRC;
1326 // If this is a call to a function that returns an fp value on the x87 fp
1327 // stack, but where we prefer to use the value in xmm registers, copy it
1328 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1329 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1330 RVLocs[0].getLocReg() == X86::ST1) &&
1331 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1333 SrcRC = X86::RSTRegisterClass;
1334 DstRC = X86::RFP80RegisterClass;
1337 unsigned ResultReg = createResultReg(DstRC);
1338 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1339 RVLocs[0].getLocReg(), DstRC, SrcRC);
1340 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1342 if (CopyVT != RVLocs[0].getValVT()) {
1343 // Round the F80 the right size, which also moves to the appropriate xmm
1344 // register. This is accomplished by storing the F80 value in memory and
1345 // then loading it back. Ewww...
1346 MVT ResVT = RVLocs[0].getValVT();
1347 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1348 unsigned MemSize = ResVT.getSizeInBits()/8;
1349 int FI = MFI.CreateStackObject(MemSize, MemSize);
1350 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1351 DstRC = ResVT == MVT::f32
1352 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1353 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1354 ResultReg = createResultReg(DstRC);
1355 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1359 // Mask out all but lowest bit for some call which produces an i1.
1360 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1362 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1363 ResultReg = AndResult;
1366 UpdateValueMap(I, ResultReg);
1374 X86FastISel::TargetSelectInstruction(Instruction *I) {
1375 switch (I->getOpcode()) {
1377 case Instruction::Load:
1378 return X86SelectLoad(I);
1379 case Instruction::Store:
1380 return X86SelectStore(I);
1381 case Instruction::ICmp:
1382 case Instruction::FCmp:
1383 return X86SelectCmp(I);
1384 case Instruction::ZExt:
1385 return X86SelectZExt(I);
1386 case Instruction::Br:
1387 return X86SelectBranch(I);
1388 case Instruction::Call:
1389 return X86SelectCall(I);
1390 case Instruction::LShr:
1391 case Instruction::AShr:
1392 case Instruction::Shl:
1393 return X86SelectShift(I);
1394 case Instruction::Select:
1395 return X86SelectSelect(I);
1396 case Instruction::Trunc:
1397 return X86SelectTrunc(I);
1398 case Instruction::FPExt:
1399 return X86SelectFPExt(I);
1400 case Instruction::FPTrunc:
1401 return X86SelectFPTrunc(I);
1402 case Instruction::ExtractValue:
1403 return X86SelectExtractValue(I);
1404 case Instruction::IntToPtr: // Deliberate fall-through.
1405 case Instruction::PtrToInt: {
1406 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1407 MVT DstVT = TLI.getValueType(I->getType());
1408 if (DstVT.bitsGT(SrcVT))
1409 return X86SelectZExt(I);
1410 if (DstVT.bitsLT(SrcVT))
1411 return X86SelectTrunc(I);
1412 unsigned Reg = getRegForValue(I->getOperand(0));
1413 if (Reg == 0) return false;
1414 UpdateValueMap(I, Reg);
1422 unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
1424 if (!isTypeLegal(C->getType(), VT))
1427 // Get opcode and regclass of the output for the given load instruction.
1429 const TargetRegisterClass *RC = NULL;
1430 switch (VT.getSimpleVT()) {
1431 default: return false;
1434 RC = X86::GR8RegisterClass;
1438 RC = X86::GR16RegisterClass;
1442 RC = X86::GR32RegisterClass;
1445 // Must be in x86-64 mode.
1447 RC = X86::GR64RegisterClass;
1450 if (Subtarget->hasSSE1()) {
1452 RC = X86::FR32RegisterClass;
1454 Opc = X86::LD_Fp32m;
1455 RC = X86::RFP32RegisterClass;
1459 if (Subtarget->hasSSE2()) {
1461 RC = X86::FR64RegisterClass;
1463 Opc = X86::LD_Fp64m;
1464 RC = X86::RFP64RegisterClass;
1468 // No f80 support yet.
1472 // Materialize addresses with LEA instructions.
1473 if (isa<GlobalValue>(C)) {
1475 if (X86SelectAddress(C, AM, false)) {
1476 if (TLI.getPointerTy() == MVT::i32)
1480 unsigned ResultReg = createResultReg(RC);
1481 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1487 // MachineConstantPool wants an explicit alignment.
1488 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1490 // Alignment of vector types. FIXME!
1491 Align = TD.getTypeAllocSize(C->getType());
1494 // x86-32 PIC requires a PIC base register for constant pools.
1495 unsigned PICBase = 0;
1496 if (TM.getRelocationModel() == Reloc::PIC_ &&
1497 !Subtarget->is64Bit())
1498 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1500 // Create the load from the constant pool.
1501 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1502 unsigned ResultReg = createResultReg(RC);
1503 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), MCPOffset,
1509 unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
1510 // Fail on dynamic allocas. At this point, getRegForValue has already
1511 // checked its CSE maps, so if we're here trying to handle a dynamic
1512 // alloca, we're not going to succeed. X86SelectAddress has a
1513 // check for dynamic allocas, because it's called directly from
1514 // various places, but TargetMaterializeAlloca also needs a check
1515 // in order to avoid recursion between getRegForValue,
1516 // X86SelectAddrss, and TargetMaterializeAlloca.
1517 if (!StaticAllocaMap.count(C))
1521 if (!X86SelectAddress(C, AM, false))
1523 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1524 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1525 unsigned ResultReg = createResultReg(RC);
1526 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1531 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1532 MachineModuleInfo *mmi,
1534 DenseMap<const Value *, unsigned> &vm,
1535 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1536 DenseMap<const AllocaInst *, int> &am
1538 , SmallSet<Instruction*, 8> &cil
1541 return new X86FastISel(mf, mmi, dw, vm, bm, am