1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/Support/CallSite.h"
31 #include "llvm/Support/GetElementPtrTypeIterator.h"
35 class X86FastISel : public FastISel {
36 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
37 /// make the right decision when generating code for different targets.
38 const X86Subtarget *Subtarget;
40 /// StackPtr - Register used as the stack pointer.
44 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
45 /// floating point ops.
46 /// When SSE is available, use it for f32 operations.
47 /// When SSE2 is available, use it for f64 operations.
52 explicit X86FastISel(MachineFunction &mf,
53 MachineModuleInfo *mmi,
54 DenseMap<const Value *, unsigned> &vm,
55 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
56 DenseMap<const AllocaInst *, int> &am
58 , SmallSet<Instruction*, 8> &cil
61 : FastISel(mf, mmi, vm, bm, am
66 Subtarget = &TM.getSubtarget<X86Subtarget>();
67 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
68 X86ScalarSSEf64 = Subtarget->hasSSE2();
69 X86ScalarSSEf32 = Subtarget->hasSSE1();
72 virtual bool TargetSelectInstruction(Instruction *I);
74 #include "X86GenFastISel.inc"
77 bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
79 bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
81 bool X86FastEmitStore(MVT VT, Value *Val,
82 const X86AddressMode &AM);
83 bool X86FastEmitStore(MVT VT, unsigned Val,
84 const X86AddressMode &AM);
86 bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
89 bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
91 bool X86SelectLoad(Instruction *I);
93 bool X86SelectStore(Instruction *I);
95 bool X86SelectCmp(Instruction *I);
97 bool X86SelectZExt(Instruction *I);
99 bool X86SelectBranch(Instruction *I);
101 bool X86SelectShift(Instruction *I);
103 bool X86SelectSelect(Instruction *I);
105 bool X86SelectTrunc(Instruction *I);
107 bool X86SelectFPExt(Instruction *I);
108 bool X86SelectFPTrunc(Instruction *I);
110 bool X86SelectExtractValue(Instruction *I);
112 bool X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic);
113 bool X86SelectCall(Instruction *I);
115 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
117 const X86InstrInfo *getInstrInfo() const {
118 return getTargetMachine()->getInstrInfo();
120 const X86TargetMachine *getTargetMachine() const {
121 return static_cast<const X86TargetMachine *>(&TM);
124 unsigned TargetMaterializeConstant(Constant *C);
126 unsigned TargetMaterializeAlloca(AllocaInst *C);
128 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
129 /// computed in an SSE register, not on the X87 floating point stack.
130 bool isScalarFPTypeInSSEReg(MVT VT) const {
131 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
132 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
135 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
138 bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
139 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
140 if (VT == MVT::Other || !VT.isSimple())
141 // Unhandled type. Halt "fast" selection and bail.
144 // For now, require SSE/SSE2 for performing floating-point operations,
145 // since x87 requires additional work.
146 if (VT == MVT::f64 && !X86ScalarSSEf64)
148 if (VT == MVT::f32 && !X86ScalarSSEf32)
150 // Similarly, no f80 support yet.
153 // We only handle legal types. For example, on x86-32 the instruction
154 // selector contains all of the 64-bit instructions from x86-64,
155 // under the assumption that i64 won't be used if the target doesn't
157 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
160 #include "X86GenCallingConv.inc"
162 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
164 CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
165 if (Subtarget->is64Bit()) {
166 if (Subtarget->isTargetWin64())
167 return CC_X86_Win64_C;
168 else if (CC == CallingConv::Fast && isTaillCall)
169 return CC_X86_64_TailCall;
174 if (CC == CallingConv::X86_FastCall)
175 return CC_X86_32_FastCall;
176 else if (CC == CallingConv::Fast)
177 return CC_X86_32_FastCC;
182 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
183 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
184 /// Return true and the result register by reference if it is possible.
185 bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
186 unsigned &ResultReg) {
187 // Get opcode and regclass of the output for the given load instruction.
189 const TargetRegisterClass *RC = NULL;
190 switch (VT.getSimpleVT()) {
191 default: return false;
194 RC = X86::GR8RegisterClass;
198 RC = X86::GR16RegisterClass;
202 RC = X86::GR32RegisterClass;
205 // Must be in x86-64 mode.
207 RC = X86::GR64RegisterClass;
210 if (Subtarget->hasSSE1()) {
212 RC = X86::FR32RegisterClass;
215 RC = X86::RFP32RegisterClass;
219 if (Subtarget->hasSSE2()) {
221 RC = X86::FR64RegisterClass;
224 RC = X86::RFP64RegisterClass;
228 // No f80 support yet.
232 ResultReg = createResultReg(RC);
233 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
237 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
238 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
239 /// and a displacement offset, or a GlobalAddress,
240 /// i.e. V. Return true if it is possible.
242 X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
243 const X86AddressMode &AM) {
244 // Get opcode and regclass of the output for the given store instruction.
246 switch (VT.getSimpleVT()) {
247 case MVT::f80: // No f80 support yet.
248 default: return false;
249 case MVT::i8: Opc = X86::MOV8mr; break;
250 case MVT::i16: Opc = X86::MOV16mr; break;
251 case MVT::i32: Opc = X86::MOV32mr; break;
252 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
254 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
257 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
261 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Val);
265 bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val,
266 const X86AddressMode &AM) {
267 // Handle 'null' like i32/i64 0.
268 if (isa<ConstantPointerNull>(Val))
269 Val = Constant::getNullValue(TD.getIntPtrType());
271 // If this is a store of a simple constant, fold the constant into the store.
272 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
274 switch (VT.getSimpleVT()) {
276 case MVT::i8: Opc = X86::MOV8mi; break;
277 case MVT::i16: Opc = X86::MOV16mi; break;
278 case MVT::i32: Opc = X86::MOV32mi; break;
280 // Must be a 32-bit sign extended value.
281 if ((int)CI->getSExtValue() == CI->getSExtValue())
282 Opc = X86::MOV64mi32;
287 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addImm(CI->getSExtValue());
292 unsigned ValReg = getRegForValue(Val);
296 return X86FastEmitStore(VT, ValReg, AM);
299 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
300 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
301 /// ISD::SIGN_EXTEND).
302 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
303 unsigned Src, MVT SrcVT,
304 unsigned &ResultReg) {
305 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
314 /// X86SelectAddress - Attempt to fill in an address from the given value.
316 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
318 unsigned Opcode = Instruction::UserOp1;
319 if (Instruction *I = dyn_cast<Instruction>(V)) {
320 Opcode = I->getOpcode();
322 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
323 Opcode = C->getOpcode();
329 case Instruction::BitCast:
330 // Look past bitcasts.
331 return X86SelectAddress(U->getOperand(0), AM, isCall);
333 case Instruction::IntToPtr:
334 // Look past no-op inttoptrs.
335 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
336 return X86SelectAddress(U->getOperand(0), AM, isCall);
339 case Instruction::PtrToInt:
340 // Look past no-op ptrtoints.
341 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
342 return X86SelectAddress(U->getOperand(0), AM, isCall);
345 case Instruction::Alloca: {
347 // Do static allocas.
348 const AllocaInst *A = cast<AllocaInst>(V);
349 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
350 if (SI != StaticAllocaMap.end()) {
351 AM.BaseType = X86AddressMode::FrameIndexBase;
352 AM.Base.FrameIndex = SI->second;
358 case Instruction::Add: {
360 // Adds of constants are common and easy enough.
361 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
362 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
363 // They have to fit in the 32-bit signed displacement field though.
365 AM.Disp = (uint32_t)Disp;
366 return X86SelectAddress(U->getOperand(0), AM, isCall);
372 case Instruction::GetElementPtr: {
374 // Pattern-match simple GEPs.
375 uint64_t Disp = (int32_t)AM.Disp;
376 unsigned IndexReg = AM.IndexReg;
377 unsigned Scale = AM.Scale;
378 gep_type_iterator GTI = gep_type_begin(U);
379 // Iterate through the indices, folding what we can. Constants can be
380 // folded, and one dynamic index can be handled, if the scale is supported.
381 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
382 i != e; ++i, ++GTI) {
384 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
385 const StructLayout *SL = TD.getStructLayout(STy);
386 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
387 Disp += SL->getElementOffset(Idx);
389 uint64_t S = TD.getABITypeSize(GTI.getIndexedType());
390 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
391 // Constant-offset addressing.
392 Disp += CI->getSExtValue() * S;
393 } else if (IndexReg == 0 &&
395 !getTargetMachine()->symbolicAddressesAreRIPRel()) &&
396 (S == 1 || S == 2 || S == 4 || S == 8)) {
397 // Scaled-index addressing.
399 IndexReg = getRegForGEPIndex(Op);
404 goto unsupported_gep;
407 // Check for displacement overflow.
410 // Ok, the GEP indices were covered by constant-offset and scaled-index
411 // addressing. Update the address state and move on to examining the base.
412 AM.IndexReg = IndexReg;
414 AM.Disp = (uint32_t)Disp;
415 return X86SelectAddress(U->getOperand(0), AM, isCall);
417 // Ok, the GEP indices weren't all covered.
422 // Handle constant address.
423 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
424 // Can't handle alternate code models yet.
425 if (TM.getCodeModel() != CodeModel::Default &&
426 TM.getCodeModel() != CodeModel::Small)
429 // RIP-relative addresses can't have additional register operands.
430 if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
431 (AM.Base.Reg != 0 || AM.IndexReg != 0))
434 // Set up the basic address.
437 TM.getRelocationModel() == Reloc::PIC_ &&
438 !Subtarget->is64Bit())
439 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
441 // Emit an extra load if the ABI requires it.
442 if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
443 // Check to see if we've already materialized this
444 // value in a register in this block.
445 if (unsigned Reg = LocalValueMap[V]) {
450 // Issue load from stub if necessary.
452 const TargetRegisterClass *RC = NULL;
453 if (TLI.getPointerTy() == MVT::i32) {
455 RC = X86::GR32RegisterClass;
458 RC = X86::GR64RegisterClass;
461 X86AddressMode StubAM;
462 StubAM.Base.Reg = AM.Base.Reg;
464 unsigned ResultReg = createResultReg(RC);
465 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), StubAM);
467 // Now construct the final address. Note that the Disp, Scale,
468 // and Index values may already be set here.
469 AM.Base.Reg = ResultReg;
472 // Prevent loading GV stub multiple times in same MBB.
473 LocalValueMap[V] = AM.Base.Reg;
478 // If all else fails, try to materialize the value in a register.
479 if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
480 if (AM.Base.Reg == 0) {
481 AM.Base.Reg = getRegForValue(V);
482 return AM.Base.Reg != 0;
484 if (AM.IndexReg == 0) {
485 assert(AM.Scale == 1 && "Scale with no index!");
486 AM.IndexReg = getRegForValue(V);
487 return AM.IndexReg != 0;
494 /// X86SelectStore - Select and emit code to implement store instructions.
495 bool X86FastISel::X86SelectStore(Instruction* I) {
497 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
501 if (!X86SelectAddress(I->getOperand(1), AM, false))
504 return X86FastEmitStore(VT, I->getOperand(0), AM);
507 /// X86SelectLoad - Select and emit code to implement load instructions.
509 bool X86FastISel::X86SelectLoad(Instruction *I) {
511 if (!isTypeLegal(I->getType(), VT))
515 if (!X86SelectAddress(I->getOperand(0), AM, false))
518 unsigned ResultReg = 0;
519 if (X86FastEmitLoad(VT, AM, ResultReg)) {
520 UpdateValueMap(I, ResultReg);
526 static unsigned X86ChooseCmpOpcode(MVT VT) {
527 switch (VT.getSimpleVT()) {
529 case MVT::i8: return X86::CMP8rr;
530 case MVT::i16: return X86::CMP16rr;
531 case MVT::i32: return X86::CMP32rr;
532 case MVT::i64: return X86::CMP64rr;
533 case MVT::f32: return X86::UCOMISSrr;
534 case MVT::f64: return X86::UCOMISDrr;
538 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
539 /// of the comparison, return an opcode that works for the compare (e.g.
540 /// CMP32ri) otherwise return 0.
541 static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
542 switch (VT.getSimpleVT()) {
543 // Otherwise, we can't fold the immediate into this comparison.
545 case MVT::i8: return X86::CMP8ri;
546 case MVT::i16: return X86::CMP16ri;
547 case MVT::i32: return X86::CMP32ri;
549 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
551 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
552 return X86::CMP64ri32;
557 bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
558 unsigned Op0Reg = getRegForValue(Op0);
559 if (Op0Reg == 0) return false;
561 // Handle 'null' like i32/i64 0.
562 if (isa<ConstantPointerNull>(Op1))
563 Op1 = Constant::getNullValue(TD.getIntPtrType());
565 // We have two options: compare with register or immediate. If the RHS of
566 // the compare is an immediate that we can fold into this compare, use
567 // CMPri, otherwise use CMPrr.
568 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
569 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
570 BuildMI(MBB, TII.get(CompareImmOpc)).addReg(Op0Reg)
571 .addImm(Op1C->getSExtValue());
576 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
577 if (CompareOpc == 0) return false;
579 unsigned Op1Reg = getRegForValue(Op1);
580 if (Op1Reg == 0) return false;
581 BuildMI(MBB, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
586 bool X86FastISel::X86SelectCmp(Instruction *I) {
587 CmpInst *CI = cast<CmpInst>(I);
590 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
593 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
595 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
596 switch (CI->getPredicate()) {
597 case CmpInst::FCMP_OEQ: {
598 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
601 unsigned EReg = createResultReg(&X86::GR8RegClass);
602 unsigned NPReg = createResultReg(&X86::GR8RegClass);
603 BuildMI(MBB, TII.get(X86::SETEr), EReg);
604 BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
605 BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
606 UpdateValueMap(I, ResultReg);
609 case CmpInst::FCMP_UNE: {
610 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
613 unsigned NEReg = createResultReg(&X86::GR8RegClass);
614 unsigned PReg = createResultReg(&X86::GR8RegClass);
615 BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
616 BuildMI(MBB, TII.get(X86::SETPr), PReg);
617 BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
618 UpdateValueMap(I, ResultReg);
621 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
622 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
623 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
624 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
625 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
626 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
627 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
628 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
629 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
630 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
631 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
632 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
634 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
635 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
636 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
637 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
638 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
639 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
640 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
641 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
642 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
643 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
648 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
652 // Emit a compare of Op0/Op1.
653 if (!X86FastEmitCompare(Op0, Op1, VT))
656 BuildMI(MBB, TII.get(SetCCOpc), ResultReg);
657 UpdateValueMap(I, ResultReg);
661 bool X86FastISel::X86SelectZExt(Instruction *I) {
662 // Special-case hack: The only i1 values we know how to produce currently
663 // set the upper bits of an i8 value to zero.
664 if (I->getType() == Type::Int8Ty &&
665 I->getOperand(0)->getType() == Type::Int1Ty) {
666 unsigned ResultReg = getRegForValue(I->getOperand(0));
667 if (ResultReg == 0) return false;
668 UpdateValueMap(I, ResultReg);
676 bool X86FastISel::X86SelectBranch(Instruction *I) {
677 // Unconditional branches are selected by tablegen-generated code.
678 // Handle a conditional branch.
679 BranchInst *BI = cast<BranchInst>(I);
680 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
681 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
683 // Fold the common case of a conditional branch with a comparison.
684 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
685 if (CI->hasOneUse()) {
686 MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
688 // Try to take advantage of fallthrough opportunities.
689 CmpInst::Predicate Predicate = CI->getPredicate();
690 if (MBB->isLayoutSuccessor(TrueMBB)) {
691 std::swap(TrueMBB, FalseMBB);
692 Predicate = CmpInst::getInversePredicate(Predicate);
695 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
696 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
699 case CmpInst::FCMP_OEQ:
700 std::swap(TrueMBB, FalseMBB);
701 Predicate = CmpInst::FCMP_UNE;
703 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break;
704 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break;
705 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
706 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break;
707 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break;
708 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
709 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
710 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break;
711 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break;
712 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break;
713 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break;
714 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
715 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
717 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break;
718 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break;
719 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break;
720 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
721 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
722 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
723 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break;
724 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
725 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break;
726 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
731 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
735 // Emit a compare of the LHS and RHS, setting the flags.
736 if (!X86FastEmitCompare(Op0, Op1, VT))
739 BuildMI(MBB, TII.get(BranchOpc)).addMBB(TrueMBB);
741 if (Predicate == CmpInst::FCMP_UNE) {
742 // X86 requires a second branch to handle UNE (and OEQ,
743 // which is mapped to UNE above).
744 BuildMI(MBB, TII.get(X86::JP)).addMBB(TrueMBB);
747 FastEmitBranch(FalseMBB);
748 MBB->addSuccessor(TrueMBB);
753 // Otherwise do a clumsy setcc and re-test it.
754 unsigned OpReg = getRegForValue(BI->getCondition());
755 if (OpReg == 0) return false;
757 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
758 BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
759 FastEmitBranch(FalseMBB);
760 MBB->addSuccessor(TrueMBB);
764 bool X86FastISel::X86SelectShift(Instruction *I) {
765 unsigned CReg = 0, OpReg = 0, OpImm = 0;
766 const TargetRegisterClass *RC = NULL;
767 if (I->getType() == Type::Int8Ty) {
769 RC = &X86::GR8RegClass;
770 switch (I->getOpcode()) {
771 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
772 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
773 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
774 default: return false;
776 } else if (I->getType() == Type::Int16Ty) {
778 RC = &X86::GR16RegClass;
779 switch (I->getOpcode()) {
780 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
781 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
782 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
783 default: return false;
785 } else if (I->getType() == Type::Int32Ty) {
787 RC = &X86::GR32RegClass;
788 switch (I->getOpcode()) {
789 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
790 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
791 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
792 default: return false;
794 } else if (I->getType() == Type::Int64Ty) {
796 RC = &X86::GR64RegClass;
797 switch (I->getOpcode()) {
798 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
799 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
800 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
801 default: return false;
807 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
808 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
811 unsigned Op0Reg = getRegForValue(I->getOperand(0));
812 if (Op0Reg == 0) return false;
814 // Fold immediate in shl(x,3).
815 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
816 unsigned ResultReg = createResultReg(RC);
817 BuildMI(MBB, TII.get(OpImm),
818 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue());
819 UpdateValueMap(I, ResultReg);
823 unsigned Op1Reg = getRegForValue(I->getOperand(1));
824 if (Op1Reg == 0) return false;
825 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
827 // The shift instruction uses X86::CL. If we defined a super-register
828 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
831 BuildMI(MBB, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
832 .addReg(CReg).addImm(X86::SUBREG_8BIT);
834 unsigned ResultReg = createResultReg(RC);
835 BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg);
836 UpdateValueMap(I, ResultReg);
840 bool X86FastISel::X86SelectSelect(Instruction *I) {
841 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
842 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
846 const TargetRegisterClass *RC = NULL;
847 if (VT.getSimpleVT() == MVT::i16) {
848 Opc = X86::CMOVE16rr;
849 RC = &X86::GR16RegClass;
850 } else if (VT.getSimpleVT() == MVT::i32) {
851 Opc = X86::CMOVE32rr;
852 RC = &X86::GR32RegClass;
853 } else if (VT.getSimpleVT() == MVT::i64) {
854 Opc = X86::CMOVE64rr;
855 RC = &X86::GR64RegClass;
860 unsigned Op0Reg = getRegForValue(I->getOperand(0));
861 if (Op0Reg == 0) return false;
862 unsigned Op1Reg = getRegForValue(I->getOperand(1));
863 if (Op1Reg == 0) return false;
864 unsigned Op2Reg = getRegForValue(I->getOperand(2));
865 if (Op2Reg == 0) return false;
867 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
868 unsigned ResultReg = createResultReg(RC);
869 BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
870 UpdateValueMap(I, ResultReg);
874 bool X86FastISel::X86SelectFPExt(Instruction *I) {
875 // fpext from float to double.
876 if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
877 Value *V = I->getOperand(0);
878 if (V->getType() == Type::FloatTy) {
879 unsigned OpReg = getRegForValue(V);
880 if (OpReg == 0) return false;
881 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
882 BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
883 UpdateValueMap(I, ResultReg);
891 bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
892 if (Subtarget->hasSSE2()) {
893 if (I->getType() == Type::FloatTy) {
894 Value *V = I->getOperand(0);
895 if (V->getType() == Type::DoubleTy) {
896 unsigned OpReg = getRegForValue(V);
897 if (OpReg == 0) return false;
898 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
899 BuildMI(MBB, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
900 UpdateValueMap(I, ResultReg);
909 bool X86FastISel::X86SelectTrunc(Instruction *I) {
910 if (Subtarget->is64Bit())
911 // All other cases should be handled by the tblgen generated code.
913 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
914 MVT DstVT = TLI.getValueType(I->getType());
915 if (DstVT != MVT::i8)
916 // All other cases should be handled by the tblgen generated code.
918 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
919 // All other cases should be handled by the tblgen generated code.
922 unsigned InputReg = getRegForValue(I->getOperand(0));
924 // Unhandled operand. Halt "fast" selection and bail.
927 // First issue a copy to GR16_ or GR32_.
928 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16to16_ : X86::MOV32to32_;
929 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
930 ? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
931 unsigned CopyReg = createResultReg(CopyRC);
932 BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
934 // Then issue an extract_subreg.
935 unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg, X86::SUBREG_8BIT);
939 UpdateValueMap(I, ResultReg);
943 bool X86FastISel::X86SelectExtractValue(Instruction *I) {
944 ExtractValueInst *EI = cast<ExtractValueInst>(I);
945 Value *Agg = EI->getAggregateOperand();
947 if (CallInst *CI = dyn_cast<CallInst>(Agg)) {
948 Function *F = CI->getCalledFunction();
950 if (F && F->isDeclaration()) {
951 switch (F->getIntrinsicID()) {
953 case Intrinsic::sadd_with_overflow:
954 case Intrinsic::uadd_with_overflow:
955 // Cheat a little. We know that the registers for "add" and "seto" are
956 // allocated sequentially. However, we only keep track of the register
957 // for "add" in the value map. Use extractvalue's index to get the
958 // correct register for "seto".
959 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
968 bool X86FastISel::X86VisitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
969 // FIXME: Handle more intrinsics.
971 default: return false;
972 case Intrinsic::sadd_with_overflow:
973 case Intrinsic::uadd_with_overflow: {
974 // Replace "add with overflow" intrinsics with an "add" instruction followed
975 // by a seto/setc instruction. Later on, when the "extractvalue"
976 // instructions are encountered, we use the fact that two registers were
977 // created sequentially to get the correct registers for the "sum" and the
980 const Function *Callee = I.getCalledFunction();
982 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
984 if (!isTypeLegal(RetTy, VT))
987 Value *Op1 = I.getOperand(1);
988 Value *Op2 = I.getOperand(2);
989 unsigned Reg1 = getRegForValue(Op1);
990 unsigned Reg2 = getRegForValue(Op2);
992 if (Reg1 == 0 || Reg2 == 0)
993 // FIXME: Handle values *not* in registers.
1000 else if (VT == MVT::i64)
1005 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1006 BuildMI(MBB, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1007 UpdateValueMap(&I, ResultReg);
1009 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1010 BuildMI(MBB, TII.get((Intrinsic == Intrinsic::sadd_with_overflow) ?
1011 X86::SETOr : X86::SETCr), ResultReg);
1017 bool X86FastISel::X86SelectCall(Instruction *I) {
1018 CallInst *CI = cast<CallInst>(I);
1019 Value *Callee = I->getOperand(0);
1021 // Can't handle inline asm yet.
1022 if (isa<InlineAsm>(Callee))
1025 // Handle intrinsic calls.
1026 if (Function *F = CI->getCalledFunction())
1027 if (F->isDeclaration())
1028 if (unsigned IID = F->getIntrinsicID())
1029 return X86VisitIntrinsicCall(*CI, IID);
1031 // Handle only C and fastcc calling conventions for now.
1033 unsigned CC = CS.getCallingConv();
1034 if (CC != CallingConv::C &&
1035 CC != CallingConv::Fast &&
1036 CC != CallingConv::X86_FastCall)
1039 // Let SDISel handle vararg functions.
1040 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1041 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1042 if (FTy->isVarArg())
1045 // Handle *simple* calls for now.
1046 const Type *RetTy = CS.getType();
1048 if (RetTy == Type::VoidTy)
1049 RetVT = MVT::isVoid;
1050 else if (!isTypeLegal(RetTy, RetVT, true))
1053 // Materialize callee address in a register. FIXME: GV address can be
1054 // handled with a CALLpcrel32 instead.
1055 X86AddressMode CalleeAM;
1056 if (!X86SelectAddress(Callee, CalleeAM, true))
1058 unsigned CalleeOp = 0;
1059 GlobalValue *GV = 0;
1060 if (CalleeAM.Base.Reg != 0) {
1061 assert(CalleeAM.GV == 0);
1062 CalleeOp = CalleeAM.Base.Reg;
1063 } else if (CalleeAM.GV != 0) {
1064 assert(CalleeAM.GV != 0);
1069 // Allow calls which produce i1 results.
1070 bool AndToI1 = false;
1071 if (RetVT == MVT::i1) {
1076 // Deal with call operands first.
1077 SmallVector<Value*, 8> ArgVals;
1078 SmallVector<unsigned, 8> Args;
1079 SmallVector<MVT, 8> ArgVTs;
1080 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1081 Args.reserve(CS.arg_size());
1082 ArgVals.reserve(CS.arg_size());
1083 ArgVTs.reserve(CS.arg_size());
1084 ArgFlags.reserve(CS.arg_size());
1085 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1087 unsigned Arg = getRegForValue(*i);
1090 ISD::ArgFlagsTy Flags;
1091 unsigned AttrInd = i - CS.arg_begin() + 1;
1092 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1094 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1097 // FIXME: Only handle *easy* calls for now.
1098 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1099 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1100 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1101 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1104 const Type *ArgTy = (*i)->getType();
1106 if (!isTypeLegal(ArgTy, ArgVT))
1108 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1109 Flags.setOrigAlign(OriginalAlignment);
1111 Args.push_back(Arg);
1112 ArgVals.push_back(*i);
1113 ArgVTs.push_back(ArgVT);
1114 ArgFlags.push_back(Flags);
1117 // Analyze operands of the call, assigning locations to each operand.
1118 SmallVector<CCValAssign, 16> ArgLocs;
1119 CCState CCInfo(CC, false, TM, ArgLocs);
1120 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1122 // Get a count of how many bytes are to be pushed on the stack.
1123 unsigned NumBytes = CCInfo.getNextStackOffset();
1125 // Issue CALLSEQ_START
1126 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1127 BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes);
1129 // Process argument: walk the register/memloc assignments, inserting
1131 SmallVector<unsigned, 4> RegArgs;
1132 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1133 CCValAssign &VA = ArgLocs[i];
1134 unsigned Arg = Args[VA.getValNo()];
1135 MVT ArgVT = ArgVTs[VA.getValNo()];
1137 // Promote the value if needed.
1138 switch (VA.getLocInfo()) {
1139 default: assert(0 && "Unknown loc info!");
1140 case CCValAssign::Full: break;
1141 case CCValAssign::SExt: {
1142 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1144 assert(Emitted && "Failed to emit a sext!");
1145 ArgVT = VA.getLocVT();
1148 case CCValAssign::ZExt: {
1149 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1151 assert(Emitted && "Failed to emit a zext!");
1152 ArgVT = VA.getLocVT();
1155 case CCValAssign::AExt: {
1156 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1159 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1162 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1165 assert(Emitted && "Failed to emit a aext!");
1166 ArgVT = VA.getLocVT();
1171 if (VA.isRegLoc()) {
1172 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1173 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1175 assert(Emitted && "Failed to emit a copy instruction!");
1176 RegArgs.push_back(VA.getLocReg());
1178 unsigned LocMemOffset = VA.getLocMemOffset();
1180 AM.Base.Reg = StackPtr;
1181 AM.Disp = LocMemOffset;
1182 Value *ArgVal = ArgVals[VA.getValNo()];
1184 // If this is a really simple value, emit this with the Value* version of
1185 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1186 // can cause us to reevaluate the argument.
1187 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1188 X86FastEmitStore(ArgVT, ArgVal, AM);
1190 X86FastEmitStore(ArgVT, Arg, AM);
1194 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1196 if (!Subtarget->is64Bit() &&
1197 TM.getRelocationModel() == Reloc::PIC_ &&
1198 Subtarget->isPICStyleGOT()) {
1199 TargetRegisterClass *RC = X86::GR32RegisterClass;
1200 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1201 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1202 assert(Emitted && "Failed to emit a copy instruction!");
1206 unsigned CallOpc = CalleeOp
1207 ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
1208 : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
1209 MachineInstrBuilder MIB = CalleeOp
1210 ? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp)
1211 : BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(GV);
1213 // Add an implicit use GOT pointer in EBX.
1214 if (!Subtarget->is64Bit() &&
1215 TM.getRelocationModel() == Reloc::PIC_ &&
1216 Subtarget->isPICStyleGOT())
1217 MIB.addReg(X86::EBX);
1219 // Add implicit physical register uses to the call.
1220 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1221 MIB.addReg(RegArgs[i]);
1223 // Issue CALLSEQ_END
1224 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1225 BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1227 // Now handle call return value (if any).
1228 if (RetVT.getSimpleVT() != MVT::isVoid) {
1229 SmallVector<CCValAssign, 16> RVLocs;
1230 CCState CCInfo(CC, false, TM, RVLocs);
1231 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1233 // Copy all of the result registers out of their specified physreg.
1234 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1235 MVT CopyVT = RVLocs[0].getValVT();
1236 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1237 TargetRegisterClass *SrcRC = DstRC;
1239 // If this is a call to a function that returns an fp value on the x87 fp
1240 // stack, but where we prefer to use the value in xmm registers, copy it
1241 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1242 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1243 RVLocs[0].getLocReg() == X86::ST1) &&
1244 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1246 SrcRC = X86::RSTRegisterClass;
1247 DstRC = X86::RFP80RegisterClass;
1250 unsigned ResultReg = createResultReg(DstRC);
1251 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1252 RVLocs[0].getLocReg(), DstRC, SrcRC);
1253 assert(Emitted && "Failed to emit a copy instruction!");
1254 if (CopyVT != RVLocs[0].getValVT()) {
1255 // Round the F80 the right size, which also moves to the appropriate xmm
1256 // register. This is accomplished by storing the F80 value in memory and
1257 // then loading it back. Ewww...
1258 MVT ResVT = RVLocs[0].getValVT();
1259 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1260 unsigned MemSize = ResVT.getSizeInBits()/8;
1261 int FI = MFI.CreateStackObject(MemSize, MemSize);
1262 addFrameReference(BuildMI(MBB, TII.get(Opc)), FI).addReg(ResultReg);
1263 DstRC = ResVT == MVT::f32
1264 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1265 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1266 ResultReg = createResultReg(DstRC);
1267 addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI);
1271 // Mask out all but lowest bit for some call which produces an i1.
1272 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1273 BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1274 ResultReg = AndResult;
1277 UpdateValueMap(I, ResultReg);
1285 X86FastISel::TargetSelectInstruction(Instruction *I) {
1286 switch (I->getOpcode()) {
1288 case Instruction::Load:
1289 return X86SelectLoad(I);
1290 case Instruction::Store:
1291 return X86SelectStore(I);
1292 case Instruction::ICmp:
1293 case Instruction::FCmp:
1294 return X86SelectCmp(I);
1295 case Instruction::ZExt:
1296 return X86SelectZExt(I);
1297 case Instruction::Br:
1298 return X86SelectBranch(I);
1299 case Instruction::Call:
1300 return X86SelectCall(I);
1301 case Instruction::LShr:
1302 case Instruction::AShr:
1303 case Instruction::Shl:
1304 return X86SelectShift(I);
1305 case Instruction::Select:
1306 return X86SelectSelect(I);
1307 case Instruction::Trunc:
1308 return X86SelectTrunc(I);
1309 case Instruction::FPExt:
1310 return X86SelectFPExt(I);
1311 case Instruction::FPTrunc:
1312 return X86SelectFPTrunc(I);
1313 case Instruction::ExtractValue:
1314 return X86SelectExtractValue(I);
1320 unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
1322 if (!isTypeLegal(C->getType(), VT))
1325 // Get opcode and regclass of the output for the given load instruction.
1327 const TargetRegisterClass *RC = NULL;
1328 switch (VT.getSimpleVT()) {
1329 default: return false;
1332 RC = X86::GR8RegisterClass;
1336 RC = X86::GR16RegisterClass;
1340 RC = X86::GR32RegisterClass;
1343 // Must be in x86-64 mode.
1345 RC = X86::GR64RegisterClass;
1348 if (Subtarget->hasSSE1()) {
1350 RC = X86::FR32RegisterClass;
1352 Opc = X86::LD_Fp32m;
1353 RC = X86::RFP32RegisterClass;
1357 if (Subtarget->hasSSE2()) {
1359 RC = X86::FR64RegisterClass;
1361 Opc = X86::LD_Fp64m;
1362 RC = X86::RFP64RegisterClass;
1366 // No f80 support yet.
1370 // Materialize addresses with LEA instructions.
1371 if (isa<GlobalValue>(C)) {
1373 if (X86SelectAddress(C, AM, false)) {
1374 if (TLI.getPointerTy() == MVT::i32)
1378 unsigned ResultReg = createResultReg(RC);
1379 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
1385 // MachineConstantPool wants an explicit alignment.
1386 unsigned Align = TD.getPreferredTypeAlignmentShift(C->getType());
1388 // Alignment of vector types. FIXME!
1389 Align = TD.getABITypeSize(C->getType());
1390 Align = Log2_64(Align);
1393 // x86-32 PIC requires a PIC base register for constant pools.
1394 unsigned PICBase = 0;
1395 if (TM.getRelocationModel() == Reloc::PIC_ &&
1396 !Subtarget->is64Bit())
1397 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1399 // Create the load from the constant pool.
1400 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1401 unsigned ResultReg = createResultReg(RC);
1402 addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset,
1408 unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
1409 // Fail on dynamic allocas. At this point, getRegForValue has already
1410 // checked its CSE maps, so if we're here trying to handle a dynamic
1411 // alloca, we're not going to succeed. X86SelectAddress has a
1412 // check for dynamic allocas, because it's called directly from
1413 // various places, but TargetMaterializeAlloca also needs a check
1414 // in order to avoid recursion between getRegForValue,
1415 // X86SelectAddrss, and TargetMaterializeAlloca.
1416 if (!StaticAllocaMap.count(C))
1420 if (!X86SelectAddress(C, AM, false))
1422 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1423 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1424 unsigned ResultReg = createResultReg(RC);
1425 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
1430 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1431 MachineModuleInfo *mmi,
1432 DenseMap<const Value *, unsigned> &vm,
1433 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1434 DenseMap<const AllocaInst *, int> &am
1436 , SmallSet<Instruction*, 8> &cil
1439 return new X86FastISel(mf, mmi, vm, bm, am