1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/Support/CallSite.h"
30 #include "llvm/Support/GetElementPtrTypeIterator.h"
34 class X86FastISel : public FastISel {
35 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
36 /// make the right decision when generating code for different targets.
37 const X86Subtarget *Subtarget;
39 /// StackPtr - Register used as the stack pointer.
43 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
44 /// floating point ops.
45 /// When SSE is available, use it for f32 operations.
46 /// When SSE2 is available, use it for f64 operations.
51 explicit X86FastISel(MachineFunction &mf,
52 MachineModuleInfo *mmi,
53 DenseMap<const Value *, unsigned> &vm,
54 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
55 DenseMap<const AllocaInst *, int> &am
57 , SmallSet<Instruction*, 8> &cil
60 : FastISel(mf, mmi, vm, bm, am
65 Subtarget = &TM.getSubtarget<X86Subtarget>();
66 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
67 X86ScalarSSEf64 = Subtarget->hasSSE2();
68 X86ScalarSSEf32 = Subtarget->hasSSE1();
71 virtual bool TargetSelectInstruction(Instruction *I);
73 #include "X86GenFastISel.inc"
76 bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
78 bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
80 bool X86FastEmitStore(MVT VT, unsigned Val,
81 const X86AddressMode &AM);
83 bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
86 bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
88 bool X86SelectLoad(Instruction *I);
90 bool X86SelectStore(Instruction *I);
92 bool X86SelectCmp(Instruction *I);
94 bool X86SelectZExt(Instruction *I);
96 bool X86SelectBranch(Instruction *I);
98 bool X86SelectShift(Instruction *I);
100 bool X86SelectSelect(Instruction *I);
102 bool X86SelectTrunc(Instruction *I);
104 bool X86SelectFPExt(Instruction *I);
105 bool X86SelectFPTrunc(Instruction *I);
107 bool X86SelectCall(Instruction *I);
109 CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
111 const X86InstrInfo *getInstrInfo() const {
112 return getTargetMachine()->getInstrInfo();
114 const X86TargetMachine *getTargetMachine() const {
115 return static_cast<const X86TargetMachine *>(&TM);
118 unsigned TargetMaterializeConstant(Constant *C);
120 unsigned TargetMaterializeAlloca(AllocaInst *C);
122 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
123 /// computed in an SSE register, not on the X87 floating point stack.
124 bool isScalarFPTypeInSSEReg(MVT VT) const {
125 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
126 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
129 bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
132 bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
133 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
134 if (VT == MVT::Other || !VT.isSimple())
135 // Unhandled type. Halt "fast" selection and bail.
138 // For now, require SSE/SSE2 for performing floating-point operations,
139 // since x87 requires additional work.
140 if (VT == MVT::f64 && !X86ScalarSSEf64)
142 if (VT == MVT::f32 && !X86ScalarSSEf32)
144 // Similarly, no f80 support yet.
147 // We only handle legal types. For example, on x86-32 the instruction
148 // selector contains all of the 64-bit instructions from x86-64,
149 // under the assumption that i64 won't be used if the target doesn't
151 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
154 #include "X86GenCallingConv.inc"
156 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
158 CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
159 if (Subtarget->is64Bit()) {
160 if (Subtarget->isTargetWin64())
161 return CC_X86_Win64_C;
162 else if (CC == CallingConv::Fast && isTaillCall)
163 return CC_X86_64_TailCall;
168 if (CC == CallingConv::X86_FastCall)
169 return CC_X86_32_FastCall;
170 else if (CC == CallingConv::Fast)
171 return CC_X86_32_FastCC;
176 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
177 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
178 /// Return true and the result register by reference if it is possible.
179 bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
180 unsigned &ResultReg) {
181 // Get opcode and regclass of the output for the given load instruction.
183 const TargetRegisterClass *RC = NULL;
184 switch (VT.getSimpleVT()) {
185 default: return false;
188 RC = X86::GR8RegisterClass;
192 RC = X86::GR16RegisterClass;
196 RC = X86::GR32RegisterClass;
199 // Must be in x86-64 mode.
201 RC = X86::GR64RegisterClass;
204 if (Subtarget->hasSSE1()) {
206 RC = X86::FR32RegisterClass;
209 RC = X86::RFP32RegisterClass;
213 if (Subtarget->hasSSE2()) {
215 RC = X86::FR64RegisterClass;
218 RC = X86::RFP64RegisterClass;
222 // No f80 support yet.
226 ResultReg = createResultReg(RC);
227 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
231 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
232 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
233 /// and a displacement offset, or a GlobalAddress,
234 /// i.e. V. Return true if it is possible.
236 X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
237 const X86AddressMode &AM) {
238 // Get opcode and regclass of the output for the given store instruction.
240 const TargetRegisterClass *RC = NULL;
241 switch (VT.getSimpleVT()) {
242 default: return false;
245 RC = X86::GR8RegisterClass;
249 RC = X86::GR16RegisterClass;
253 RC = X86::GR32RegisterClass;
256 // Must be in x86-64 mode.
258 RC = X86::GR64RegisterClass;
261 if (Subtarget->hasSSE1()) {
263 RC = X86::FR32RegisterClass;
266 RC = X86::RFP32RegisterClass;
270 if (Subtarget->hasSSE2()) {
272 RC = X86::FR64RegisterClass;
275 RC = X86::RFP64RegisterClass;
279 // No f80 support yet.
283 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Val);
287 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
288 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
289 /// ISD::SIGN_EXTEND).
290 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
291 unsigned Src, MVT SrcVT,
292 unsigned &ResultReg) {
293 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
302 /// X86SelectAddress - Attempt to fill in an address from the given value.
304 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
306 unsigned Opcode = Instruction::UserOp1;
307 if (Instruction *I = dyn_cast<Instruction>(V)) {
308 Opcode = I->getOpcode();
310 } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
311 Opcode = C->getOpcode();
317 case Instruction::BitCast:
318 // Look past bitcasts.
319 return X86SelectAddress(U->getOperand(0), AM, isCall);
321 case Instruction::IntToPtr:
322 // Look past no-op inttoptrs.
323 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
324 return X86SelectAddress(U->getOperand(0), AM, isCall);
326 case Instruction::PtrToInt:
327 // Look past no-op ptrtoints.
328 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
329 return X86SelectAddress(U->getOperand(0), AM, isCall);
331 case Instruction::Alloca: {
333 // Do static allocas.
334 const AllocaInst *A = cast<AllocaInst>(V);
335 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
336 if (SI != StaticAllocaMap.end()) {
337 AM.BaseType = X86AddressMode::FrameIndexBase;
338 AM.Base.FrameIndex = SI->second;
344 case Instruction::Add: {
346 // Adds of constants are common and easy enough.
347 if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
348 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
349 // They have to fit in the 32-bit signed displacement field though.
351 AM.Disp = (uint32_t)Disp;
352 return X86SelectAddress(U->getOperand(0), AM, isCall);
358 case Instruction::GetElementPtr: {
360 // Pattern-match simple GEPs.
361 uint64_t Disp = (int32_t)AM.Disp;
362 unsigned IndexReg = AM.IndexReg;
363 unsigned Scale = AM.Scale;
364 gep_type_iterator GTI = gep_type_begin(U);
365 // Look at all but the last index. Constants can be folded,
366 // and one dynamic index can be handled, if the scale is supported.
367 for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
368 i != e; ++i, ++GTI) {
370 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
371 const StructLayout *SL = TD.getStructLayout(STy);
372 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
373 Disp += SL->getElementOffset(Idx);
375 uint64_t S = TD.getABITypeSize(GTI.getIndexedType());
376 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
377 // Constant-offset addressing.
378 Disp += CI->getSExtValue() * S;
379 } else if (IndexReg == 0 &&
381 !getTargetMachine()->symbolicAddressesAreRIPRel()) &&
382 (S == 1 || S == 2 || S == 4 || S == 8)) {
383 // Scaled-index addressing.
385 IndexReg = getRegForValue(Op);
390 goto unsupported_gep;
393 // Check for displacement overflow.
396 // Ok, the GEP indices were covered by constant-offset and scaled-index
397 // addressing. Update the address state and move on to examining the base.
398 AM.IndexReg = IndexReg;
400 AM.Disp = (uint32_t)Disp;
401 return X86SelectAddress(U->getOperand(0), AM, isCall);
403 // Ok, the GEP indices weren't all covered.
408 // Handle constant address.
409 if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
410 // Can't handle alternate code models yet.
411 if (TM.getCodeModel() != CodeModel::Default &&
412 TM.getCodeModel() != CodeModel::Small)
415 // RIP-relative addresses can't have additional register operands.
416 if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
417 (AM.Base.Reg != 0 || AM.IndexReg != 0))
420 // Set up the basic address.
423 TM.getRelocationModel() == Reloc::PIC_ &&
424 !Subtarget->is64Bit())
425 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
427 // Emit an extra load if the ABI requires it.
428 if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
429 // Check to see if we've already materialized this
430 // value in a register in this block.
431 if (unsigned Reg = LocalValueMap[V]) {
436 // Issue load from stub if necessary.
438 const TargetRegisterClass *RC = NULL;
439 if (TLI.getPointerTy() == MVT::i32) {
441 RC = X86::GR32RegisterClass;
444 RC = X86::GR64RegisterClass;
447 X86AddressMode StubAM;
448 StubAM.Base.Reg = AM.Base.Reg;
450 unsigned ResultReg = createResultReg(RC);
451 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), StubAM);
453 // Now construct the final address. Note that the Disp, Scale,
454 // and Index values may already be set here.
455 AM.Base.Reg = ResultReg;
458 // Prevent loading GV stub multiple times in same MBB.
459 LocalValueMap[V] = AM.Base.Reg;
464 // If all else fails, try to materialize the value in a register.
465 if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
466 if (AM.Base.Reg == 0) {
467 AM.Base.Reg = getRegForValue(V);
468 return AM.Base.Reg != 0;
470 if (AM.IndexReg == 0) {
471 assert(AM.Scale == 1 && "Scale with no index!");
472 AM.IndexReg = getRegForValue(V);
473 return AM.IndexReg != 0;
480 /// X86SelectStore - Select and emit code to implement store instructions.
481 bool X86FastISel::X86SelectStore(Instruction* I) {
483 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
485 unsigned Val = getRegForValue(I->getOperand(0));
487 // Unhandled operand. Halt "fast" selection and bail.
491 if (!X86SelectAddress(I->getOperand(1), AM, false))
494 return X86FastEmitStore(VT, Val, AM);
497 /// X86SelectLoad - Select and emit code to implement load instructions.
499 bool X86FastISel::X86SelectLoad(Instruction *I) {
501 if (!isTypeLegal(I->getType(), VT))
505 if (!X86SelectAddress(I->getOperand(0), AM, false))
508 unsigned ResultReg = 0;
509 if (X86FastEmitLoad(VT, AM, ResultReg)) {
510 UpdateValueMap(I, ResultReg);
516 static unsigned X86ChooseCmpOpcode(MVT VT) {
517 switch (VT.getSimpleVT()) {
519 case MVT::i8: return X86::CMP8rr;
520 case MVT::i16: return X86::CMP16rr;
521 case MVT::i32: return X86::CMP32rr;
522 case MVT::i64: return X86::CMP64rr;
523 case MVT::f32: return X86::UCOMISSrr;
524 case MVT::f64: return X86::UCOMISDrr;
528 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
529 /// of the comparison, return an opcode that works for the compare (e.g.
530 /// CMP32ri) otherwise return 0.
531 static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
532 switch (VT.getSimpleVT()) {
533 // Otherwise, we can't fold the immediate into this comparison.
535 case MVT::i8: return X86::CMP8ri;
536 case MVT::i16: return X86::CMP16ri;
537 case MVT::i32: return X86::CMP32ri;
539 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
541 if (RHSC->getType() == Type::Int64Ty &&
542 (int)RHSC->getSExtValue() == RHSC->getSExtValue())
543 return X86::CMP64ri32;
548 bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
549 unsigned Op0Reg = getRegForValue(Op0);
550 if (Op0Reg == 0) return false;
552 // Handle 'null' like i32/i64 0.
553 if (isa<ConstantPointerNull>(Op1))
554 Op1 = Constant::getNullValue(TD.getIntPtrType());
556 // We have two options: compare with register or immediate. If the RHS of
557 // the compare is an immediate that we can fold into this compare, use
558 // CMPri, otherwise use CMPrr.
559 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
560 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
561 BuildMI(MBB, TII.get(CompareImmOpc)).addReg(Op0Reg)
562 .addImm(Op1C->getSExtValue());
567 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
568 if (CompareOpc == 0) return false;
570 unsigned Op1Reg = getRegForValue(Op1);
571 if (Op1Reg == 0) return false;
572 BuildMI(MBB, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
577 bool X86FastISel::X86SelectCmp(Instruction *I) {
578 CmpInst *CI = cast<CmpInst>(I);
581 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
584 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
586 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
587 switch (CI->getPredicate()) {
588 case CmpInst::FCMP_OEQ: {
589 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
592 unsigned EReg = createResultReg(&X86::GR8RegClass);
593 unsigned NPReg = createResultReg(&X86::GR8RegClass);
594 BuildMI(MBB, TII.get(X86::SETEr), EReg);
595 BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
596 BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
597 UpdateValueMap(I, ResultReg);
600 case CmpInst::FCMP_UNE: {
601 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
604 unsigned NEReg = createResultReg(&X86::GR8RegClass);
605 unsigned PReg = createResultReg(&X86::GR8RegClass);
606 BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
607 BuildMI(MBB, TII.get(X86::SETPr), PReg);
608 BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
609 UpdateValueMap(I, ResultReg);
612 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
613 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
614 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
615 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
616 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
617 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
618 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
619 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
620 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
621 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
622 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
623 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
625 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
626 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
627 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
628 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
629 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
630 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
631 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
632 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
633 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
634 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
639 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
643 // Emit a compare of Op0/Op1.
644 if (!X86FastEmitCompare(Op0, Op1, VT))
647 BuildMI(MBB, TII.get(SetCCOpc), ResultReg);
648 UpdateValueMap(I, ResultReg);
652 bool X86FastISel::X86SelectZExt(Instruction *I) {
653 // Special-case hack: The only i1 values we know how to produce currently
654 // set the upper bits of an i8 value to zero.
655 if (I->getType() == Type::Int8Ty &&
656 I->getOperand(0)->getType() == Type::Int1Ty) {
657 unsigned ResultReg = getRegForValue(I->getOperand(0));
658 if (ResultReg == 0) return false;
659 UpdateValueMap(I, ResultReg);
667 bool X86FastISel::X86SelectBranch(Instruction *I) {
668 // Unconditional branches are selected by tablegen-generated code.
669 // Handle a conditional branch.
670 BranchInst *BI = cast<BranchInst>(I);
671 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
672 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
674 // Fold the common case of a conditional branch with a comparison.
675 if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
676 if (CI->hasOneUse()) {
677 MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
679 // Try to take advantage of fallthrough opportunities.
680 CmpInst::Predicate Predicate = CI->getPredicate();
681 if (MBB->isLayoutSuccessor(TrueMBB)) {
682 std::swap(TrueMBB, FalseMBB);
683 Predicate = CmpInst::getInversePredicate(Predicate);
686 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
687 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
690 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA; break;
691 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
692 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA; break;
693 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE; break;
694 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
695 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
696 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP; break;
697 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE; break;
698 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB; break;
699 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE; break;
700 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
701 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
703 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE; break;
704 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE; break;
705 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA; break;
706 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
707 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB; break;
708 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
709 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG; break;
710 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
711 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL; break;
712 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
717 Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
721 // Emit a compare of the LHS and RHS, setting the flags.
722 if (!X86FastEmitCompare(Op0, Op1, VT))
725 BuildMI(MBB, TII.get(BranchOpc)).addMBB(TrueMBB);
726 FastEmitBranch(FalseMBB);
727 MBB->addSuccessor(TrueMBB);
732 // Otherwise do a clumsy setcc and re-test it.
733 unsigned OpReg = getRegForValue(BI->getCondition());
734 if (OpReg == 0) return false;
736 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
737 BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
738 FastEmitBranch(FalseMBB);
739 MBB->addSuccessor(TrueMBB);
743 bool X86FastISel::X86SelectShift(Instruction *I) {
744 unsigned CReg = 0, OpReg = 0, OpImm = 0;
745 const TargetRegisterClass *RC = NULL;
746 if (I->getType() == Type::Int8Ty) {
748 RC = &X86::GR8RegClass;
749 switch (I->getOpcode()) {
750 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
751 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
752 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
753 default: return false;
755 } else if (I->getType() == Type::Int16Ty) {
757 RC = &X86::GR16RegClass;
758 switch (I->getOpcode()) {
759 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
760 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
761 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
762 default: return false;
764 } else if (I->getType() == Type::Int32Ty) {
766 RC = &X86::GR32RegClass;
767 switch (I->getOpcode()) {
768 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
769 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
770 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
771 default: return false;
773 } else if (I->getType() == Type::Int64Ty) {
775 RC = &X86::GR64RegClass;
776 switch (I->getOpcode()) {
777 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
778 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
779 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
780 default: return false;
786 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
787 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
790 unsigned Op0Reg = getRegForValue(I->getOperand(0));
791 if (Op0Reg == 0) return false;
793 // Fold immediate in shl(x,3).
794 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
795 unsigned ResultReg = createResultReg(RC);
796 BuildMI(MBB, TII.get(OpImm),
797 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue());
798 UpdateValueMap(I, ResultReg);
802 unsigned Op1Reg = getRegForValue(I->getOperand(1));
803 if (Op1Reg == 0) return false;
804 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
806 // The shift instruction uses X86::CL. If we defined a super-register
807 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
810 BuildMI(MBB, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
811 .addReg(CReg).addImm(X86::SUBREG_8BIT);
813 unsigned ResultReg = createResultReg(RC);
814 BuildMI(MBB, TII.get(OpReg), ResultReg).addReg(Op0Reg);
815 UpdateValueMap(I, ResultReg);
819 bool X86FastISel::X86SelectSelect(Instruction *I) {
820 MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
821 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
825 const TargetRegisterClass *RC = NULL;
826 if (VT.getSimpleVT() == MVT::i16) {
827 Opc = X86::CMOVE16rr;
828 RC = &X86::GR16RegClass;
829 } else if (VT.getSimpleVT() == MVT::i32) {
830 Opc = X86::CMOVE32rr;
831 RC = &X86::GR32RegClass;
832 } else if (VT.getSimpleVT() == MVT::i64) {
833 Opc = X86::CMOVE64rr;
834 RC = &X86::GR64RegClass;
839 unsigned Op0Reg = getRegForValue(I->getOperand(0));
840 if (Op0Reg == 0) return false;
841 unsigned Op1Reg = getRegForValue(I->getOperand(1));
842 if (Op1Reg == 0) return false;
843 unsigned Op2Reg = getRegForValue(I->getOperand(2));
844 if (Op2Reg == 0) return false;
846 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
847 unsigned ResultReg = createResultReg(RC);
848 BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
849 UpdateValueMap(I, ResultReg);
853 bool X86FastISel::X86SelectFPExt(Instruction *I) {
854 // fpext from float to double.
855 if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
856 Value *V = I->getOperand(0);
857 if (V->getType() == Type::FloatTy) {
858 unsigned OpReg = getRegForValue(V);
859 if (OpReg == 0) return false;
860 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
861 BuildMI(MBB, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
862 UpdateValueMap(I, ResultReg);
870 bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
871 if (Subtarget->hasSSE2()) {
872 if (I->getType() == Type::FloatTy) {
873 Value *V = I->getOperand(0);
874 if (V->getType() == Type::DoubleTy) {
875 unsigned OpReg = getRegForValue(V);
876 if (OpReg == 0) return false;
877 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
878 BuildMI(MBB, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
879 UpdateValueMap(I, ResultReg);
888 bool X86FastISel::X86SelectTrunc(Instruction *I) {
889 if (Subtarget->is64Bit())
890 // All other cases should be handled by the tblgen generated code.
892 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
893 MVT DstVT = TLI.getValueType(I->getType());
894 if (DstVT != MVT::i8)
895 // All other cases should be handled by the tblgen generated code.
897 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
898 // All other cases should be handled by the tblgen generated code.
901 unsigned InputReg = getRegForValue(I->getOperand(0));
903 // Unhandled operand. Halt "fast" selection and bail.
906 // First issue a copy to GR16_ or GR32_.
907 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16to16_ : X86::MOV32to32_;
908 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
909 ? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
910 unsigned CopyReg = createResultReg(CopyRC);
911 BuildMI(MBB, TII.get(CopyOpc), CopyReg).addReg(InputReg);
913 // Then issue an extract_subreg.
914 unsigned ResultReg = FastEmitInst_extractsubreg(CopyReg, X86::SUBREG_8BIT);
918 UpdateValueMap(I, ResultReg);
922 bool X86FastISel::X86SelectCall(Instruction *I) {
923 CallInst *CI = cast<CallInst>(I);
924 Value *Callee = I->getOperand(0);
926 // Can't handle inline asm yet.
927 if (isa<InlineAsm>(Callee))
930 // FIXME: Handle some intrinsics.
931 if (Function *F = CI->getCalledFunction()) {
932 if (F->isDeclaration() &&F->getIntrinsicID())
936 // Handle only C and fastcc calling conventions for now.
938 unsigned CC = CS.getCallingConv();
939 if (CC != CallingConv::C &&
940 CC != CallingConv::Fast &&
941 CC != CallingConv::X86_FastCall)
944 // Let SDISel handle vararg functions.
945 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
946 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
950 // Handle *simple* calls for now.
951 const Type *RetTy = CS.getType();
953 if (RetTy == Type::VoidTy)
955 else if (!isTypeLegal(RetTy, RetVT, true))
958 // Materialize callee address in a register. FIXME: GV address can be
959 // handled with a CALLpcrel32 instead.
960 X86AddressMode CalleeAM;
961 if (!X86SelectAddress(Callee, CalleeAM, true))
963 unsigned CalleeOp = 0;
965 if (CalleeAM.Base.Reg != 0) {
966 assert(CalleeAM.GV == 0);
967 CalleeOp = CalleeAM.Base.Reg;
968 } else if (CalleeAM.GV != 0) {
969 assert(CalleeAM.GV != 0);
974 // Allow calls which produce i1 results.
975 bool AndToI1 = false;
976 if (RetVT == MVT::i1) {
981 // Deal with call operands first.
982 SmallVector<unsigned, 4> Args;
983 SmallVector<MVT, 4> ArgVTs;
984 SmallVector<ISD::ArgFlagsTy, 4> ArgFlags;
985 Args.reserve(CS.arg_size());
986 ArgVTs.reserve(CS.arg_size());
987 ArgFlags.reserve(CS.arg_size());
988 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
990 unsigned Arg = getRegForValue(*i);
993 ISD::ArgFlagsTy Flags;
994 unsigned AttrInd = i - CS.arg_begin() + 1;
995 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
997 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1000 // FIXME: Only handle *easy* calls for now.
1001 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1002 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1003 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1004 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1007 const Type *ArgTy = (*i)->getType();
1009 if (!isTypeLegal(ArgTy, ArgVT))
1011 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1012 Flags.setOrigAlign(OriginalAlignment);
1014 Args.push_back(Arg);
1015 ArgVTs.push_back(ArgVT);
1016 ArgFlags.push_back(Flags);
1019 // Analyze operands of the call, assigning locations to each operand.
1020 SmallVector<CCValAssign, 16> ArgLocs;
1021 CCState CCInfo(CC, false, TM, ArgLocs);
1022 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1024 // Get a count of how many bytes are to be pushed on the stack.
1025 unsigned NumBytes = CCInfo.getNextStackOffset();
1027 // Issue CALLSEQ_START
1028 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1029 BuildMI(MBB, TII.get(AdjStackDown)).addImm(NumBytes);
1031 // Process argumenet: walk the register/memloc assignments, inserting
1033 SmallVector<unsigned, 4> RegArgs;
1034 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1035 CCValAssign &VA = ArgLocs[i];
1036 unsigned Arg = Args[VA.getValNo()];
1037 MVT ArgVT = ArgVTs[VA.getValNo()];
1039 // Promote the value if needed.
1040 switch (VA.getLocInfo()) {
1041 default: assert(0 && "Unknown loc info!");
1042 case CCValAssign::Full: break;
1043 case CCValAssign::SExt: {
1044 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1046 assert(Emitted && "Failed to emit a sext!");
1047 ArgVT = VA.getLocVT();
1050 case CCValAssign::ZExt: {
1051 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1053 assert(Emitted && "Failed to emit a zext!");
1054 ArgVT = VA.getLocVT();
1057 case CCValAssign::AExt: {
1058 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1061 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1064 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1067 assert(Emitted && "Failed to emit a aext!");
1068 ArgVT = VA.getLocVT();
1073 if (VA.isRegLoc()) {
1074 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1075 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1077 assert(Emitted && "Failed to emit a copy instruction!");
1078 RegArgs.push_back(VA.getLocReg());
1080 unsigned LocMemOffset = VA.getLocMemOffset();
1082 AM.Base.Reg = StackPtr;
1083 AM.Disp = LocMemOffset;
1084 X86FastEmitStore(ArgVT, Arg, AM);
1088 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1090 if (!Subtarget->is64Bit() &&
1091 TM.getRelocationModel() == Reloc::PIC_ &&
1092 Subtarget->isPICStyleGOT()) {
1093 TargetRegisterClass *RC = X86::GR32RegisterClass;
1094 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1095 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1096 assert(Emitted && "Failed to emit a copy instruction!");
1100 unsigned CallOpc = CalleeOp
1101 ? (Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r)
1102 : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
1103 MachineInstrBuilder MIB = CalleeOp
1104 ? BuildMI(MBB, TII.get(CallOpc)).addReg(CalleeOp)
1105 : BuildMI(MBB, TII.get(CallOpc)).addGlobalAddress(GV);
1107 // Add an implicit use GOT pointer in EBX.
1108 if (!Subtarget->is64Bit() &&
1109 TM.getRelocationModel() == Reloc::PIC_ &&
1110 Subtarget->isPICStyleGOT())
1111 MIB.addReg(X86::EBX);
1113 // Add implicit physical register uses to the call.
1114 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1115 MIB.addReg(RegArgs[i]);
1117 // Issue CALLSEQ_END
1118 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1119 BuildMI(MBB, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1121 // Now handle call return value (if any).
1122 if (RetVT.getSimpleVT() != MVT::isVoid) {
1123 SmallVector<CCValAssign, 16> RVLocs;
1124 CCState CCInfo(CC, false, TM, RVLocs);
1125 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1127 // Copy all of the result registers out of their specified physreg.
1128 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1129 MVT CopyVT = RVLocs[0].getValVT();
1130 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1131 TargetRegisterClass *SrcRC = DstRC;
1133 // If this is a call to a function that returns an fp value on the x87 fp
1134 // stack, but where we prefer to use the value in xmm registers, copy it
1135 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1136 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1137 RVLocs[0].getLocReg() == X86::ST1) &&
1138 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1140 SrcRC = X86::RSTRegisterClass;
1141 DstRC = X86::RFP80RegisterClass;
1144 unsigned ResultReg = createResultReg(DstRC);
1145 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1146 RVLocs[0].getLocReg(), DstRC, SrcRC);
1147 assert(Emitted && "Failed to emit a copy instruction!");
1148 if (CopyVT != RVLocs[0].getValVT()) {
1149 // Round the F80 the right size, which also moves to the appropriate xmm
1150 // register. This is accomplished by storing the F80 value in memory and
1151 // then loading it back. Ewww...
1152 MVT ResVT = RVLocs[0].getValVT();
1153 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1154 unsigned MemSize = ResVT.getSizeInBits()/8;
1155 int FI = MFI.CreateStackObject(MemSize, MemSize);
1156 addFrameReference(BuildMI(MBB, TII.get(Opc)), FI).addReg(ResultReg);
1157 DstRC = ResVT == MVT::f32
1158 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1159 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1160 ResultReg = createResultReg(DstRC);
1161 addFrameReference(BuildMI(MBB, TII.get(Opc), ResultReg), FI);
1165 // Mask out all but lowest bit for some call which produces an i1.
1166 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1167 BuildMI(MBB, TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1168 ResultReg = AndResult;
1171 UpdateValueMap(I, ResultReg);
1179 X86FastISel::TargetSelectInstruction(Instruction *I) {
1180 switch (I->getOpcode()) {
1182 case Instruction::Load:
1183 return X86SelectLoad(I);
1184 case Instruction::Store:
1185 return X86SelectStore(I);
1186 case Instruction::ICmp:
1187 case Instruction::FCmp:
1188 return X86SelectCmp(I);
1189 case Instruction::ZExt:
1190 return X86SelectZExt(I);
1191 case Instruction::Br:
1192 return X86SelectBranch(I);
1193 case Instruction::Call:
1194 return X86SelectCall(I);
1195 case Instruction::LShr:
1196 case Instruction::AShr:
1197 case Instruction::Shl:
1198 return X86SelectShift(I);
1199 case Instruction::Select:
1200 return X86SelectSelect(I);
1201 case Instruction::Trunc:
1202 return X86SelectTrunc(I);
1203 case Instruction::FPExt:
1204 return X86SelectFPExt(I);
1205 case Instruction::FPTrunc:
1206 return X86SelectFPTrunc(I);
1212 unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
1214 if (!isTypeLegal(C->getType(), VT))
1217 // Get opcode and regclass of the output for the given load instruction.
1219 const TargetRegisterClass *RC = NULL;
1220 switch (VT.getSimpleVT()) {
1221 default: return false;
1224 RC = X86::GR8RegisterClass;
1228 RC = X86::GR16RegisterClass;
1232 RC = X86::GR32RegisterClass;
1235 // Must be in x86-64 mode.
1237 RC = X86::GR64RegisterClass;
1240 if (Subtarget->hasSSE1()) {
1242 RC = X86::FR32RegisterClass;
1244 Opc = X86::LD_Fp32m;
1245 RC = X86::RFP32RegisterClass;
1249 if (Subtarget->hasSSE2()) {
1251 RC = X86::FR64RegisterClass;
1253 Opc = X86::LD_Fp64m;
1254 RC = X86::RFP64RegisterClass;
1258 // No f80 support yet.
1262 // Materialize addresses with LEA instructions.
1263 if (isa<GlobalValue>(C)) {
1265 if (X86SelectAddress(C, AM, false)) {
1266 if (TLI.getPointerTy() == MVT::i32)
1270 unsigned ResultReg = createResultReg(RC);
1271 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
1277 // MachineConstantPool wants an explicit alignment.
1278 unsigned Align = TD.getPreferredTypeAlignmentShift(C->getType());
1280 // Alignment of vector types. FIXME!
1281 Align = TD.getABITypeSize(C->getType());
1282 Align = Log2_64(Align);
1285 // x86-32 PIC requires a PIC base register for constant pools.
1286 unsigned PICBase = 0;
1287 if (TM.getRelocationModel() == Reloc::PIC_ &&
1288 !Subtarget->is64Bit())
1289 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1291 // Create the load from the constant pool.
1292 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1293 unsigned ResultReg = createResultReg(RC);
1294 addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset,
1300 unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
1301 // Fail on dynamic allocas. At this point, getRegForValue has already
1302 // checked its CSE maps, so if we're here trying to handle a dynamic
1303 // alloca, we're not going to succeed. X86SelectAddress has a
1304 // check for dynamic allocas, because it's called directly from
1305 // various places, but TargetMaterializeAlloca also needs a check
1306 // in order to avoid recursion between getRegForValue,
1307 // X86SelectAddrss, and TargetMaterializeAlloca.
1308 if (!StaticAllocaMap.count(C))
1312 if (!X86SelectAddress(C, AM, false))
1314 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1315 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1316 unsigned ResultReg = createResultReg(RC);
1317 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
1322 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1323 MachineModuleInfo *mmi,
1324 DenseMap<const Value *, unsigned> &vm,
1325 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1326 DenseMap<const AllocaInst *, int> &am
1328 , SmallSet<Instruction*, 8> &cil
1331 return new X86FastISel(mf, mmi, vm, bm, am