1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/IntrinsicInst.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/Support/CallSite.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/GetElementPtrTypeIterator.h"
33 #include "llvm/Target/TargetOptions.h"
38 class X86FastISel : public FastISel {
39 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
40 /// make the right decision when generating code for different targets.
41 const X86Subtarget *Subtarget;
43 /// StackPtr - Register used as the stack pointer.
47 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
48 /// floating point ops.
49 /// When SSE is available, use it for f32 operations.
50 /// When SSE2 is available, use it for f64 operations.
55 explicit X86FastISel(MachineFunction &mf,
56 DenseMap<const Value *, unsigned> &vm,
57 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
58 DenseMap<const AllocaInst *, int> &am,
59 std::vector<std::pair<MachineInstr*, unsigned> > &pn
61 , SmallSet<const Instruction *, 8> &cil
64 : FastISel(mf, vm, bm, am, pn
69 Subtarget = &TM.getSubtarget<X86Subtarget>();
70 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
71 X86ScalarSSEf64 = Subtarget->hasSSE2();
72 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 virtual bool TargetSelectInstruction(const Instruction *I);
77 #include "X86GenFastISel.inc"
80 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT);
82 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
84 bool X86FastEmitStore(EVT VT, const Value *Val,
85 const X86AddressMode &AM);
86 bool X86FastEmitStore(EVT VT, unsigned Val,
87 const X86AddressMode &AM);
89 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
92 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
93 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
95 bool X86SelectLoad(const Instruction *I);
97 bool X86SelectStore(const Instruction *I);
99 bool X86SelectCmp(const Instruction *I);
101 bool X86SelectZExt(const Instruction *I);
103 bool X86SelectBranch(const Instruction *I);
105 bool X86SelectShift(const Instruction *I);
107 bool X86SelectSelect(const Instruction *I);
109 bool X86SelectTrunc(const Instruction *I);
111 bool X86SelectFPExt(const Instruction *I);
112 bool X86SelectFPTrunc(const Instruction *I);
114 bool X86SelectExtractValue(const Instruction *I);
116 bool X86VisitIntrinsicCall(const IntrinsicInst &I);
117 bool X86SelectCall(const Instruction *I);
119 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false);
121 const X86InstrInfo *getInstrInfo() const {
122 return getTargetMachine()->getInstrInfo();
124 const X86TargetMachine *getTargetMachine() const {
125 return static_cast<const X86TargetMachine *>(&TM);
128 unsigned TargetMaterializeConstant(const Constant *C);
130 unsigned TargetMaterializeAlloca(const AllocaInst *C);
132 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
133 /// computed in an SSE register, not on the X87 floating point stack.
134 bool isScalarFPTypeInSSEReg(EVT VT) const {
135 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
136 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
139 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false);
142 } // end anonymous namespace.
144 bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) {
145 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
146 if (VT == MVT::Other || !VT.isSimple())
147 // Unhandled type. Halt "fast" selection and bail.
150 // For now, require SSE/SSE2 for performing floating-point operations,
151 // since x87 requires additional work.
152 if (VT == MVT::f64 && !X86ScalarSSEf64)
154 if (VT == MVT::f32 && !X86ScalarSSEf32)
156 // Similarly, no f80 support yet.
159 // We only handle legal types. For example, on x86-32 the instruction
160 // selector contains all of the 64-bit instructions from x86-64,
161 // under the assumption that i64 won't be used if the target doesn't
163 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
166 #include "X86GenCallingConv.inc"
168 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
170 CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC,
172 if (Subtarget->is64Bit()) {
173 if (CC == CallingConv::GHC)
174 return CC_X86_64_GHC;
175 else if (Subtarget->isTargetWin64())
176 return CC_X86_Win64_C;
181 if (CC == CallingConv::X86_FastCall)
182 return CC_X86_32_FastCall;
183 else if (CC == CallingConv::X86_ThisCall)
184 return CC_X86_32_ThisCall;
185 else if (CC == CallingConv::Fast)
186 return CC_X86_32_FastCC;
187 else if (CC == CallingConv::GHC)
188 return CC_X86_32_GHC;
193 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
194 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
195 /// Return true and the result register by reference if it is possible.
196 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM,
197 unsigned &ResultReg) {
198 // Get opcode and regclass of the output for the given load instruction.
200 const TargetRegisterClass *RC = NULL;
201 switch (VT.getSimpleVT().SimpleTy) {
202 default: return false;
206 RC = X86::GR8RegisterClass;
210 RC = X86::GR16RegisterClass;
214 RC = X86::GR32RegisterClass;
217 // Must be in x86-64 mode.
219 RC = X86::GR64RegisterClass;
222 if (Subtarget->hasSSE1()) {
224 RC = X86::FR32RegisterClass;
227 RC = X86::RFP32RegisterClass;
231 if (Subtarget->hasSSE2()) {
233 RC = X86::FR64RegisterClass;
236 RC = X86::RFP64RegisterClass;
240 // No f80 support yet.
244 ResultReg = createResultReg(RC);
245 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
249 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
250 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
251 /// and a displacement offset, or a GlobalAddress,
252 /// i.e. V. Return true if it is possible.
254 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val,
255 const X86AddressMode &AM) {
256 // Get opcode and regclass of the output for the given store instruction.
258 switch (VT.getSimpleVT().SimpleTy) {
259 case MVT::f80: // No f80 support yet.
260 default: return false;
262 // Mask out all but lowest bit.
263 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
265 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
268 // FALLTHROUGH, handling i1 as i8.
269 case MVT::i8: Opc = X86::MOV8mr; break;
270 case MVT::i16: Opc = X86::MOV16mr; break;
271 case MVT::i32: Opc = X86::MOV32mr; break;
272 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
274 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
277 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
281 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
285 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
286 const X86AddressMode &AM) {
287 // Handle 'null' like i32/i64 0.
288 if (isa<ConstantPointerNull>(Val))
289 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext()));
291 // If this is a store of a simple constant, fold the constant into the store.
292 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
295 switch (VT.getSimpleVT().SimpleTy) {
297 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
298 case MVT::i8: Opc = X86::MOV8mi; break;
299 case MVT::i16: Opc = X86::MOV16mi; break;
300 case MVT::i32: Opc = X86::MOV32mi; break;
302 // Must be a 32-bit sign extended value.
303 if ((int)CI->getSExtValue() == CI->getSExtValue())
304 Opc = X86::MOV64mi32;
309 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
310 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
316 unsigned ValReg = getRegForValue(Val);
320 return X86FastEmitStore(VT, ValReg, AM);
323 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
324 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
325 /// ISD::SIGN_EXTEND).
326 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
327 unsigned Src, EVT SrcVT,
328 unsigned &ResultReg) {
329 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
330 Src, /*TODO: Kill=*/false);
339 /// X86SelectAddress - Attempt to fill in an address from the given value.
341 bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
342 const User *U = NULL;
343 unsigned Opcode = Instruction::UserOp1;
344 if (const Instruction *I = dyn_cast<Instruction>(V)) {
345 Opcode = I->getOpcode();
347 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
348 Opcode = C->getOpcode();
352 if (const PointerType *Ty = dyn_cast<PointerType>(V->getType()))
353 if (Ty->getAddressSpace() > 255)
354 // Fast instruction selection doesn't support pointers through %fs or %gs
359 case Instruction::BitCast:
360 // Look past bitcasts.
361 return X86SelectAddress(U->getOperand(0), AM);
363 case Instruction::IntToPtr:
364 // Look past no-op inttoptrs.
365 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
366 return X86SelectAddress(U->getOperand(0), AM);
369 case Instruction::PtrToInt:
370 // Look past no-op ptrtoints.
371 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
372 return X86SelectAddress(U->getOperand(0), AM);
375 case Instruction::Alloca: {
376 // Do static allocas.
377 const AllocaInst *A = cast<AllocaInst>(V);
378 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
379 if (SI != StaticAllocaMap.end()) {
380 AM.BaseType = X86AddressMode::FrameIndexBase;
381 AM.Base.FrameIndex = SI->second;
387 case Instruction::Add: {
388 // Adds of constants are common and easy enough.
389 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
390 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
391 // They have to fit in the 32-bit signed displacement field though.
392 if (isInt<32>(Disp)) {
393 AM.Disp = (uint32_t)Disp;
394 return X86SelectAddress(U->getOperand(0), AM);
400 case Instruction::GetElementPtr: {
401 X86AddressMode SavedAM = AM;
403 // Pattern-match simple GEPs.
404 uint64_t Disp = (int32_t)AM.Disp;
405 unsigned IndexReg = AM.IndexReg;
406 unsigned Scale = AM.Scale;
407 gep_type_iterator GTI = gep_type_begin(U);
408 // Iterate through the indices, folding what we can. Constants can be
409 // folded, and one dynamic index can be handled, if the scale is supported.
410 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
411 i != e; ++i, ++GTI) {
412 const Value *Op = *i;
413 if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
414 const StructLayout *SL = TD.getStructLayout(STy);
415 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
416 Disp += SL->getElementOffset(Idx);
418 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
419 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
420 // Constant-offset addressing.
421 Disp += CI->getSExtValue() * S;
422 } else if (IndexReg == 0 &&
423 (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
424 (S == 1 || S == 2 || S == 4 || S == 8)) {
425 // Scaled-index addressing.
427 IndexReg = getRegForGEPIndex(Op).first;
432 goto unsupported_gep;
435 // Check for displacement overflow.
436 if (!isInt<32>(Disp))
438 // Ok, the GEP indices were covered by constant-offset and scaled-index
439 // addressing. Update the address state and move on to examining the base.
440 AM.IndexReg = IndexReg;
442 AM.Disp = (uint32_t)Disp;
443 if (X86SelectAddress(U->getOperand(0), AM))
446 // If we couldn't merge the sub value into this addr mode, revert back to
447 // our address and just match the value instead of completely failing.
451 // Ok, the GEP indices weren't all covered.
456 // Handle constant address.
457 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
458 // Can't handle alternate code models yet.
459 if (TM.getCodeModel() != CodeModel::Small)
462 // RIP-relative addresses can't have additional register operands.
463 if (Subtarget->isPICStyleRIPRel() &&
464 (AM.Base.Reg != 0 || AM.IndexReg != 0))
467 // Can't handle TLS yet.
468 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
469 if (GVar->isThreadLocal())
472 // Okay, we've committed to selecting this global. Set up the basic address.
475 // Allow the subtarget to classify the global.
476 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM);
478 // If this reference is relative to the pic base, set it now.
479 if (isGlobalRelativeToPICBase(GVFlags)) {
480 // FIXME: How do we know Base.Reg is free??
481 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
484 // Unless the ABI requires an extra load, return a direct reference to
486 if (!isGlobalStubReference(GVFlags)) {
487 if (Subtarget->isPICStyleRIPRel()) {
488 // Use rip-relative addressing if we can. Above we verified that the
489 // base and index registers are unused.
490 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
491 AM.Base.Reg = X86::RIP;
493 AM.GVOpFlags = GVFlags;
497 // Ok, we need to do a load from a stub. If we've already loaded from this
498 // stub, reuse the loaded pointer, otherwise emit the load now.
499 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
501 if (I != LocalValueMap.end() && I->second != 0) {
504 // Issue load from stub.
506 const TargetRegisterClass *RC = NULL;
507 X86AddressMode StubAM;
508 StubAM.Base.Reg = AM.Base.Reg;
510 StubAM.GVOpFlags = GVFlags;
512 if (TLI.getPointerTy() == MVT::i64) {
514 RC = X86::GR64RegisterClass;
516 if (Subtarget->isPICStyleRIPRel())
517 StubAM.Base.Reg = X86::RIP;
520 RC = X86::GR32RegisterClass;
523 LoadReg = createResultReg(RC);
524 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM);
526 // Prevent loading GV stub multiple times in same MBB.
527 LocalValueMap[V] = LoadReg;
530 // Now construct the final address. Note that the Disp, Scale,
531 // and Index values may already be set here.
532 AM.Base.Reg = LoadReg;
537 // If all else fails, try to materialize the value in a register.
538 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
539 if (AM.Base.Reg == 0) {
540 AM.Base.Reg = getRegForValue(V);
541 return AM.Base.Reg != 0;
543 if (AM.IndexReg == 0) {
544 assert(AM.Scale == 1 && "Scale with no index!");
545 AM.IndexReg = getRegForValue(V);
546 return AM.IndexReg != 0;
553 /// X86SelectCallAddress - Attempt to fill in an address from the given value.
555 bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
556 const User *U = NULL;
557 unsigned Opcode = Instruction::UserOp1;
558 if (const Instruction *I = dyn_cast<Instruction>(V)) {
559 Opcode = I->getOpcode();
561 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
562 Opcode = C->getOpcode();
568 case Instruction::BitCast:
569 // Look past bitcasts.
570 return X86SelectCallAddress(U->getOperand(0), AM);
572 case Instruction::IntToPtr:
573 // Look past no-op inttoptrs.
574 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
575 return X86SelectCallAddress(U->getOperand(0), AM);
578 case Instruction::PtrToInt:
579 // Look past no-op ptrtoints.
580 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
581 return X86SelectCallAddress(U->getOperand(0), AM);
585 // Handle constant address.
586 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
587 // Can't handle alternate code models yet.
588 if (TM.getCodeModel() != CodeModel::Small)
591 // RIP-relative addresses can't have additional register operands.
592 if (Subtarget->isPICStyleRIPRel() &&
593 (AM.Base.Reg != 0 || AM.IndexReg != 0))
596 // Can't handle TLS or DLLImport.
597 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
598 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage())
601 // Okay, we've committed to selecting this global. Set up the basic address.
604 // No ABI requires an extra load for anything other than DLLImport, which
605 // we rejected above. Return a direct reference to the global.
606 if (Subtarget->isPICStyleRIPRel()) {
607 // Use rip-relative addressing if we can. Above we verified that the
608 // base and index registers are unused.
609 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
610 AM.Base.Reg = X86::RIP;
611 } else if (Subtarget->isPICStyleStubPIC()) {
612 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
613 } else if (Subtarget->isPICStyleGOT()) {
614 AM.GVOpFlags = X86II::MO_GOTOFF;
620 // If all else fails, try to materialize the value in a register.
621 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
622 if (AM.Base.Reg == 0) {
623 AM.Base.Reg = getRegForValue(V);
624 return AM.Base.Reg != 0;
626 if (AM.IndexReg == 0) {
627 assert(AM.Scale == 1 && "Scale with no index!");
628 AM.IndexReg = getRegForValue(V);
629 return AM.IndexReg != 0;
637 /// X86SelectStore - Select and emit code to implement store instructions.
638 bool X86FastISel::X86SelectStore(const Instruction *I) {
640 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true))
644 if (!X86SelectAddress(I->getOperand(1), AM))
647 return X86FastEmitStore(VT, I->getOperand(0), AM);
650 /// X86SelectLoad - Select and emit code to implement load instructions.
652 bool X86FastISel::X86SelectLoad(const Instruction *I) {
654 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true))
658 if (!X86SelectAddress(I->getOperand(0), AM))
661 unsigned ResultReg = 0;
662 if (X86FastEmitLoad(VT, AM, ResultReg)) {
663 UpdateValueMap(I, ResultReg);
669 static unsigned X86ChooseCmpOpcode(EVT VT) {
670 switch (VT.getSimpleVT().SimpleTy) {
672 case MVT::i8: return X86::CMP8rr;
673 case MVT::i16: return X86::CMP16rr;
674 case MVT::i32: return X86::CMP32rr;
675 case MVT::i64: return X86::CMP64rr;
676 case MVT::f32: return X86::UCOMISSrr;
677 case MVT::f64: return X86::UCOMISDrr;
681 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
682 /// of the comparison, return an opcode that works for the compare (e.g.
683 /// CMP32ri) otherwise return 0.
684 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
685 switch (VT.getSimpleVT().SimpleTy) {
686 // Otherwise, we can't fold the immediate into this comparison.
688 case MVT::i8: return X86::CMP8ri;
689 case MVT::i16: return X86::CMP16ri;
690 case MVT::i32: return X86::CMP32ri;
692 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
694 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
695 return X86::CMP64ri32;
700 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1,
702 unsigned Op0Reg = getRegForValue(Op0);
703 if (Op0Reg == 0) return false;
705 // Handle 'null' like i32/i64 0.
706 if (isa<ConstantPointerNull>(Op1))
707 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
709 // We have two options: compare with register or immediate. If the RHS of
710 // the compare is an immediate that we can fold into this compare, use
711 // CMPri, otherwise use CMPrr.
712 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
713 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
714 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
715 .addImm(Op1C->getSExtValue());
720 unsigned CompareOpc = X86ChooseCmpOpcode(VT);
721 if (CompareOpc == 0) return false;
723 unsigned Op1Reg = getRegForValue(Op1);
724 if (Op1Reg == 0) return false;
725 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
730 bool X86FastISel::X86SelectCmp(const Instruction *I) {
731 const CmpInst *CI = cast<CmpInst>(I);
734 if (!isTypeLegal(I->getOperand(0)->getType(), VT))
737 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
739 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
740 switch (CI->getPredicate()) {
741 case CmpInst::FCMP_OEQ: {
742 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
745 unsigned EReg = createResultReg(&X86::GR8RegClass);
746 unsigned NPReg = createResultReg(&X86::GR8RegClass);
747 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
748 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
750 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
751 UpdateValueMap(I, ResultReg);
754 case CmpInst::FCMP_UNE: {
755 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
758 unsigned NEReg = createResultReg(&X86::GR8RegClass);
759 unsigned PReg = createResultReg(&X86::GR8RegClass);
760 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
761 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
762 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
763 UpdateValueMap(I, ResultReg);
766 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
767 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
768 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
769 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
770 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
771 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
772 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
773 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
774 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
775 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
776 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
777 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
779 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
780 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
781 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
782 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
783 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
784 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
785 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
786 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
787 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
788 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
793 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
797 // Emit a compare of Op0/Op1.
798 if (!X86FastEmitCompare(Op0, Op1, VT))
801 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
802 UpdateValueMap(I, ResultReg);
806 bool X86FastISel::X86SelectZExt(const Instruction *I) {
807 // Handle zero-extension from i1 to i8, which is common.
808 if (I->getType()->isIntegerTy(8) &&
809 I->getOperand(0)->getType()->isIntegerTy(1)) {
810 unsigned ResultReg = getRegForValue(I->getOperand(0));
811 if (ResultReg == 0) return false;
812 // Set the high bits to zero.
813 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false);
814 if (ResultReg == 0) return false;
815 UpdateValueMap(I, ResultReg);
823 bool X86FastISel::X86SelectBranch(const Instruction *I) {
824 // Unconditional branches are selected by tablegen-generated code.
825 // Handle a conditional branch.
826 const BranchInst *BI = cast<BranchInst>(I);
827 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
828 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
830 // Fold the common case of a conditional branch with a comparison.
831 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
832 if (CI->hasOneUse()) {
833 EVT VT = TLI.getValueType(CI->getOperand(0)->getType());
835 // Try to take advantage of fallthrough opportunities.
836 CmpInst::Predicate Predicate = CI->getPredicate();
837 if (MBB->isLayoutSuccessor(TrueMBB)) {
838 std::swap(TrueMBB, FalseMBB);
839 Predicate = CmpInst::getInversePredicate(Predicate);
842 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
843 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
846 case CmpInst::FCMP_OEQ:
847 std::swap(TrueMBB, FalseMBB);
848 Predicate = CmpInst::FCMP_UNE;
850 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
851 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
852 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
853 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
854 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
855 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
856 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
857 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
858 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
859 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
860 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
861 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
862 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
864 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
865 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
866 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
867 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
868 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
869 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
870 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
871 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
872 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
873 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
878 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
882 // Emit a compare of the LHS and RHS, setting the flags.
883 if (!X86FastEmitCompare(Op0, Op1, VT))
886 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
888 if (Predicate == CmpInst::FCMP_UNE) {
889 // X86 requires a second branch to handle UNE (and OEQ,
890 // which is mapped to UNE above).
891 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
894 FastEmitBranch(FalseMBB, DL);
895 MBB->addSuccessor(TrueMBB);
898 } else if (ExtractValueInst *EI =
899 dyn_cast<ExtractValueInst>(BI->getCondition())) {
900 // Check to see if the branch instruction is from an "arithmetic with
901 // overflow" intrinsic. The main way these intrinsics are used is:
903 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
904 // %sum = extractvalue { i32, i1 } %t, 0
905 // %obit = extractvalue { i32, i1 } %t, 1
906 // br i1 %obit, label %overflow, label %normal
908 // The %sum and %obit are converted in an ADD and a SETO/SETB before
909 // reaching the branch. Therefore, we search backwards through the MBB
910 // looking for the SETO/SETB instruction. If an instruction modifies the
911 // EFLAGS register before we reach the SETO/SETB instruction, then we can't
912 // convert the branch into a JO/JB instruction.
913 if (const IntrinsicInst *CI =
914 dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
915 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
916 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
917 const MachineInstr *SetMI = 0;
918 unsigned Reg = lookUpRegForValue(EI);
920 for (MachineBasicBlock::const_reverse_iterator
921 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
922 const MachineInstr &MI = *RI;
924 if (MI.definesRegister(Reg)) {
925 unsigned Src, Dst, SrcSR, DstSR;
927 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
936 const TargetInstrDesc &TID = MI.getDesc();
937 if (TID.hasUnmodeledSideEffects() ||
938 TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
943 unsigned OpCode = SetMI->getOpcode();
945 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
946 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
947 X86::JO_4 : X86::JB_4))
949 FastEmitBranch(FalseMBB, DL);
950 MBB->addSuccessor(TrueMBB);
958 // Otherwise do a clumsy setcc and re-test it.
959 unsigned OpReg = getRegForValue(BI->getCondition());
960 if (OpReg == 0) return false;
962 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
963 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
964 FastEmitBranch(FalseMBB, DL);
965 MBB->addSuccessor(TrueMBB);
969 bool X86FastISel::X86SelectShift(const Instruction *I) {
970 unsigned CReg = 0, OpReg = 0, OpImm = 0;
971 const TargetRegisterClass *RC = NULL;
972 if (I->getType()->isIntegerTy(8)) {
974 RC = &X86::GR8RegClass;
975 switch (I->getOpcode()) {
976 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
977 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
978 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
979 default: return false;
981 } else if (I->getType()->isIntegerTy(16)) {
983 RC = &X86::GR16RegClass;
984 switch (I->getOpcode()) {
985 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
986 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
987 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
988 default: return false;
990 } else if (I->getType()->isIntegerTy(32)) {
992 RC = &X86::GR32RegClass;
993 switch (I->getOpcode()) {
994 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
995 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
996 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
997 default: return false;
999 } else if (I->getType()->isIntegerTy(64)) {
1001 RC = &X86::GR64RegClass;
1002 switch (I->getOpcode()) {
1003 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
1004 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
1005 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
1006 default: return false;
1012 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1013 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1016 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1017 if (Op0Reg == 0) return false;
1019 // Fold immediate in shl(x,3).
1020 if (const ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
1021 unsigned ResultReg = createResultReg(RC);
1022 BuildMI(MBB, DL, TII.get(OpImm),
1023 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
1024 UpdateValueMap(I, ResultReg);
1028 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1029 if (Op1Reg == 0) return false;
1030 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC, DL);
1032 // The shift instruction uses X86::CL. If we defined a super-register
1033 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
1034 // we're doing here.
1035 if (CReg != X86::CL)
1036 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL)
1037 .addReg(CReg).addImm(X86::sub_8bit);
1039 unsigned ResultReg = createResultReg(RC);
1040 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
1041 UpdateValueMap(I, ResultReg);
1045 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1046 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1047 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1051 const TargetRegisterClass *RC = NULL;
1052 if (VT.getSimpleVT() == MVT::i16) {
1053 Opc = X86::CMOVE16rr;
1054 RC = &X86::GR16RegClass;
1055 } else if (VT.getSimpleVT() == MVT::i32) {
1056 Opc = X86::CMOVE32rr;
1057 RC = &X86::GR32RegClass;
1058 } else if (VT.getSimpleVT() == MVT::i64) {
1059 Opc = X86::CMOVE64rr;
1060 RC = &X86::GR64RegClass;
1065 unsigned Op0Reg = getRegForValue(I->getOperand(0));
1066 if (Op0Reg == 0) return false;
1067 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1068 if (Op1Reg == 0) return false;
1069 unsigned Op2Reg = getRegForValue(I->getOperand(2));
1070 if (Op2Reg == 0) return false;
1072 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
1073 unsigned ResultReg = createResultReg(RC);
1074 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
1075 UpdateValueMap(I, ResultReg);
1079 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
1080 // fpext from float to double.
1081 if (Subtarget->hasSSE2() &&
1082 I->getType()->isDoubleTy()) {
1083 const Value *V = I->getOperand(0);
1084 if (V->getType()->isFloatTy()) {
1085 unsigned OpReg = getRegForValue(V);
1086 if (OpReg == 0) return false;
1087 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1088 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
1089 UpdateValueMap(I, ResultReg);
1097 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
1098 if (Subtarget->hasSSE2()) {
1099 if (I->getType()->isFloatTy()) {
1100 const Value *V = I->getOperand(0);
1101 if (V->getType()->isDoubleTy()) {
1102 unsigned OpReg = getRegForValue(V);
1103 if (OpReg == 0) return false;
1104 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1105 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
1106 UpdateValueMap(I, ResultReg);
1115 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
1116 if (Subtarget->is64Bit())
1117 // All other cases should be handled by the tblgen generated code.
1119 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1120 EVT DstVT = TLI.getValueType(I->getType());
1122 // This code only handles truncation to byte right now.
1123 if (DstVT != MVT::i8 && DstVT != MVT::i1)
1124 // All other cases should be handled by the tblgen generated code.
1126 if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
1127 // All other cases should be handled by the tblgen generated code.
1130 unsigned InputReg = getRegForValue(I->getOperand(0));
1132 // Unhandled operand. Halt "fast" selection and bail.
1135 // First issue a copy to GR16_ABCD or GR32_ABCD.
1136 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
1137 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1138 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1139 unsigned CopyReg = createResultReg(CopyRC);
1140 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1142 // Then issue an extract_subreg.
1143 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1144 CopyReg, /*Kill=*/true,
1149 UpdateValueMap(I, ResultReg);
1153 bool X86FastISel::X86SelectExtractValue(const Instruction *I) {
1154 const ExtractValueInst *EI = cast<ExtractValueInst>(I);
1155 const Value *Agg = EI->getAggregateOperand();
1157 if (const IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1158 switch (CI->getIntrinsicID()) {
1160 case Intrinsic::sadd_with_overflow:
1161 case Intrinsic::uadd_with_overflow:
1162 // Cheat a little. We know that the registers for "add" and "seto" are
1163 // allocated sequentially. However, we only keep track of the register
1164 // for "add" in the value map. Use extractvalue's index to get the
1165 // correct register for "seto".
1166 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1174 bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) {
1175 // FIXME: Handle more intrinsics.
1176 switch (I.getIntrinsicID()) {
1177 default: return false;
1178 case Intrinsic::stackprotector: {
1179 // Emit code inline code to store the stack guard onto the stack.
1180 EVT PtrTy = TLI.getPointerTy();
1182 const Value *Op1 = I.getOperand(1); // The guard's value.
1183 const AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
1185 // Grab the frame index.
1187 if (!X86SelectAddress(Slot, AM)) return false;
1189 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false;
1193 case Intrinsic::objectsize: {
1194 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2));
1195 const Type *Ty = I.getCalledFunction()->getReturnType();
1197 assert(CI && "Non-constant type in Intrinsic::objectsize?");
1200 if (!isTypeLegal(Ty, VT))
1206 else if (VT == MVT::i64)
1211 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1212 BuildMI(MBB, DL, TII.get(OpC), ResultReg).
1213 addImm(CI->isZero() ? -1ULL : 0);
1214 UpdateValueMap(&I, ResultReg);
1217 case Intrinsic::dbg_declare: {
1218 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I);
1220 assert(DI->getAddress() && "Null address should be checked earlier!");
1221 if (!X86SelectAddress(DI->getAddress(), AM))
1223 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1224 // FIXME may need to add RegState::Debug to any registers produced,
1225 // although ESP/EBP should be the only ones at the moment.
1226 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0).
1227 addMetadata(DI->getVariable());
1230 case Intrinsic::trap: {
1231 BuildMI(MBB, DL, TII.get(X86::TRAP));
1234 case Intrinsic::sadd_with_overflow:
1235 case Intrinsic::uadd_with_overflow: {
1236 // Replace "add with overflow" intrinsics with an "add" instruction followed
1237 // by a seto/setc instruction. Later on, when the "extractvalue"
1238 // instructions are encountered, we use the fact that two registers were
1239 // created sequentially to get the correct registers for the "sum" and the
1241 const Function *Callee = I.getCalledFunction();
1243 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1246 if (!isTypeLegal(RetTy, VT))
1249 const Value *Op1 = I.getOperand(1);
1250 const Value *Op2 = I.getOperand(2);
1251 unsigned Reg1 = getRegForValue(Op1);
1252 unsigned Reg2 = getRegForValue(Op2);
1254 if (Reg1 == 0 || Reg2 == 0)
1255 // FIXME: Handle values *not* in registers.
1261 else if (VT == MVT::i64)
1266 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1267 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1268 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1270 // If the add with overflow is an intra-block value then we just want to
1271 // create temporaries for it like normal. If it is a cross-block value then
1272 // UpdateValueMap will return the cross-block register used. Since we
1273 // *really* want the value to be live in the register pair known by
1274 // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1275 // the cross block case. In the non-cross-block case, we should just make
1276 // another register for the value.
1277 if (DestReg1 != ResultReg)
1278 ResultReg = DestReg1+1;
1280 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1282 unsigned Opc = X86::SETBr;
1283 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1285 BuildMI(MBB, DL, TII.get(Opc), ResultReg);
1291 bool X86FastISel::X86SelectCall(const Instruction *I) {
1292 const CallInst *CI = cast<CallInst>(I);
1293 const Value *Callee = I->getOperand(0);
1295 // Can't handle inline asm yet.
1296 if (isa<InlineAsm>(Callee))
1299 // Handle intrinsic calls.
1300 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1301 return X86VisitIntrinsicCall(*II);
1303 // Handle only C and fastcc calling conventions for now.
1304 ImmutableCallSite CS(CI);
1305 CallingConv::ID CC = CS.getCallingConv();
1306 if (CC != CallingConv::C &&
1307 CC != CallingConv::Fast &&
1308 CC != CallingConv::X86_FastCall)
1311 // fastcc with -tailcallopt is intended to provide a guaranteed
1312 // tail call optimization. Fastisel doesn't know how to do that.
1313 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
1316 // Let SDISel handle vararg functions.
1317 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1318 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1319 if (FTy->isVarArg())
1322 // Fast-isel doesn't know about callee-pop yet.
1323 if (Subtarget->IsCalleePop(FTy->isVarArg(), CC))
1326 // Handle *simple* calls for now.
1327 const Type *RetTy = CS.getType();
1329 if (RetTy->isVoidTy())
1330 RetVT = MVT::isVoid;
1331 else if (!isTypeLegal(RetTy, RetVT, true))
1334 // Materialize callee address in a register. FIXME: GV address can be
1335 // handled with a CALLpcrel32 instead.
1336 X86AddressMode CalleeAM;
1337 if (!X86SelectCallAddress(Callee, CalleeAM))
1339 unsigned CalleeOp = 0;
1340 const GlobalValue *GV = 0;
1341 if (CalleeAM.GV != 0) {
1343 } else if (CalleeAM.Base.Reg != 0) {
1344 CalleeOp = CalleeAM.Base.Reg;
1348 // Allow calls which produce i1 results.
1349 bool AndToI1 = false;
1350 if (RetVT == MVT::i1) {
1355 // Deal with call operands first.
1356 SmallVector<const Value *, 8> ArgVals;
1357 SmallVector<unsigned, 8> Args;
1358 SmallVector<EVT, 8> ArgVTs;
1359 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1360 Args.reserve(CS.arg_size());
1361 ArgVals.reserve(CS.arg_size());
1362 ArgVTs.reserve(CS.arg_size());
1363 ArgFlags.reserve(CS.arg_size());
1364 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1366 unsigned Arg = getRegForValue(*i);
1369 ISD::ArgFlagsTy Flags;
1370 unsigned AttrInd = i - CS.arg_begin() + 1;
1371 if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1373 if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1376 // FIXME: Only handle *easy* calls for now.
1377 if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1378 CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1379 CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1380 CS.paramHasAttr(AttrInd, Attribute::ByVal))
1383 const Type *ArgTy = (*i)->getType();
1385 if (!isTypeLegal(ArgTy, ArgVT))
1387 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1388 Flags.setOrigAlign(OriginalAlignment);
1390 Args.push_back(Arg);
1391 ArgVals.push_back(*i);
1392 ArgVTs.push_back(ArgVT);
1393 ArgFlags.push_back(Flags);
1396 // Analyze operands of the call, assigning locations to each operand.
1397 SmallVector<CCValAssign, 16> ArgLocs;
1398 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext());
1400 // Allocate shadow area for Win64
1401 if (Subtarget->isTargetWin64()) {
1402 CCInfo.AllocateStack(32, 8);
1405 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1407 // Get a count of how many bytes are to be pushed on the stack.
1408 unsigned NumBytes = CCInfo.getNextStackOffset();
1410 // Issue CALLSEQ_START
1411 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1412 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1414 // Process argument: walk the register/memloc assignments, inserting
1416 SmallVector<unsigned, 4> RegArgs;
1417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1418 CCValAssign &VA = ArgLocs[i];
1419 unsigned Arg = Args[VA.getValNo()];
1420 EVT ArgVT = ArgVTs[VA.getValNo()];
1422 // Promote the value if needed.
1423 switch (VA.getLocInfo()) {
1424 default: llvm_unreachable("Unknown loc info!");
1425 case CCValAssign::Full: break;
1426 case CCValAssign::SExt: {
1427 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1429 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1431 ArgVT = VA.getLocVT();
1434 case CCValAssign::ZExt: {
1435 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1437 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1439 ArgVT = VA.getLocVT();
1442 case CCValAssign::AExt: {
1443 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1446 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1449 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1452 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1453 ArgVT = VA.getLocVT();
1456 case CCValAssign::BCvt: {
1457 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(),
1458 ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false);
1459 assert(BC != 0 && "Failed to emit a bitcast!");
1461 ArgVT = VA.getLocVT();
1466 if (VA.isRegLoc()) {
1467 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1468 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1470 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1472 RegArgs.push_back(VA.getLocReg());
1474 unsigned LocMemOffset = VA.getLocMemOffset();
1476 AM.Base.Reg = StackPtr;
1477 AM.Disp = LocMemOffset;
1478 const Value *ArgVal = ArgVals[VA.getValNo()];
1480 // If this is a really simple value, emit this with the Value* version of
1481 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it
1482 // can cause us to reevaluate the argument.
1483 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1484 X86FastEmitStore(ArgVT, ArgVal, AM);
1486 X86FastEmitStore(ArgVT, Arg, AM);
1490 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1492 if (Subtarget->isPICStyleGOT()) {
1493 TargetRegisterClass *RC = X86::GR32RegisterClass;
1494 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1495 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC,
1497 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1502 MachineInstrBuilder MIB;
1504 // Register-indirect call.
1505 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r;
1506 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp);
1510 assert(GV && "Not a direct call");
1512 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
1514 // See if we need any target-specific flags on the GV operand.
1515 unsigned char OpFlags = 0;
1517 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1518 // external symbols most go through the PLT in PIC mode. If the symbol
1519 // has hidden or protected visibility, or if it is static or local, then
1520 // we don't need to use the PLT - we can directly call it.
1521 if (Subtarget->isTargetELF() &&
1522 TM.getRelocationModel() == Reloc::PIC_ &&
1523 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1524 OpFlags = X86II::MO_PLT;
1525 } else if (Subtarget->isPICStyleStubAny() &&
1526 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1527 Subtarget->getDarwinVers() < 9) {
1528 // PC-relative references to external symbols should go through $stub,
1529 // unless we're building with the leopard linker or later, which
1530 // automatically synthesizes these stubs.
1531 OpFlags = X86II::MO_DARWIN_STUB;
1535 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags);
1538 // Add an implicit use GOT pointer in EBX.
1539 if (Subtarget->isPICStyleGOT())
1540 MIB.addReg(X86::EBX);
1542 // Add implicit physical register uses to the call.
1543 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1544 MIB.addReg(RegArgs[i]);
1546 // Issue CALLSEQ_END
1547 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1548 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1550 // Now handle call return value (if any).
1551 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1552 SmallVector<CCValAssign, 16> RVLocs;
1553 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
1554 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1556 // Copy all of the result registers out of their specified physreg.
1557 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1558 EVT CopyVT = RVLocs[0].getValVT();
1559 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1560 TargetRegisterClass *SrcRC = DstRC;
1562 // If this is a call to a function that returns an fp value on the x87 fp
1563 // stack, but where we prefer to use the value in xmm registers, copy it
1564 // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1565 if ((RVLocs[0].getLocReg() == X86::ST0 ||
1566 RVLocs[0].getLocReg() == X86::ST1) &&
1567 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1569 SrcRC = X86::RSTRegisterClass;
1570 DstRC = X86::RFP80RegisterClass;
1573 unsigned ResultReg = createResultReg(DstRC);
1574 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1575 RVLocs[0].getLocReg(), DstRC, SrcRC, DL);
1576 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1578 if (CopyVT != RVLocs[0].getValVT()) {
1579 // Round the F80 the right size, which also moves to the appropriate xmm
1580 // register. This is accomplished by storing the F80 value in memory and
1581 // then loading it back. Ewww...
1582 EVT ResVT = RVLocs[0].getValVT();
1583 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1584 unsigned MemSize = ResVT.getSizeInBits()/8;
1585 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
1586 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1587 DstRC = ResVT == MVT::f32
1588 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1589 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1590 ResultReg = createResultReg(DstRC);
1591 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1595 // Mask out all but lowest bit for some call which produces an i1.
1596 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1598 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1599 ResultReg = AndResult;
1602 UpdateValueMap(I, ResultReg);
1610 X86FastISel::TargetSelectInstruction(const Instruction *I) {
1611 switch (I->getOpcode()) {
1613 case Instruction::Load:
1614 return X86SelectLoad(I);
1615 case Instruction::Store:
1616 return X86SelectStore(I);
1617 case Instruction::ICmp:
1618 case Instruction::FCmp:
1619 return X86SelectCmp(I);
1620 case Instruction::ZExt:
1621 return X86SelectZExt(I);
1622 case Instruction::Br:
1623 return X86SelectBranch(I);
1624 case Instruction::Call:
1625 return X86SelectCall(I);
1626 case Instruction::LShr:
1627 case Instruction::AShr:
1628 case Instruction::Shl:
1629 return X86SelectShift(I);
1630 case Instruction::Select:
1631 return X86SelectSelect(I);
1632 case Instruction::Trunc:
1633 return X86SelectTrunc(I);
1634 case Instruction::FPExt:
1635 return X86SelectFPExt(I);
1636 case Instruction::FPTrunc:
1637 return X86SelectFPTrunc(I);
1638 case Instruction::ExtractValue:
1639 return X86SelectExtractValue(I);
1640 case Instruction::IntToPtr: // Deliberate fall-through.
1641 case Instruction::PtrToInt: {
1642 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1643 EVT DstVT = TLI.getValueType(I->getType());
1644 if (DstVT.bitsGT(SrcVT))
1645 return X86SelectZExt(I);
1646 if (DstVT.bitsLT(SrcVT))
1647 return X86SelectTrunc(I);
1648 unsigned Reg = getRegForValue(I->getOperand(0));
1649 if (Reg == 0) return false;
1650 UpdateValueMap(I, Reg);
1658 unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) {
1660 if (!isTypeLegal(C->getType(), VT))
1663 // Get opcode and regclass of the output for the given load instruction.
1665 const TargetRegisterClass *RC = NULL;
1666 switch (VT.getSimpleVT().SimpleTy) {
1667 default: return false;
1670 RC = X86::GR8RegisterClass;
1674 RC = X86::GR16RegisterClass;
1678 RC = X86::GR32RegisterClass;
1681 // Must be in x86-64 mode.
1683 RC = X86::GR64RegisterClass;
1686 if (Subtarget->hasSSE1()) {
1688 RC = X86::FR32RegisterClass;
1690 Opc = X86::LD_Fp32m;
1691 RC = X86::RFP32RegisterClass;
1695 if (Subtarget->hasSSE2()) {
1697 RC = X86::FR64RegisterClass;
1699 Opc = X86::LD_Fp64m;
1700 RC = X86::RFP64RegisterClass;
1704 // No f80 support yet.
1708 // Materialize addresses with LEA instructions.
1709 if (isa<GlobalValue>(C)) {
1711 if (X86SelectAddress(C, AM)) {
1712 if (TLI.getPointerTy() == MVT::i32)
1716 unsigned ResultReg = createResultReg(RC);
1717 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1723 // MachineConstantPool wants an explicit alignment.
1724 unsigned Align = TD.getPrefTypeAlignment(C->getType());
1726 // Alignment of vector types. FIXME!
1727 Align = TD.getTypeAllocSize(C->getType());
1730 // x86-32 PIC requires a PIC base register for constant pools.
1731 unsigned PICBase = 0;
1732 unsigned char OpFlag = 0;
1733 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic
1734 OpFlag = X86II::MO_PIC_BASE_OFFSET;
1735 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1736 } else if (Subtarget->isPICStyleGOT()) {
1737 OpFlag = X86II::MO_GOTOFF;
1738 PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1739 } else if (Subtarget->isPICStyleRIPRel() &&
1740 TM.getCodeModel() == CodeModel::Small) {
1744 // Create the load from the constant pool.
1745 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1746 unsigned ResultReg = createResultReg(RC);
1747 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg),
1748 MCPOffset, PICBase, OpFlag);
1753 unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) {
1754 // Fail on dynamic allocas. At this point, getRegForValue has already
1755 // checked its CSE maps, so if we're here trying to handle a dynamic
1756 // alloca, we're not going to succeed. X86SelectAddress has a
1757 // check for dynamic allocas, because it's called directly from
1758 // various places, but TargetMaterializeAlloca also needs a check
1759 // in order to avoid recursion between getRegForValue,
1760 // X86SelectAddrss, and TargetMaterializeAlloca.
1761 if (!StaticAllocaMap.count(C))
1765 if (!X86SelectAddress(C, AM))
1767 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1768 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1769 unsigned ResultReg = createResultReg(RC);
1770 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1775 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1776 DenseMap<const Value *, unsigned> &vm,
1777 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1778 DenseMap<const AllocaInst *, int> &am,
1779 std::vector<std::pair<MachineInstr*, unsigned> > &pn
1781 , SmallSet<const Instruction *, 8> &cil
1784 return new X86FastISel(mf, vm, bm, am, pn