1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
11 // of the target-specific code is generated by tablegen in the file
12 // X86GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 class X86FastISel : public FastISel {
31 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
32 /// make the right decision when generating code for different targets.
33 const X86Subtarget *Subtarget;
36 explicit X86FastISel(MachineFunction &mf,
37 DenseMap<const Value *, unsigned> &vm,
38 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm)
39 : FastISel(mf, vm, bm) {
40 Subtarget = &TM.getSubtarget<X86Subtarget>();
43 virtual bool TargetSelectInstruction(Instruction *I);
45 #include "X86GenFastISel.inc"
48 bool X86SelectConstAddr(Value *V, unsigned &Op0);
50 bool X86SelectLoad(Instruction *I);
52 bool X86SelectStore(Instruction *I);
54 bool X86SelectCmp(Instruction *I);
56 bool X86SelectZExt(Instruction *I);
58 bool X86SelectBranch(Instruction *I);
60 unsigned TargetSelectConstantPoolLoad(Constant *C, MachineConstantPool* MCP);
63 /// X86SelectConstAddr - Select and emit code to materialize constant address.
65 bool X86FastISel::X86SelectConstAddr(Value *V,
67 // FIXME: Only GlobalAddress for now.
68 GlobalValue *GV = dyn_cast<GlobalValue>(V);
72 if (Subtarget->GVRequiresExtraLoad(GV, TM, false)) {
73 // Issue load from stub if necessary.
75 const TargetRegisterClass *RC = NULL;
76 if (TLI.getPointerTy() == MVT::i32) {
78 RC = X86::GR32RegisterClass;
81 RC = X86::GR64RegisterClass;
83 Op0 = createResultReg(RC);
86 addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
87 // Prevent loading GV stub multiple times in same MBB.
88 LocalValueMap[V] = Op0;
93 /// X86SelectStore - Select and emit code to implement store instructions.
94 bool X86FastISel::X86SelectStore(Instruction* I) {
95 MVT VT = MVT::getMVT(I->getOperand(0)->getType());
96 if (VT == MVT::Other || !VT.isSimple())
97 // Unhandled type. Halt "fast" selection and bail.
101 VT = TLI.getPointerTy();
102 // We only handle legal types. For example, on x86-32 the instruction
103 // selector contains all of the 64-bit instructions from x86-64,
104 // under the assumption that i64 won't be used if the target doesn't
106 if (!TLI.isTypeLegal(VT))
108 unsigned Op0 = getRegForValue(I->getOperand(0));
110 // Unhandled operand. Halt "fast" selection and bail.
113 Value *V = I->getOperand(1);
114 unsigned Op1 = getRegForValue(V);
116 // Handle constant load address.
117 if (!isa<Constant>(V) || !X86SelectConstAddr(V, Op1))
118 // Unhandled operand. Halt "fast" selection and bail.
122 // Get opcode and regclass of the output for the given load instruction.
124 const TargetRegisterClass *RC = NULL;
125 switch (VT.getSimpleVT()) {
126 default: return false;
129 RC = X86::GR8RegisterClass;
133 RC = X86::GR16RegisterClass;
137 RC = X86::GR32RegisterClass;
140 // Must be in x86-64 mode.
142 RC = X86::GR64RegisterClass;
145 if (Subtarget->hasSSE1()) {
147 RC = X86::FR32RegisterClass;
150 RC = X86::RFP32RegisterClass;
154 if (Subtarget->hasSSE2()) {
156 RC = X86::FR64RegisterClass;
159 RC = X86::RFP64RegisterClass;
164 RC = X86::RFP80RegisterClass;
170 // Address is in register.
173 AM.GV = cast<GlobalValue>(V);
174 addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Op0);
178 /// X86SelectLoad - Select and emit code to implement load instructions.
180 bool X86FastISel::X86SelectLoad(Instruction *I) {
181 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
182 if (VT == MVT::Other || !VT.isSimple())
183 // Unhandled type. Halt "fast" selection and bail.
187 VT = TLI.getPointerTy();
188 // We only handle legal types. For example, on x86-32 the instruction
189 // selector contains all of the 64-bit instructions from x86-64,
190 // under the assumption that i64 won't be used if the target doesn't
192 if (!TLI.isTypeLegal(VT))
195 Value *V = I->getOperand(0);
196 unsigned Op0 = getRegForValue(V);
198 // Handle constant load address.
199 if (!isa<Constant>(V) || !X86SelectConstAddr(V, Op0))
200 // Unhandled operand. Halt "fast" selection and bail.
204 // Get opcode and regclass of the output for the given load instruction.
206 const TargetRegisterClass *RC = NULL;
207 switch (VT.getSimpleVT()) {
208 default: return false;
211 RC = X86::GR8RegisterClass;
215 RC = X86::GR16RegisterClass;
219 RC = X86::GR32RegisterClass;
222 // Must be in x86-64 mode.
224 RC = X86::GR64RegisterClass;
227 if (Subtarget->hasSSE1()) {
229 RC = X86::FR32RegisterClass;
232 RC = X86::RFP32RegisterClass;
236 if (Subtarget->hasSSE2()) {
238 RC = X86::FR64RegisterClass;
241 RC = X86::RFP64RegisterClass;
246 RC = X86::RFP80RegisterClass;
250 unsigned ResultReg = createResultReg(RC);
253 // Address is in register.
256 AM.GV = cast<GlobalValue>(V);
257 addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
258 UpdateValueMap(I, ResultReg);
262 bool X86FastISel::X86SelectCmp(Instruction *I) {
263 CmpInst *CI = cast<CmpInst>(I);
265 unsigned Op0Reg = getRegForValue(CI->getOperand(0));
266 if (Op0Reg == 0) return false;
267 unsigned Op1Reg = getRegForValue(CI->getOperand(1));
268 if (Op1Reg == 0) return false;
270 MVT VT = TLI.getValueType(I->getOperand(0)->getType());
271 if (!TLI.isTypeLegal(VT))
275 switch (VT.getSimpleVT()) {
276 case MVT::i8: Opc = X86::CMP8rr; break;
277 case MVT::i16: Opc = X86::CMP16rr; break;
278 case MVT::i32: Opc = X86::CMP32rr; break;
279 case MVT::i64: Opc = X86::CMP64rr; break;
280 case MVT::f32: Opc = X86::UCOMISSrr; break;
281 case MVT::f64: Opc = X86::UCOMISDrr; break;
282 default: return false;
285 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
286 switch (CI->getPredicate()) {
287 case CmpInst::FCMP_OEQ: {
288 unsigned EReg = createResultReg(&X86::GR8RegClass);
289 unsigned NPReg = createResultReg(&X86::GR8RegClass);
290 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
291 BuildMI(MBB, TII.get(X86::SETEr), EReg);
292 BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
293 BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
296 case CmpInst::FCMP_UNE: {
297 unsigned NEReg = createResultReg(&X86::GR8RegClass);
298 unsigned PReg = createResultReg(&X86::GR8RegClass);
299 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
300 BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
301 BuildMI(MBB, TII.get(X86::SETPr), PReg);
302 BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
305 case CmpInst::FCMP_OGT:
306 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
307 BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
309 case CmpInst::FCMP_OGE:
310 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
311 BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
313 case CmpInst::FCMP_OLT:
314 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
315 BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
317 case CmpInst::FCMP_OLE:
318 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
319 BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
321 case CmpInst::FCMP_ONE:
322 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
323 BuildMI(MBB, TII.get(X86::SETNEr), ResultReg);
325 case CmpInst::FCMP_ORD:
326 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
327 BuildMI(MBB, TII.get(X86::SETNPr), ResultReg);
329 case CmpInst::FCMP_UNO:
330 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
331 BuildMI(MBB, TII.get(X86::SETPr), ResultReg);
333 case CmpInst::FCMP_UEQ:
334 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
335 BuildMI(MBB, TII.get(X86::SETEr), ResultReg);
337 case CmpInst::FCMP_UGT:
338 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
339 BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
341 case CmpInst::FCMP_UGE:
342 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
343 BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
345 case CmpInst::FCMP_ULT:
346 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
347 BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
349 case CmpInst::FCMP_ULE:
350 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
351 BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
353 case CmpInst::ICMP_EQ:
354 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
355 BuildMI(MBB, TII.get(X86::SETEr), ResultReg);
357 case CmpInst::ICMP_NE:
358 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
359 BuildMI(MBB, TII.get(X86::SETNEr), ResultReg);
361 case CmpInst::ICMP_UGT:
362 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
363 BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
365 case CmpInst::ICMP_UGE:
366 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
367 BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
369 case CmpInst::ICMP_ULT:
370 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
371 BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
373 case CmpInst::ICMP_ULE:
374 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
375 BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
377 case CmpInst::ICMP_SGT:
378 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
379 BuildMI(MBB, TII.get(X86::SETGr), ResultReg);
381 case CmpInst::ICMP_SGE:
382 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
383 BuildMI(MBB, TII.get(X86::SETGEr), ResultReg);
385 case CmpInst::ICMP_SLT:
386 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
387 BuildMI(MBB, TII.get(X86::SETLr), ResultReg);
389 case CmpInst::ICMP_SLE:
390 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
391 BuildMI(MBB, TII.get(X86::SETLEr), ResultReg);
397 UpdateValueMap(I, ResultReg);
401 bool X86FastISel::X86SelectZExt(Instruction *I) {
402 // Special-case hack: The only i1 values we know how to produce currently
403 // set the upper bits of an i8 value to zero.
404 if (I->getType() == Type::Int8Ty &&
405 I->getOperand(0)->getType() == Type::Int1Ty) {
406 unsigned ResultReg = getRegForValue(I->getOperand(0));
407 if (ResultReg == 0) return false;
408 UpdateValueMap(I, ResultReg);
415 bool X86FastISel::X86SelectBranch(Instruction *I) {
416 BranchInst *BI = cast<BranchInst>(I);
417 // Unconditional branches are selected by tablegen-generated code.
418 unsigned OpReg = getRegForValue(BI->getCondition());
419 if (OpReg == 0) return false;
420 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
421 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
423 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
424 BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
425 BuildMI(MBB, TII.get(X86::JMP)).addMBB(FalseMBB);
427 MBB->addSuccessor(TrueMBB);
428 MBB->addSuccessor(FalseMBB);
434 X86FastISel::TargetSelectInstruction(Instruction *I) {
435 switch (I->getOpcode()) {
437 case Instruction::Load:
438 return X86SelectLoad(I);
439 case Instruction::Store:
440 return X86SelectStore(I);
441 case Instruction::ICmp:
442 case Instruction::FCmp:
443 return X86SelectCmp(I);
444 case Instruction::ZExt:
445 return X86SelectZExt(I);
446 case Instruction::Br:
447 return X86SelectBranch(I);
453 unsigned X86FastISel::TargetSelectConstantPoolLoad(Constant *C,
454 MachineConstantPool* MCP) {
455 unsigned CPLoad = getRegForValue(C);
459 // Can't handle PIC-mode yet.
460 if (TM.getRelocationModel() == Reloc::PIC_)
463 MVT VT = MVT::getMVT(C->getType(), /*HandleUnknown=*/true);
464 if (VT == MVT::Other || !VT.isSimple())
465 // Unhandled type. Halt "fast" selection and bail.
469 VT = TLI.getPointerTy();
470 // We only handle legal types. For example, on x86-32 the instruction
471 // selector contains all of the 64-bit instructions from x86-64,
472 // under the assumption that i64 won't be used if the target doesn't
474 if (!TLI.isTypeLegal(VT))
477 // Get opcode and regclass of the output for the given load instruction.
479 const TargetRegisterClass *RC = NULL;
480 switch (VT.getSimpleVT()) {
481 default: return false;
484 RC = X86::GR8RegisterClass;
488 RC = X86::GR16RegisterClass;
492 RC = X86::GR32RegisterClass;
495 // Must be in x86-64 mode.
497 RC = X86::GR64RegisterClass;
500 if (Subtarget->hasSSE1()) {
502 RC = X86::FR32RegisterClass;
505 RC = X86::RFP32RegisterClass;
509 if (Subtarget->hasSSE2()) {
511 RC = X86::FR64RegisterClass;
514 RC = X86::RFP64RegisterClass;
519 RC = X86::RFP80RegisterClass;
523 unsigned ResultReg = createResultReg(RC);
524 if (isa<GlobalValue>(C)) {
525 if (X86SelectConstAddr(C, ResultReg))
532 unsigned MCPOffset = MCP->getConstantPoolIndex(C, 0);
533 addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset);
534 UpdateValueMap(C, ResultReg);
539 llvm::FastISel *X86::createFastISel(MachineFunction &mf,
540 DenseMap<const Value *, unsigned> &vm,
541 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm) {
542 return new X86FastISel(mf, vm, bm);