1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // pseudo registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // The x87 hardware tracks liveness of the stack registers, so it is necessary
16 // to implement exact liveness tracking between basic blocks. The CFG edges are
17 // partitioned into bundles where the same FP registers must be live in
18 // identical stack positions. Instructions are inserted at the end of each basic
19 // block to rearrange the live registers to match the outgoing bundle.
21 // This approach avoids splitting critical edges at the potential cost of more
22 // live register shuffling instructions when critical edges are present.
24 //===----------------------------------------------------------------------===//
26 #define DEBUG_TYPE "x86-codegen"
28 #include "X86InstrInfo.h"
29 #include "llvm/InlineAsm.h"
30 #include "llvm/ADT/DepthFirstIterator.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/CodeGen/EdgeBundles.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetInstrInfo.h"
44 #include "llvm/Target/TargetMachine.h"
48 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
49 STATISTIC(NumFP , "Number of floating point instructions");
52 struct FPS : public MachineFunctionPass {
54 FPS() : MachineFunctionPass(ID) {
55 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
56 // This is really only to keep valgrind quiet.
57 // The logic in isLive() is too much for it.
58 memset(Stack, 0, sizeof(Stack));
59 memset(RegMap, 0, sizeof(RegMap));
62 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 AU.addRequired<EdgeBundles>();
65 AU.addPreservedID(MachineLoopInfoID);
66 AU.addPreservedID(MachineDominatorsID);
67 MachineFunctionPass::getAnalysisUsage(AU);
70 virtual bool runOnMachineFunction(MachineFunction &MF);
72 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
75 const TargetInstrInfo *TII; // Machine instruction info.
77 // Two CFG edges are related if they leave the same block, or enter the same
78 // block. The transitive closure of an edge under this relation is a
79 // LiveBundle. It represents a set of CFG edges where the live FP stack
80 // registers must be allocated identically in the x87 stack.
82 // A LiveBundle is usually all the edges leaving a block, or all the edges
83 // entering a block, but it can contain more edges if critical edges are
86 // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
87 // but the exact mapping of FP registers to stack slots is fixed later.
89 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
92 // Number of pre-assigned live registers in FixStack. This is 0 when the
93 // stack order has not yet been fixed.
96 // Assigned stack order for live-in registers.
97 // FixStack[i] == getStackEntry(i) for all i < FixCount.
98 unsigned char FixStack[8];
100 LiveBundle() : Mask(0), FixCount(0) {}
102 // Have the live registers been assigned a stack order yet?
103 bool isFixed() const { return !Mask || FixCount; }
106 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
107 // with no live FP registers.
108 SmallVector<LiveBundle, 8> LiveBundles;
110 // The edge bundle analysis provides indices into the LiveBundles vector.
111 EdgeBundles *Bundles;
113 // Return a bitmask of FP registers in block's live-in list.
114 unsigned calcLiveInMask(MachineBasicBlock *MBB) {
116 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
117 E = MBB->livein_end(); I != E; ++I) {
118 unsigned Reg = *I - X86::FP0;
125 // Partition all the CFG edges into LiveBundles.
126 void bundleCFG(MachineFunction &MF);
128 MachineBasicBlock *MBB; // Current basic block
130 // The hardware keeps track of how many FP registers are live, so we have
131 // to model that exactly. Usually, each live register corresponds to an
132 // FP<n> register, but when dealing with calls, returns, and inline
133 // assembly, it is sometimes necessary to have live scratch registers.
134 unsigned Stack[8]; // FP<n> Registers in each stack slot...
135 unsigned StackTop; // The current top of the FP stack.
138 NumFPRegs = 16 // Including scratch pseudo-registers.
141 // For each live FP<n> register, point to its Stack[] entry.
142 // The first entries correspond to FP0-FP6, the rest are scratch registers
143 // used when we need slightly different live registers than what the
144 // register allocator thinks.
145 unsigned RegMap[NumFPRegs];
147 // Pending fixed registers - Inline assembly needs FP registers to appear
148 // in fixed stack slot positions. This is handled by copying FP registers
149 // to ST registers before the instruction, and copying back after the
152 // This is modeled with pending ST registers. NumPendingSTs is the number
153 // of ST registers (ST0-STn) we are tracking. PendingST[n] points to an FP
154 // register that holds the ST value. The ST registers are not moved into
155 // place until immediately before the instruction that needs them.
157 // It can happen that we need an ST register to be live when no FP register
160 // %ST0 = COPY %FP4<kill>
162 // When that happens, we allocate a scratch FP register to hold the ST
163 // value. That means every register in PendingST must be live.
165 unsigned NumPendingSTs;
166 unsigned char PendingST[8];
168 // Set up our stack model to match the incoming registers to MBB.
169 void setupBlockStack();
171 // Shuffle live registers to match the expectations of successor blocks.
172 void finishBlockStack();
174 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
175 void dumpStack() const {
176 dbgs() << "Stack contents:";
177 for (unsigned i = 0; i != StackTop; ++i) {
178 dbgs() << " FP" << Stack[i];
179 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
181 for (unsigned i = 0; i != NumPendingSTs; ++i)
182 dbgs() << ", ST" << i << " in FP" << unsigned(PendingST[i]);
187 /// getSlot - Return the stack slot number a particular register number is
189 unsigned getSlot(unsigned RegNo) const {
190 assert(RegNo < NumFPRegs && "Regno out of range!");
191 return RegMap[RegNo];
194 /// isLive - Is RegNo currently live in the stack?
195 bool isLive(unsigned RegNo) const {
196 unsigned Slot = getSlot(RegNo);
197 return Slot < StackTop && Stack[Slot] == RegNo;
200 /// getScratchReg - Return an FP register that is not currently in use.
201 unsigned getScratchReg() {
202 for (int i = NumFPRegs - 1; i >= 8; --i)
205 llvm_unreachable("Ran out of scratch FP registers");
208 /// isScratchReg - Returns trus if RegNo is a scratch FP register.
209 bool isScratchReg(unsigned RegNo) {
210 return RegNo > 8 && RegNo < NumFPRegs;
213 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
214 unsigned getStackEntry(unsigned STi) const {
216 report_fatal_error("Access past stack top!");
217 return Stack[StackTop-1-STi];
220 /// getSTReg - Return the X86::ST(i) register which contains the specified
221 /// FP<RegNo> register.
222 unsigned getSTReg(unsigned RegNo) const {
223 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
226 // pushReg - Push the specified FP<n> register onto the stack.
227 void pushReg(unsigned Reg) {
228 assert(Reg < NumFPRegs && "Register number out of range!");
230 report_fatal_error("Stack overflow!");
231 Stack[StackTop] = Reg;
232 RegMap[Reg] = StackTop++;
235 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
236 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
237 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
238 if (isAtTop(RegNo)) return;
240 unsigned STReg = getSTReg(RegNo);
241 unsigned RegOnTop = getStackEntry(0);
243 // Swap the slots the regs are in.
244 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
246 // Swap stack slot contents.
247 if (RegMap[RegOnTop] >= StackTop)
248 report_fatal_error("Access past stack top!");
249 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
251 // Emit an fxch to update the runtime processors version of the state.
252 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
256 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
257 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
258 unsigned STReg = getSTReg(RegNo);
259 pushReg(AsReg); // New register on top of stack
261 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
264 /// duplicatePendingSTBeforeKill - The instruction at I is about to kill
265 /// RegNo. If any PendingST registers still need the RegNo value, duplicate
266 /// them to new scratch registers.
267 void duplicatePendingSTBeforeKill(unsigned RegNo, MachineInstr *I) {
268 for (unsigned i = 0; i != NumPendingSTs; ++i) {
269 if (PendingST[i] != RegNo)
271 unsigned SR = getScratchReg();
272 DEBUG(dbgs() << "Duplicating pending ST" << i
273 << " in FP" << RegNo << " to FP" << SR << '\n');
274 duplicateToTop(RegNo, SR, I);
279 /// popStackAfter - Pop the current value off of the top of the FP stack
280 /// after the specified instruction.
281 void popStackAfter(MachineBasicBlock::iterator &I);
283 /// freeStackSlotAfter - Free the specified register from the register
284 /// stack, so that it is no longer in a register. If the register is
285 /// currently at the top of the stack, we just pop the current instruction,
286 /// otherwise we store the current top-of-stack into the specified slot,
287 /// then pop the top of stack.
288 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
290 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
292 MachineBasicBlock::iterator
293 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
295 /// Adjust the live registers to be the set in Mask.
296 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
298 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
299 /// st(0), FP reg FixStack[1] is st(1) etc.
300 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
301 MachineBasicBlock::iterator I);
303 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
305 void handleZeroArgFP(MachineBasicBlock::iterator &I);
306 void handleOneArgFP(MachineBasicBlock::iterator &I);
307 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
308 void handleTwoArgFP(MachineBasicBlock::iterator &I);
309 void handleCompareFP(MachineBasicBlock::iterator &I);
310 void handleCondMovFP(MachineBasicBlock::iterator &I);
311 void handleSpecialFP(MachineBasicBlock::iterator &I);
313 // Check if a COPY instruction is using FP registers.
314 bool isFPCopy(MachineInstr *MI) {
315 unsigned DstReg = MI->getOperand(0).getReg();
316 unsigned SrcReg = MI->getOperand(1).getReg();
318 return X86::RFP80RegClass.contains(DstReg) ||
319 X86::RFP80RegClass.contains(SrcReg);
325 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
327 /// getFPReg - Return the X86::FPx register number for the specified operand.
328 /// For example, this returns 3 for X86::FP3.
329 static unsigned getFPReg(const MachineOperand &MO) {
330 assert(MO.isReg() && "Expected an FP register!");
331 unsigned Reg = MO.getReg();
332 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
333 return Reg - X86::FP0;
336 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
337 /// register references into FP stack references.
339 bool FPS::runOnMachineFunction(MachineFunction &MF) {
340 // We only need to run this pass if there are any FP registers used in this
341 // function. If it is all integer, there is nothing for us to do!
342 bool FPIsUsed = false;
344 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
345 for (unsigned i = 0; i <= 6; ++i)
346 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
352 if (!FPIsUsed) return false;
354 Bundles = &getAnalysis<EdgeBundles>();
355 TII = MF.getTarget().getInstrInfo();
357 // Prepare cross-MBB liveness.
362 // Process the function in depth first order so that we process at least one
363 // of the predecessors for every reachable block in the function.
364 SmallPtrSet<MachineBasicBlock*, 8> Processed;
365 MachineBasicBlock *Entry = MF.begin();
367 bool Changed = false;
368 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
369 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
371 Changed |= processBasicBlock(MF, **I);
373 // Process any unreachable blocks in arbitrary order now.
374 if (MF.size() != Processed.size())
375 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
376 if (Processed.insert(BB))
377 Changed |= processBasicBlock(MF, *BB);
384 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and
385 /// live-out sets for the FP registers. Consistent means that the set of
386 /// registers live-out from a block is identical to the live-in set of all
387 /// successors. This is not enforced by the normal live-in lists since
388 /// registers may be implicitly defined, or not used by all successors.
389 void FPS::bundleCFG(MachineFunction &MF) {
390 assert(LiveBundles.empty() && "Stale data in LiveBundles");
391 LiveBundles.resize(Bundles->getNumBundles());
393 // Gather the actual live-in masks for all MBBs.
394 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
395 MachineBasicBlock *MBB = I;
396 const unsigned Mask = calcLiveInMask(MBB);
399 // Update MBB ingoing bundle mask.
400 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)].Mask |= Mask;
404 /// processBasicBlock - Loop over all of the instructions in the basic block,
405 /// transforming FP instructions into their stack form.
407 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
408 bool Changed = false;
414 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
415 MachineInstr *MI = I;
416 uint64_t Flags = MI->getDesc().TSFlags;
418 unsigned FPInstClass = Flags & X86II::FPTypeMask;
419 if (MI->isInlineAsm())
420 FPInstClass = X86II::SpecialFP;
422 if (MI->isCopy() && isFPCopy(MI))
423 FPInstClass = X86II::SpecialFP;
425 if (MI->isImplicitDef() &&
426 X86::RFP80RegClass.contains(MI->getOperand(0).getReg()))
427 FPInstClass = X86II::SpecialFP;
429 if (FPInstClass == X86II::NotFP)
430 continue; // Efficiently ignore non-fp insts!
432 MachineInstr *PrevMI = 0;
436 ++NumFP; // Keep track of # of pseudo instrs
437 DEBUG(dbgs() << "\nFPInst:\t" << *MI);
439 // Get dead variables list now because the MI pointer may be deleted as part
441 SmallVector<unsigned, 8> DeadRegs;
442 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
443 const MachineOperand &MO = MI->getOperand(i);
444 if (MO.isReg() && MO.isDead())
445 DeadRegs.push_back(MO.getReg());
448 switch (FPInstClass) {
449 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
450 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
451 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
452 case X86II::TwoArgFP: handleTwoArgFP(I); break;
453 case X86II::CompareFP: handleCompareFP(I); break;
454 case X86II::CondMovFP: handleCondMovFP(I); break;
455 case X86II::SpecialFP: handleSpecialFP(I); break;
456 default: llvm_unreachable("Unknown FP Type!");
459 // Check to see if any of the values defined by this instruction are dead
460 // after definition. If so, pop them.
461 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
462 unsigned Reg = DeadRegs[i];
463 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
464 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
465 freeStackSlotAfter(I, Reg-X86::FP0);
469 // Print out all of the instructions expanded to if -debug
471 MachineBasicBlock::iterator PrevI(PrevMI);
473 dbgs() << "Just deleted pseudo instruction\n";
475 MachineBasicBlock::iterator Start = I;
476 // Rewind to first instruction newly inserted.
477 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
478 dbgs() << "Inserted instructions:\n\t";
479 Start->print(dbgs(), &MF.getTarget());
480 while (++Start != llvm::next(I)) {}
494 /// setupBlockStack - Use the live bundles to set up our model of the stack
495 /// to match predecessors' live out stack.
496 void FPS::setupBlockStack() {
497 DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
498 << " derived from " << MBB->getName() << ".\n");
500 // Get the live-in bundle for MBB.
501 const LiveBundle &Bundle =
502 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)];
505 DEBUG(dbgs() << "Block has no FP live-ins.\n");
509 // Depth-first iteration should ensure that we always have an assigned stack.
510 assert(Bundle.isFixed() && "Reached block before any predecessors");
512 // Push the fixed live-in registers.
513 for (unsigned i = Bundle.FixCount; i > 0; --i) {
514 MBB->addLiveIn(X86::ST0+i-1);
515 DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
516 << unsigned(Bundle.FixStack[i-1]) << '\n');
517 pushReg(Bundle.FixStack[i-1]);
520 // Kill off unwanted live-ins. This can happen with a critical edge.
521 // FIXME: We could keep these live registers around as zombies. They may need
522 // to be revived at the end of a short block. It might save a few instrs.
523 adjustLiveRegs(calcLiveInMask(MBB), MBB->begin());
527 /// finishBlockStack - Revive live-outs that are implicitly defined out of
528 /// MBB. Shuffle live registers to match the expected fixed stack of any
529 /// predecessors, and ensure that all predecessors are expecting the same
531 void FPS::finishBlockStack() {
532 // The RET handling below takes care of return blocks for us.
533 if (MBB->succ_empty())
536 DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
537 << " derived from " << MBB->getName() << ".\n");
539 // Get MBB's live-out bundle.
540 unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true);
541 LiveBundle &Bundle = LiveBundles[BundleIdx];
543 // We may need to kill and define some registers to match successors.
544 // FIXME: This can probably be combined with the shuffle below.
545 MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
546 adjustLiveRegs(Bundle.Mask, Term);
549 DEBUG(dbgs() << "No live-outs.\n");
553 // Has the stack order been fixed yet?
554 DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
555 if (Bundle.isFixed()) {
556 DEBUG(dbgs() << "Shuffling stack to match.\n");
557 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
559 // Not fixed yet, we get to choose.
560 DEBUG(dbgs() << "Fixing stack order now.\n");
561 Bundle.FixCount = StackTop;
562 for (unsigned i = 0; i < StackTop; ++i)
563 Bundle.FixStack[i] = getStackEntry(i);
568 //===----------------------------------------------------------------------===//
569 // Efficient Lookup Table Support
570 //===----------------------------------------------------------------------===//
576 bool operator<(const TableEntry &TE) const { return from < TE.from; }
577 friend bool operator<(const TableEntry &TE, unsigned V) {
580 friend bool LLVM_ATTRIBUTE_USED operator<(unsigned V,
581 const TableEntry &TE) {
588 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
589 for (unsigned i = 0; i != NumEntries-1; ++i)
590 if (!(Table[i] < Table[i+1])) return false;
595 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
596 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
597 if (I != Table+N && I->from == Opcode)
603 #define ASSERT_SORTED(TABLE)
605 #define ASSERT_SORTED(TABLE) \
606 { static bool TABLE##Checked = false; \
607 if (!TABLE##Checked) { \
608 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
609 "All lookup tables must be sorted for efficient access!"); \
610 TABLE##Checked = true; \
615 //===----------------------------------------------------------------------===//
616 // Register File -> Register Stack Mapping Methods
617 //===----------------------------------------------------------------------===//
619 // OpcodeTable - Sorted map of register instructions to their stack version.
620 // The first element is an register file pseudo instruction, the second is the
621 // concrete X86 instruction which uses the register stack.
623 static const TableEntry OpcodeTable[] = {
624 { X86::ABS_Fp32 , X86::ABS_F },
625 { X86::ABS_Fp64 , X86::ABS_F },
626 { X86::ABS_Fp80 , X86::ABS_F },
627 { X86::ADD_Fp32m , X86::ADD_F32m },
628 { X86::ADD_Fp64m , X86::ADD_F64m },
629 { X86::ADD_Fp64m32 , X86::ADD_F32m },
630 { X86::ADD_Fp80m32 , X86::ADD_F32m },
631 { X86::ADD_Fp80m64 , X86::ADD_F64m },
632 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
633 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
634 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
635 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
636 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
637 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
638 { X86::CHS_Fp32 , X86::CHS_F },
639 { X86::CHS_Fp64 , X86::CHS_F },
640 { X86::CHS_Fp80 , X86::CHS_F },
641 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
642 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
643 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
644 { X86::CMOVB_Fp32 , X86::CMOVB_F },
645 { X86::CMOVB_Fp64 , X86::CMOVB_F },
646 { X86::CMOVB_Fp80 , X86::CMOVB_F },
647 { X86::CMOVE_Fp32 , X86::CMOVE_F },
648 { X86::CMOVE_Fp64 , X86::CMOVE_F },
649 { X86::CMOVE_Fp80 , X86::CMOVE_F },
650 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
651 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
652 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
653 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
654 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
655 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
656 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
657 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
658 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
659 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
660 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
661 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
662 { X86::CMOVP_Fp32 , X86::CMOVP_F },
663 { X86::CMOVP_Fp64 , X86::CMOVP_F },
664 { X86::CMOVP_Fp80 , X86::CMOVP_F },
665 { X86::COS_Fp32 , X86::COS_F },
666 { X86::COS_Fp64 , X86::COS_F },
667 { X86::COS_Fp80 , X86::COS_F },
668 { X86::DIVR_Fp32m , X86::DIVR_F32m },
669 { X86::DIVR_Fp64m , X86::DIVR_F64m },
670 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
671 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
672 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
673 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
674 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
675 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
676 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
677 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
678 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
679 { X86::DIV_Fp32m , X86::DIV_F32m },
680 { X86::DIV_Fp64m , X86::DIV_F64m },
681 { X86::DIV_Fp64m32 , X86::DIV_F32m },
682 { X86::DIV_Fp80m32 , X86::DIV_F32m },
683 { X86::DIV_Fp80m64 , X86::DIV_F64m },
684 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
685 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
686 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
687 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
688 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
689 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
690 { X86::ILD_Fp16m32 , X86::ILD_F16m },
691 { X86::ILD_Fp16m64 , X86::ILD_F16m },
692 { X86::ILD_Fp16m80 , X86::ILD_F16m },
693 { X86::ILD_Fp32m32 , X86::ILD_F32m },
694 { X86::ILD_Fp32m64 , X86::ILD_F32m },
695 { X86::ILD_Fp32m80 , X86::ILD_F32m },
696 { X86::ILD_Fp64m32 , X86::ILD_F64m },
697 { X86::ILD_Fp64m64 , X86::ILD_F64m },
698 { X86::ILD_Fp64m80 , X86::ILD_F64m },
699 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
700 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
701 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
702 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
703 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
704 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
705 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
706 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
707 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
708 { X86::IST_Fp16m32 , X86::IST_F16m },
709 { X86::IST_Fp16m64 , X86::IST_F16m },
710 { X86::IST_Fp16m80 , X86::IST_F16m },
711 { X86::IST_Fp32m32 , X86::IST_F32m },
712 { X86::IST_Fp32m64 , X86::IST_F32m },
713 { X86::IST_Fp32m80 , X86::IST_F32m },
714 { X86::IST_Fp64m32 , X86::IST_FP64m },
715 { X86::IST_Fp64m64 , X86::IST_FP64m },
716 { X86::IST_Fp64m80 , X86::IST_FP64m },
717 { X86::LD_Fp032 , X86::LD_F0 },
718 { X86::LD_Fp064 , X86::LD_F0 },
719 { X86::LD_Fp080 , X86::LD_F0 },
720 { X86::LD_Fp132 , X86::LD_F1 },
721 { X86::LD_Fp164 , X86::LD_F1 },
722 { X86::LD_Fp180 , X86::LD_F1 },
723 { X86::LD_Fp32m , X86::LD_F32m },
724 { X86::LD_Fp32m64 , X86::LD_F32m },
725 { X86::LD_Fp32m80 , X86::LD_F32m },
726 { X86::LD_Fp64m , X86::LD_F64m },
727 { X86::LD_Fp64m80 , X86::LD_F64m },
728 { X86::LD_Fp80m , X86::LD_F80m },
729 { X86::MUL_Fp32m , X86::MUL_F32m },
730 { X86::MUL_Fp64m , X86::MUL_F64m },
731 { X86::MUL_Fp64m32 , X86::MUL_F32m },
732 { X86::MUL_Fp80m32 , X86::MUL_F32m },
733 { X86::MUL_Fp80m64 , X86::MUL_F64m },
734 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
735 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
736 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
737 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
738 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
739 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
740 { X86::SIN_Fp32 , X86::SIN_F },
741 { X86::SIN_Fp64 , X86::SIN_F },
742 { X86::SIN_Fp80 , X86::SIN_F },
743 { X86::SQRT_Fp32 , X86::SQRT_F },
744 { X86::SQRT_Fp64 , X86::SQRT_F },
745 { X86::SQRT_Fp80 , X86::SQRT_F },
746 { X86::ST_Fp32m , X86::ST_F32m },
747 { X86::ST_Fp64m , X86::ST_F64m },
748 { X86::ST_Fp64m32 , X86::ST_F32m },
749 { X86::ST_Fp80m32 , X86::ST_F32m },
750 { X86::ST_Fp80m64 , X86::ST_F64m },
751 { X86::ST_FpP80m , X86::ST_FP80m },
752 { X86::SUBR_Fp32m , X86::SUBR_F32m },
753 { X86::SUBR_Fp64m , X86::SUBR_F64m },
754 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
755 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
756 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
757 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
758 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
759 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
760 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
761 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
762 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
763 { X86::SUB_Fp32m , X86::SUB_F32m },
764 { X86::SUB_Fp64m , X86::SUB_F64m },
765 { X86::SUB_Fp64m32 , X86::SUB_F32m },
766 { X86::SUB_Fp80m32 , X86::SUB_F32m },
767 { X86::SUB_Fp80m64 , X86::SUB_F64m },
768 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
769 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
770 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
771 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
772 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
773 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
774 { X86::TST_Fp32 , X86::TST_F },
775 { X86::TST_Fp64 , X86::TST_F },
776 { X86::TST_Fp80 , X86::TST_F },
777 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
778 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
779 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
780 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
781 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
782 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
785 static unsigned getConcreteOpcode(unsigned Opcode) {
786 ASSERT_SORTED(OpcodeTable);
787 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
788 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
792 //===----------------------------------------------------------------------===//
794 //===----------------------------------------------------------------------===//
796 // PopTable - Sorted map of instructions to their popping version. The first
797 // element is an instruction, the second is the version which pops.
799 static const TableEntry PopTable[] = {
800 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
802 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
803 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
805 { X86::IST_F16m , X86::IST_FP16m },
806 { X86::IST_F32m , X86::IST_FP32m },
808 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
810 { X86::ST_F32m , X86::ST_FP32m },
811 { X86::ST_F64m , X86::ST_FP64m },
812 { X86::ST_Frr , X86::ST_FPrr },
814 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
815 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
817 { X86::UCOM_FIr , X86::UCOM_FIPr },
819 { X86::UCOM_FPr , X86::UCOM_FPPr },
820 { X86::UCOM_Fr , X86::UCOM_FPr },
823 /// popStackAfter - Pop the current value off of the top of the FP stack after
824 /// the specified instruction. This attempts to be sneaky and combine the pop
825 /// into the instruction itself if possible. The iterator is left pointing to
826 /// the last instruction, be it a new pop instruction inserted, or the old
827 /// instruction if it was modified in place.
829 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
830 MachineInstr* MI = I;
831 DebugLoc dl = MI->getDebugLoc();
832 ASSERT_SORTED(PopTable);
834 report_fatal_error("Cannot pop empty stack!");
835 RegMap[Stack[--StackTop]] = ~0; // Update state
837 // Check to see if there is a popping version of this instruction...
838 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
840 I->setDesc(TII->get(Opcode));
841 if (Opcode == X86::UCOM_FPPr)
843 } else { // Insert an explicit pop
844 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
848 /// freeStackSlotAfter - Free the specified register from the register stack, so
849 /// that it is no longer in a register. If the register is currently at the top
850 /// of the stack, we just pop the current instruction, otherwise we store the
851 /// current top-of-stack into the specified slot, then pop the top of stack.
852 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
853 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
858 // Otherwise, store the top of stack into the dead slot, killing the operand
859 // without having to add in an explicit xchg then pop.
861 I = freeStackSlotBefore(++I, FPRegNo);
864 /// freeStackSlotBefore - Free the specified register without trying any
866 MachineBasicBlock::iterator
867 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
868 unsigned STReg = getSTReg(FPRegNo);
869 unsigned OldSlot = getSlot(FPRegNo);
870 unsigned TopReg = Stack[StackTop-1];
871 Stack[OldSlot] = TopReg;
872 RegMap[TopReg] = OldSlot;
873 RegMap[FPRegNo] = ~0;
874 Stack[--StackTop] = ~0;
875 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)).addReg(STReg);
878 /// adjustLiveRegs - Kill and revive registers such that exactly the FP
879 /// registers with a bit in Mask are live.
880 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
881 unsigned Defs = Mask;
883 for (unsigned i = 0; i < StackTop; ++i) {
884 unsigned RegNo = Stack[i];
885 if (!(Defs & (1 << RegNo)))
886 // This register is live, but we don't want it.
887 Kills |= (1 << RegNo);
889 // We don't need to imp-def this live register.
890 Defs &= ~(1 << RegNo);
892 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
894 // Produce implicit-defs for free by using killed registers.
895 while (Kills && Defs) {
896 unsigned KReg = CountTrailingZeros_32(Kills);
897 unsigned DReg = CountTrailingZeros_32(Defs);
898 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
899 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
900 std::swap(RegMap[KReg], RegMap[DReg]);
901 Kills &= ~(1 << KReg);
902 Defs &= ~(1 << DReg);
905 // Kill registers by popping.
906 if (Kills && I != MBB->begin()) {
907 MachineBasicBlock::iterator I2 = llvm::prior(I);
909 unsigned KReg = getStackEntry(0);
910 if (!(Kills & (1 << KReg)))
912 DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
914 Kills &= ~(1 << KReg);
918 // Manually kill the rest.
920 unsigned KReg = CountTrailingZeros_32(Kills);
921 DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
922 freeStackSlotBefore(I, KReg);
923 Kills &= ~(1 << KReg);
926 // Load zeros for all the imp-defs.
928 unsigned DReg = CountTrailingZeros_32(Defs);
929 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
930 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
932 Defs &= ~(1 << DReg);
935 // Now we should have the correct registers live.
937 assert(StackTop == CountPopulation_32(Mask) && "Live count mismatch");
940 /// shuffleStackTop - emit fxch instructions before I to shuffle the top
941 /// FixCount entries into the order given by FixStack.
942 /// FIXME: Is there a better algorithm than insertion sort?
943 void FPS::shuffleStackTop(const unsigned char *FixStack,
945 MachineBasicBlock::iterator I) {
946 // Move items into place, starting from the desired stack bottom.
948 // Old register at position FixCount.
949 unsigned OldReg = getStackEntry(FixCount);
950 // Desired register at position FixCount.
951 unsigned Reg = FixStack[FixCount];
954 // (Reg st0) (OldReg st0) = (Reg OldReg st0)
957 moveToTop(OldReg, I);
963 //===----------------------------------------------------------------------===//
964 // Instruction transformation implementation
965 //===----------------------------------------------------------------------===//
967 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
969 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
970 MachineInstr *MI = I;
971 unsigned DestReg = getFPReg(MI->getOperand(0));
973 // Change from the pseudo instruction to the concrete instruction.
974 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
975 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
977 // Result gets pushed on the stack.
981 /// handleOneArgFP - fst <mem>, ST(0)
983 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
984 MachineInstr *MI = I;
985 unsigned NumOps = MI->getDesc().getNumOperands();
986 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
987 "Can only handle fst* & ftst instructions!");
989 // Is this the last use of the source register?
990 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
991 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
994 duplicatePendingSTBeforeKill(Reg, I);
996 // FISTP64m is strange because there isn't a non-popping versions.
997 // If we have one _and_ we don't want to pop the operand, duplicate the value
998 // on the stack instead of moving it. This ensure that popping the value is
1000 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
1003 (MI->getOpcode() == X86::IST_Fp64m32 ||
1004 MI->getOpcode() == X86::ISTT_Fp16m32 ||
1005 MI->getOpcode() == X86::ISTT_Fp32m32 ||
1006 MI->getOpcode() == X86::ISTT_Fp64m32 ||
1007 MI->getOpcode() == X86::IST_Fp64m64 ||
1008 MI->getOpcode() == X86::ISTT_Fp16m64 ||
1009 MI->getOpcode() == X86::ISTT_Fp32m64 ||
1010 MI->getOpcode() == X86::ISTT_Fp64m64 ||
1011 MI->getOpcode() == X86::IST_Fp64m80 ||
1012 MI->getOpcode() == X86::ISTT_Fp16m80 ||
1013 MI->getOpcode() == X86::ISTT_Fp32m80 ||
1014 MI->getOpcode() == X86::ISTT_Fp64m80 ||
1015 MI->getOpcode() == X86::ST_FpP80m)) {
1016 duplicateToTop(Reg, getScratchReg(), I);
1018 moveToTop(Reg, I); // Move to the top of the stack...
1021 // Convert from the pseudo instruction to the concrete instruction.
1022 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
1023 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1025 if (MI->getOpcode() == X86::IST_FP64m ||
1026 MI->getOpcode() == X86::ISTT_FP16m ||
1027 MI->getOpcode() == X86::ISTT_FP32m ||
1028 MI->getOpcode() == X86::ISTT_FP64m ||
1029 MI->getOpcode() == X86::ST_FP80m) {
1031 report_fatal_error("Stack empty??");
1033 } else if (KillsSrc) { // Last use of operand?
1039 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
1040 /// replace the value with a newly computed value. These instructions may have
1041 /// non-fp operands after their FP operands.
1045 /// R1 = fadd R2, [mem]
1047 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
1048 MachineInstr *MI = I;
1050 unsigned NumOps = MI->getDesc().getNumOperands();
1051 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1054 // Is this the last use of the source register?
1055 unsigned Reg = getFPReg(MI->getOperand(1));
1056 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
1059 duplicatePendingSTBeforeKill(Reg, I);
1060 // If this is the last use of the source register, just make sure it's on
1061 // the top of the stack.
1064 report_fatal_error("Stack cannot be empty!");
1066 pushReg(getFPReg(MI->getOperand(0)));
1068 // If this is not the last use of the source register, _copy_ it to the top
1070 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
1073 // Change from the pseudo instruction to the concrete instruction.
1074 MI->RemoveOperand(1); // Drop the source operand.
1075 MI->RemoveOperand(0); // Drop the destination operand.
1076 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1080 //===----------------------------------------------------------------------===//
1081 // Define tables of various ways to map pseudo instructions
1084 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
1085 static const TableEntry ForwardST0Table[] = {
1086 { X86::ADD_Fp32 , X86::ADD_FST0r },
1087 { X86::ADD_Fp64 , X86::ADD_FST0r },
1088 { X86::ADD_Fp80 , X86::ADD_FST0r },
1089 { X86::DIV_Fp32 , X86::DIV_FST0r },
1090 { X86::DIV_Fp64 , X86::DIV_FST0r },
1091 { X86::DIV_Fp80 , X86::DIV_FST0r },
1092 { X86::MUL_Fp32 , X86::MUL_FST0r },
1093 { X86::MUL_Fp64 , X86::MUL_FST0r },
1094 { X86::MUL_Fp80 , X86::MUL_FST0r },
1095 { X86::SUB_Fp32 , X86::SUB_FST0r },
1096 { X86::SUB_Fp64 , X86::SUB_FST0r },
1097 { X86::SUB_Fp80 , X86::SUB_FST0r },
1100 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
1101 static const TableEntry ReverseST0Table[] = {
1102 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1103 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1104 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1105 { X86::DIV_Fp32 , X86::DIVR_FST0r },
1106 { X86::DIV_Fp64 , X86::DIVR_FST0r },
1107 { X86::DIV_Fp80 , X86::DIVR_FST0r },
1108 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1109 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1110 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1111 { X86::SUB_Fp32 , X86::SUBR_FST0r },
1112 { X86::SUB_Fp64 , X86::SUBR_FST0r },
1113 { X86::SUB_Fp80 , X86::SUBR_FST0r },
1116 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
1117 static const TableEntry ForwardSTiTable[] = {
1118 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1119 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1120 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1121 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1122 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1123 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1124 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1125 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1126 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1127 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1128 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1129 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1132 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
1133 static const TableEntry ReverseSTiTable[] = {
1134 { X86::ADD_Fp32 , X86::ADD_FrST0 },
1135 { X86::ADD_Fp64 , X86::ADD_FrST0 },
1136 { X86::ADD_Fp80 , X86::ADD_FrST0 },
1137 { X86::DIV_Fp32 , X86::DIV_FrST0 },
1138 { X86::DIV_Fp64 , X86::DIV_FrST0 },
1139 { X86::DIV_Fp80 , X86::DIV_FrST0 },
1140 { X86::MUL_Fp32 , X86::MUL_FrST0 },
1141 { X86::MUL_Fp64 , X86::MUL_FrST0 },
1142 { X86::MUL_Fp80 , X86::MUL_FrST0 },
1143 { X86::SUB_Fp32 , X86::SUB_FrST0 },
1144 { X86::SUB_Fp64 , X86::SUB_FrST0 },
1145 { X86::SUB_Fp80 , X86::SUB_FrST0 },
1149 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
1150 /// instructions which need to be simplified and possibly transformed.
1152 /// Result: ST(0) = fsub ST(0), ST(i)
1153 /// ST(i) = fsub ST(0), ST(i)
1154 /// ST(0) = fsubr ST(0), ST(i)
1155 /// ST(i) = fsubr ST(0), ST(i)
1157 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
1158 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1159 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1160 MachineInstr *MI = I;
1162 unsigned NumOperands = MI->getDesc().getNumOperands();
1163 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
1164 unsigned Dest = getFPReg(MI->getOperand(0));
1165 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1166 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1167 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1168 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1169 DebugLoc dl = MI->getDebugLoc();
1171 unsigned TOS = getStackEntry(0);
1173 // One of our operands must be on the top of the stack. If neither is yet, we
1174 // need to move one.
1175 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
1176 // We can choose to move either operand to the top of the stack. If one of
1177 // the operands is killed by this instruction, we want that one so that we
1178 // can update right on top of the old version.
1180 moveToTop(Op0, I); // Move dead operand to TOS.
1182 } else if (KillsOp1) {
1186 // All of the operands are live after this instruction executes, so we
1187 // cannot update on top of any operand. Because of this, we must
1188 // duplicate one of the stack elements to the top. It doesn't matter
1189 // which one we pick.
1191 duplicateToTop(Op0, Dest, I);
1195 } else if (!KillsOp0 && !KillsOp1) {
1196 // If we DO have one of our operands at the top of the stack, but we don't
1197 // have a dead operand, we must duplicate one of the operands to a new slot
1199 duplicateToTop(Op0, Dest, I);
1204 // Now we know that one of our operands is on the top of the stack, and at
1205 // least one of our operands is killed by this instruction.
1206 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
1207 "Stack conditions not set up right!");
1209 // We decide which form to use based on what is on the top of the stack, and
1210 // which operand is killed by this instruction.
1211 const TableEntry *InstTable;
1212 bool isForward = TOS == Op0;
1213 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
1216 InstTable = ForwardST0Table;
1218 InstTable = ReverseST0Table;
1221 InstTable = ForwardSTiTable;
1223 InstTable = ReverseSTiTable;
1226 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
1228 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
1230 // NotTOS - The register which is not on the top of stack...
1231 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
1233 // Replace the old instruction with a new instruction
1235 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1237 // If both operands are killed, pop one off of the stack in addition to
1238 // overwriting the other one.
1239 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
1240 assert(!updateST0 && "Should have updated other operand!");
1241 popStackAfter(I); // Pop the top of stack
1244 // Update stack information so that we know the destination register is now on
1246 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
1247 assert(UpdatedSlot < StackTop && Dest < 7);
1248 Stack[UpdatedSlot] = Dest;
1249 RegMap[Dest] = UpdatedSlot;
1250 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
1253 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
1254 /// register arguments and no explicit destinations.
1256 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
1257 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1258 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1259 MachineInstr *MI = I;
1261 unsigned NumOperands = MI->getDesc().getNumOperands();
1262 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
1263 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1264 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1265 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1266 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1268 // Make sure the first operand is on the top of stack, the other one can be
1272 // Change from the pseudo instruction to the concrete instruction.
1273 MI->getOperand(0).setReg(getSTReg(Op1));
1274 MI->RemoveOperand(1);
1275 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1277 // If any of the operands are killed by this instruction, free them.
1278 if (KillsOp0) freeStackSlotAfter(I, Op0);
1279 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
1282 /// handleCondMovFP - Handle two address conditional move instructions. These
1283 /// instructions move a st(i) register to st(0) iff a condition is true. These
1284 /// instructions require that the first operand is at the top of the stack, but
1285 /// otherwise don't modify the stack at all.
1286 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
1287 MachineInstr *MI = I;
1289 unsigned Op0 = getFPReg(MI->getOperand(0));
1290 unsigned Op1 = getFPReg(MI->getOperand(2));
1291 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1293 // The first operand *must* be on the top of the stack.
1296 // Change the second operand to the stack register that the operand is in.
1297 // Change from the pseudo instruction to the concrete instruction.
1298 MI->RemoveOperand(0);
1299 MI->RemoveOperand(1);
1300 MI->getOperand(0).setReg(getSTReg(Op1));
1301 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1303 // If we kill the second operand, make sure to pop it from the stack.
1304 if (Op0 != Op1 && KillsOp1) {
1305 // Get this value off of the register stack.
1306 freeStackSlotAfter(I, Op1);
1311 /// handleSpecialFP - Handle special instructions which behave unlike other
1312 /// floating point instructions. This is primarily intended for use by pseudo
1315 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
1316 MachineInstr *MI = I;
1317 switch (MI->getOpcode()) {
1318 default: llvm_unreachable("Unknown SpecialFP instruction!");
1319 case TargetOpcode::COPY: {
1320 // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.
1321 const MachineOperand &MO1 = MI->getOperand(1);
1322 const MachineOperand &MO0 = MI->getOperand(0);
1323 unsigned DstST = MO0.getReg() - X86::ST0;
1324 unsigned SrcST = MO1.getReg() - X86::ST0;
1325 bool KillsSrc = MI->killsRegister(MO1.getReg());
1327 // ST = COPY FP. Set up a pending ST register.
1329 unsigned SrcFP = getFPReg(MO1);
1330 assert(isLive(SrcFP) && "Cannot copy dead register");
1331 assert(!MO0.isDead() && "Cannot copy to dead ST register");
1333 // Unallocated STs are marked as the nonexistent FP255.
1334 while (NumPendingSTs <= DstST)
1335 PendingST[NumPendingSTs++] = NumFPRegs;
1337 // STi could still be live from a previous inline asm.
1338 if (isScratchReg(PendingST[DstST])) {
1339 DEBUG(dbgs() << "Clobbering old ST in FP" << unsigned(PendingST[DstST])
1341 freeStackSlotBefore(MI, PendingST[DstST]);
1344 // When the source is killed, allocate a scratch FP register.
1346 duplicatePendingSTBeforeKill(SrcFP, I);
1347 unsigned Slot = getSlot(SrcFP);
1348 unsigned SR = getScratchReg();
1349 PendingST[DstST] = SR;
1353 PendingST[DstST] = SrcFP;
1357 // FP = COPY ST. Extract fixed stack value.
1358 // Any instruction defining ST registers must have assigned them to a
1359 // scratch register.
1361 unsigned DstFP = getFPReg(MO0);
1362 assert(!isLive(DstFP) && "Cannot copy ST to live FP register");
1363 assert(NumPendingSTs > SrcST && "Cannot copy from dead ST register");
1364 unsigned SrcFP = PendingST[SrcST];
1365 assert(isScratchReg(SrcFP) && "Expected ST in a scratch register");
1366 assert(isLive(SrcFP) && "Scratch holding ST is dead");
1368 // DstFP steals the stack slot from SrcFP.
1369 unsigned Slot = getSlot(SrcFP);
1370 Stack[Slot] = DstFP;
1371 RegMap[DstFP] = Slot;
1373 // Always treat the ST as killed.
1374 PendingST[SrcST] = NumFPRegs;
1375 while (NumPendingSTs && PendingST[NumPendingSTs - 1] == NumFPRegs)
1381 unsigned DstFP = getFPReg(MO0);
1382 unsigned SrcFP = getFPReg(MO1);
1383 assert(isLive(SrcFP) && "Cannot copy dead register");
1385 // If the input operand is killed, we can just change the owner of the
1386 // incoming stack slot into the result.
1387 unsigned Slot = getSlot(SrcFP);
1388 Stack[Slot] = DstFP;
1389 RegMap[DstFP] = Slot;
1391 // For COPY we just duplicate the specified value to a new stack slot.
1392 // This could be made better, but would require substantial changes.
1393 duplicateToTop(SrcFP, DstFP, I);
1398 case TargetOpcode::IMPLICIT_DEF: {
1399 // All FP registers must be explicitly defined, so load a 0 instead.
1400 unsigned Reg = MI->getOperand(0).getReg() - X86::FP0;
1401 DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
1402 BuildMI(*MBB, I, MI->getDebugLoc(), TII->get(X86::LD_F0));
1407 case X86::FpPOP_RETVAL: {
1408 // The FpPOP_RETVAL instruction is used after calls that return a value on
1409 // the floating point stack. We cannot model this with ST defs since CALL
1410 // instructions have fixed clobber lists. This instruction is interpreted
1411 // to mean that there is one more live register on the stack than we
1414 // This means that StackTop does not match the hardware stack between a
1415 // call and the FpPOP_RETVAL instructions. We do tolerate FP instructions
1416 // between CALL and FpPOP_RETVAL as long as they don't overflow the
1418 unsigned DstFP = getFPReg(MI->getOperand(0));
1420 // Move existing stack elements up to reflect reality.
1421 assert(StackTop < 8 && "Stack overflowed before FpPOP_RETVAL");
1423 std::copy_backward(Stack, Stack + StackTop, Stack + StackTop + 1);
1424 for (unsigned i = 0; i != NumFPRegs; ++i)
1429 // DstFP is the new bottom of the stack.
1433 // DstFP will be killed by processBasicBlock if this was a dead def.
1437 case TargetOpcode::INLINEASM: {
1438 // The inline asm MachineInstr currently only *uses* FP registers for the
1439 // 'f' constraint. These should be turned into the current ST(x) register
1440 // in the machine instr.
1442 // There are special rules for x87 inline assembly. The compiler must know
1443 // exactly how many registers are popped and pushed implicitly by the asm.
1444 // Otherwise it is not possible to restore the stack state after the inline
1447 // There are 3 kinds of input operands:
1449 // 1. Popped inputs. These must appear at the stack top in ST0-STn. A
1450 // popped input operand must be in a fixed stack slot, and it is either
1451 // tied to an output operand, or in the clobber list. The MI has ST use
1452 // and def operands for these inputs.
1454 // 2. Fixed inputs. These inputs appear in fixed stack slots, but are
1455 // preserved by the inline asm. The fixed stack slots must be STn-STm
1456 // following the popped inputs. A fixed input operand cannot be tied to
1457 // an output or appear in the clobber list. The MI has ST use operands
1458 // and no defs for these inputs.
1460 // 3. Preserved inputs. These inputs use the "f" constraint which is
1461 // represented as an FP register. The inline asm won't change these
1464 // Outputs must be in ST registers, FP outputs are not allowed. Clobbered
1465 // registers do not count as output operands. The inline asm changes the
1466 // stack as if it popped all the popped inputs and then pushed all the
1469 // Scan the assembly for ST registers used, defined and clobbered. We can
1470 // only tell clobbers from defs by looking at the asm descriptor.
1471 unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
1472 unsigned NumOps = 0;
1473 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
1474 i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) {
1475 unsigned Flags = MI->getOperand(i).getImm();
1476 NumOps = InlineAsm::getNumOperandRegisters(Flags);
1479 const MachineOperand &MO = MI->getOperand(i + 1);
1482 unsigned STReg = MO.getReg() - X86::ST0;
1486 switch (InlineAsm::getKind(Flags)) {
1487 case InlineAsm::Kind_RegUse:
1488 STUses |= (1u << STReg);
1490 case InlineAsm::Kind_RegDef:
1491 case InlineAsm::Kind_RegDefEarlyClobber:
1492 STDefs |= (1u << STReg);
1494 STDeadDefs |= (1u << STReg);
1496 case InlineAsm::Kind_Clobber:
1497 STClobbers |= (1u << STReg);
1504 if (STUses && !isMask_32(STUses))
1505 MI->emitError("fixed input regs must be last on the x87 stack");
1506 unsigned NumSTUses = CountTrailingOnes_32(STUses);
1508 // Defs must be contiguous from the stack top. ST0-STn.
1509 if (STDefs && !isMask_32(STDefs)) {
1510 MI->emitError("output regs must be last on the x87 stack");
1511 STDefs = NextPowerOf2(STDefs) - 1;
1513 unsigned NumSTDefs = CountTrailingOnes_32(STDefs);
1515 // So must the clobbered stack slots. ST0-STm, m >= n.
1516 if (STClobbers && !isMask_32(STDefs | STClobbers))
1517 MI->emitError("clobbers must be last on the x87 stack");
1519 // Popped inputs are the ones that are also clobbered or defined.
1520 unsigned STPopped = STUses & (STDefs | STClobbers);
1521 if (STPopped && !isMask_32(STPopped))
1522 MI->emitError("implicitly popped regs must be last on the x87 stack");
1523 unsigned NumSTPopped = CountTrailingOnes_32(STPopped);
1525 DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
1526 << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");
1528 // Scan the instruction for FP uses corresponding to "f" constraints.
1529 // Collect FP registers to kill afer the instruction.
1530 // Always kill all the scratch regs.
1531 unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
1532 unsigned FPUsed = 0;
1533 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1534 MachineOperand &Op = MI->getOperand(i);
1535 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1538 MI->emitError("illegal \"f\" output constraint");
1539 unsigned FPReg = getFPReg(Op);
1540 FPUsed |= 1U << FPReg;
1542 // If we kill this operand, make sure to pop it from the stack after the
1543 // asm. We just remember it for now, and pop them all off at the end in
1546 FPKills |= 1U << FPReg;
1549 // The popped inputs will be killed by the instruction, so duplicate them
1550 // if the FP register needs to be live after the instruction, or if it is
1551 // used in the instruction itself. We effectively treat the popped inputs
1552 // as early clobbers.
1553 for (unsigned i = 0; i < NumSTPopped; ++i) {
1554 if ((FPKills & ~FPUsed) & (1u << PendingST[i]))
1556 unsigned SR = getScratchReg();
1557 duplicateToTop(PendingST[i], SR, I);
1558 DEBUG(dbgs() << "Duplicating ST" << i << " in FP"
1559 << unsigned(PendingST[i]) << " to avoid clobbering it.\n");
1563 // Make sure we have a unique live register for every fixed use. Some of
1564 // them could be undef uses, and we need to emit LD_F0 instructions.
1565 for (unsigned i = 0; i < NumSTUses; ++i) {
1566 if (i < NumPendingSTs && PendingST[i] < NumFPRegs) {
1567 // Check for shared assignments.
1568 for (unsigned j = 0; j < i; ++j) {
1569 if (PendingST[j] != PendingST[i])
1571 // STi and STj are inn the same register, create a copy.
1572 unsigned SR = getScratchReg();
1573 duplicateToTop(PendingST[i], SR, I);
1574 DEBUG(dbgs() << "Duplicating ST" << i << " in FP"
1575 << unsigned(PendingST[i])
1576 << " to avoid collision with ST" << j << '\n');
1581 unsigned SR = getScratchReg();
1582 DEBUG(dbgs() << "Emitting LD_F0 for ST" << i << " in FP" << SR << '\n');
1583 BuildMI(*MBB, I, MI->getDebugLoc(), TII->get(X86::LD_F0));
1586 if (NumPendingSTs == i)
1589 assert(NumPendingSTs >= NumSTUses && "Fixed registers should be assigned");
1591 // Now we can rearrange the live registers to match what was requested.
1592 shuffleStackTop(PendingST, NumPendingSTs, I);
1593 DEBUG({dbgs() << "Before asm: "; dumpStack();});
1595 // With the stack layout fixed, rewrite the FP registers.
1596 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1597 MachineOperand &Op = MI->getOperand(i);
1598 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1600 unsigned FPReg = getFPReg(Op);
1601 Op.setReg(getSTReg(FPReg));
1604 // Simulate the inline asm popping its inputs and pushing its outputs.
1605 StackTop -= NumSTPopped;
1607 // Hold the fixed output registers in scratch FP registers. They will be
1608 // transferred to real FP registers by copies.
1610 for (unsigned i = 0; i < NumSTDefs; ++i) {
1611 unsigned SR = getScratchReg();
1613 FPKills &= ~(1u << SR);
1615 for (unsigned i = 0; i < NumSTDefs; ++i)
1616 PendingST[NumPendingSTs++] = getStackEntry(i);
1617 DEBUG({dbgs() << "After asm: "; dumpStack();});
1619 // If any of the ST defs were dead, pop them immediately. Our caller only
1620 // handles dead FP defs.
1621 MachineBasicBlock::iterator InsertPt = MI;
1622 for (unsigned i = 0; STDefs & (1u << i); ++i) {
1623 if (!(STDeadDefs & (1u << i)))
1625 freeStackSlotAfter(InsertPt, PendingST[i]);
1626 PendingST[i] = NumFPRegs;
1628 while (NumPendingSTs && PendingST[NumPendingSTs - 1] == NumFPRegs)
1631 // If this asm kills any FP registers (is the last use of them) we must
1632 // explicitly emit pop instructions for them. Do this now after the asm has
1633 // executed so that the ST(x) numbers are not off (which would happen if we
1634 // did this inline with operand rewriting).
1636 // Note: this might be a non-optimal pop sequence. We might be able to do
1637 // better by trying to pop in stack order or something.
1639 unsigned FPReg = CountTrailingZeros_32(FPKills);
1641 freeStackSlotAfter(InsertPt, FPReg);
1642 FPKills &= ~(1U << FPReg);
1644 // Don't delete the inline asm!
1648 case X86::WIN_FTOL_32:
1649 case X86::WIN_FTOL_64: {
1650 // Push the operand into ST0.
1651 MachineOperand &Op = MI->getOperand(0);
1652 assert(Op.isUse() && Op.isReg() &&
1653 Op.getReg() >= X86::FP0 && Op.getReg() <= X86::FP6);
1654 unsigned FPReg = getFPReg(Op);
1656 moveToTop(FPReg, I);
1658 duplicateToTop(FPReg, FPReg, I);
1660 // Emit the call. This will pop the operand.
1661 BuildMI(*MBB, I, MI->getDebugLoc(), TII->get(X86::CALLpcrel32))
1662 .addExternalSymbol("_ftol2")
1663 .addReg(X86::ST0, RegState::ImplicitKill)
1664 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
1665 .addReg(X86::EDX, RegState::Define | RegState::Implicit)
1666 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1674 // If RET has an FP register use operand, pass the first one in ST(0) and
1675 // the second one in ST(1).
1677 // Find the register operands.
1678 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1679 unsigned LiveMask = 0;
1681 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1682 MachineOperand &Op = MI->getOperand(i);
1683 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1685 // FP Register uses must be kills unless there are two uses of the same
1686 // register, in which case only one will be a kill.
1687 assert(Op.isUse() &&
1688 (Op.isKill() || // Marked kill.
1689 getFPReg(Op) == FirstFPRegOp || // Second instance.
1690 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1691 "Ret only defs operands, and values aren't live beyond it");
1693 if (FirstFPRegOp == ~0U)
1694 FirstFPRegOp = getFPReg(Op);
1696 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1697 SecondFPRegOp = getFPReg(Op);
1699 LiveMask |= (1 << getFPReg(Op));
1701 // Remove the operand so that later passes don't see it.
1702 MI->RemoveOperand(i);
1706 // We may have been carrying spurious live-ins, so make sure only the returned
1707 // registers are left live.
1708 adjustLiveRegs(LiveMask, MI);
1709 if (!LiveMask) return; // Quick check to see if any are possible.
1711 // There are only four possibilities here:
1712 // 1) we are returning a single FP value. In this case, it has to be in
1713 // ST(0) already, so just declare success by removing the value from the
1715 if (SecondFPRegOp == ~0U) {
1716 // Assert that the top of stack contains the right FP register.
1717 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1718 "Top of stack not the right register for RET!");
1720 // Ok, everything is good, mark the value as not being on the stack
1721 // anymore so that our assertion about the stack being empty at end of
1722 // block doesn't fire.
1727 // Otherwise, we are returning two values:
1728 // 2) If returning the same value for both, we only have one thing in the FP
1729 // stack. Consider: RET FP1, FP1
1730 if (StackTop == 1) {
1731 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1732 "Stack misconfiguration for RET!");
1734 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1735 // register to hold it.
1736 unsigned NewReg = getScratchReg();
1737 duplicateToTop(FirstFPRegOp, NewReg, MI);
1738 FirstFPRegOp = NewReg;
1741 /// Okay we know we have two different FPx operands now:
1742 assert(StackTop == 2 && "Must have two values live!");
1744 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1745 /// in ST(1). In this case, emit an fxch.
1746 if (getStackEntry(0) == SecondFPRegOp) {
1747 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1748 moveToTop(FirstFPRegOp, MI);
1751 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1752 /// ST(1). Just remove both from our understanding of the stack and return.
1753 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1754 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1759 I = MBB->erase(I); // Remove the pseudo instruction
1761 // We want to leave I pointing to the previous instruction, but what if we
1762 // just erased the first instruction?
1763 if (I == MBB->begin()) {
1764 DEBUG(dbgs() << "Inserting dummy KILL\n");
1765 I = BuildMI(*MBB, I, DebugLoc(), TII->get(TargetOpcode::KILL));