1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // pseudo registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // The x87 hardware tracks liveness of the stack registers, so it is necessary
16 // to implement exact liveness tracking between basic blocks. The CFG edges are
17 // partitioned into bundles where the same FP registers must be live in
18 // identical stack positions. Instructions are inserted at the end of each basic
19 // block to rearrange the live registers to match the outgoing bundle.
21 // This approach avoids splitting critical edges at the potential cost of more
22 // live register shuffling instructions when critical edges are present.
24 //===----------------------------------------------------------------------===//
27 #include "X86InstrInfo.h"
28 #include "llvm/ADT/DepthFirstIterator.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/CodeGen/EdgeBundles.h"
35 #include "llvm/CodeGen/LivePhysRegs.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetSubtargetInfo.h"
51 #define DEBUG_TYPE "x86-codegen"
53 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
54 STATISTIC(NumFP , "Number of floating point instructions");
57 const unsigned ScratchFPReg = 7;
59 struct FPS : public MachineFunctionPass {
61 FPS() : MachineFunctionPass(ID) {
62 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
63 // This is really only to keep valgrind quiet.
64 // The logic in isLive() is too much for it.
65 memset(Stack, 0, sizeof(Stack));
66 memset(RegMap, 0, sizeof(RegMap));
69 void getAnalysisUsage(AnalysisUsage &AU) const override {
71 AU.addRequired<EdgeBundles>();
72 AU.addPreservedID(MachineLoopInfoID);
73 AU.addPreservedID(MachineDominatorsID);
74 MachineFunctionPass::getAnalysisUsage(AU);
77 bool runOnMachineFunction(MachineFunction &MF) override;
79 const char *getPassName() const override { return "X86 FP Stackifier"; }
82 const TargetInstrInfo *TII; // Machine instruction info.
84 // Two CFG edges are related if they leave the same block, or enter the same
85 // block. The transitive closure of an edge under this relation is a
86 // LiveBundle. It represents a set of CFG edges where the live FP stack
87 // registers must be allocated identically in the x87 stack.
89 // A LiveBundle is usually all the edges leaving a block, or all the edges
90 // entering a block, but it can contain more edges if critical edges are
93 // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
94 // but the exact mapping of FP registers to stack slots is fixed later.
96 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
99 // Number of pre-assigned live registers in FixStack. This is 0 when the
100 // stack order has not yet been fixed.
103 // Assigned stack order for live-in registers.
104 // FixStack[i] == getStackEntry(i) for all i < FixCount.
105 unsigned char FixStack[8];
107 LiveBundle() : Mask(0), FixCount(0) {}
109 // Have the live registers been assigned a stack order yet?
110 bool isFixed() const { return !Mask || FixCount; }
113 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
114 // with no live FP registers.
115 SmallVector<LiveBundle, 8> LiveBundles;
117 // The edge bundle analysis provides indices into the LiveBundles vector.
118 EdgeBundles *Bundles;
120 // Return a bitmask of FP registers in block's live-in list.
121 static unsigned calcLiveInMask(MachineBasicBlock *MBB) {
123 for (const auto &LI : MBB->liveins()) {
124 if (LI.PhysReg < X86::FP0 || LI.PhysReg > X86::FP6)
126 Mask |= 1 << (LI.PhysReg - X86::FP0);
131 // Partition all the CFG edges into LiveBundles.
132 void bundleCFG(MachineFunction &MF);
134 MachineBasicBlock *MBB; // Current basic block
136 // The hardware keeps track of how many FP registers are live, so we have
137 // to model that exactly. Usually, each live register corresponds to an
138 // FP<n> register, but when dealing with calls, returns, and inline
139 // assembly, it is sometimes necessary to have live scratch registers.
140 unsigned Stack[8]; // FP<n> Registers in each stack slot...
141 unsigned StackTop; // The current top of the FP stack.
144 NumFPRegs = 8 // Including scratch pseudo-registers.
147 // For each live FP<n> register, point to its Stack[] entry.
148 // The first entries correspond to FP0-FP6, the rest are scratch registers
149 // used when we need slightly different live registers than what the
150 // register allocator thinks.
151 unsigned RegMap[NumFPRegs];
153 // Set up our stack model to match the incoming registers to MBB.
154 void setupBlockStack();
156 // Shuffle live registers to match the expectations of successor blocks.
157 void finishBlockStack();
159 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
160 void dumpStack() const {
161 dbgs() << "Stack contents:";
162 for (unsigned i = 0; i != StackTop; ++i) {
163 dbgs() << " FP" << Stack[i];
164 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
169 /// getSlot - Return the stack slot number a particular register number is
171 unsigned getSlot(unsigned RegNo) const {
172 assert(RegNo < NumFPRegs && "Regno out of range!");
173 return RegMap[RegNo];
176 /// isLive - Is RegNo currently live in the stack?
177 bool isLive(unsigned RegNo) const {
178 unsigned Slot = getSlot(RegNo);
179 return Slot < StackTop && Stack[Slot] == RegNo;
182 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
183 unsigned getStackEntry(unsigned STi) const {
185 report_fatal_error("Access past stack top!");
186 return Stack[StackTop-1-STi];
189 /// getSTReg - Return the X86::ST(i) register which contains the specified
190 /// FP<RegNo> register.
191 unsigned getSTReg(unsigned RegNo) const {
192 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
195 // pushReg - Push the specified FP<n> register onto the stack.
196 void pushReg(unsigned Reg) {
197 assert(Reg < NumFPRegs && "Register number out of range!");
199 report_fatal_error("Stack overflow!");
200 Stack[StackTop] = Reg;
201 RegMap[Reg] = StackTop++;
204 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
205 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
206 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
207 if (isAtTop(RegNo)) return;
209 unsigned STReg = getSTReg(RegNo);
210 unsigned RegOnTop = getStackEntry(0);
212 // Swap the slots the regs are in.
213 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
215 // Swap stack slot contents.
216 if (RegMap[RegOnTop] >= StackTop)
217 report_fatal_error("Access past stack top!");
218 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
220 // Emit an fxch to update the runtime processors version of the state.
221 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
225 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
226 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
227 unsigned STReg = getSTReg(RegNo);
228 pushReg(AsReg); // New register on top of stack
230 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
233 /// popStackAfter - Pop the current value off of the top of the FP stack
234 /// after the specified instruction.
235 void popStackAfter(MachineBasicBlock::iterator &I);
237 /// freeStackSlotAfter - Free the specified register from the register
238 /// stack, so that it is no longer in a register. If the register is
239 /// currently at the top of the stack, we just pop the current instruction,
240 /// otherwise we store the current top-of-stack into the specified slot,
241 /// then pop the top of stack.
242 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
244 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
246 MachineBasicBlock::iterator
247 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
249 /// Adjust the live registers to be the set in Mask.
250 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
252 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
253 /// st(0), FP reg FixStack[1] is st(1) etc.
254 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
255 MachineBasicBlock::iterator I);
257 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
259 void handleCall(MachineBasicBlock::iterator &I);
260 void handleZeroArgFP(MachineBasicBlock::iterator &I);
261 void handleOneArgFP(MachineBasicBlock::iterator &I);
262 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
263 void handleTwoArgFP(MachineBasicBlock::iterator &I);
264 void handleCompareFP(MachineBasicBlock::iterator &I);
265 void handleCondMovFP(MachineBasicBlock::iterator &I);
266 void handleSpecialFP(MachineBasicBlock::iterator &I);
268 // Check if a COPY instruction is using FP registers.
269 static bool isFPCopy(MachineInstr *MI) {
270 unsigned DstReg = MI->getOperand(0).getReg();
271 unsigned SrcReg = MI->getOperand(1).getReg();
273 return X86::RFP80RegClass.contains(DstReg) ||
274 X86::RFP80RegClass.contains(SrcReg);
277 void setKillFlags(MachineBasicBlock &MBB) const;
282 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
284 /// getFPReg - Return the X86::FPx register number for the specified operand.
285 /// For example, this returns 3 for X86::FP3.
286 static unsigned getFPReg(const MachineOperand &MO) {
287 assert(MO.isReg() && "Expected an FP register!");
288 unsigned Reg = MO.getReg();
289 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
290 return Reg - X86::FP0;
293 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
294 /// register references into FP stack references.
296 bool FPS::runOnMachineFunction(MachineFunction &MF) {
297 // We only need to run this pass if there are any FP registers used in this
298 // function. If it is all integer, there is nothing for us to do!
299 bool FPIsUsed = false;
301 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
302 const MachineRegisterInfo &MRI = MF.getRegInfo();
303 for (unsigned i = 0; i <= 6; ++i)
304 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
310 if (!FPIsUsed) return false;
312 Bundles = &getAnalysis<EdgeBundles>();
313 TII = MF.getSubtarget().getInstrInfo();
315 // Prepare cross-MBB liveness.
320 // Process the function in depth first order so that we process at least one
321 // of the predecessors for every reachable block in the function.
322 SmallPtrSet<MachineBasicBlock*, 8> Processed;
323 MachineBasicBlock *Entry = MF.begin();
325 bool Changed = false;
326 for (MachineBasicBlock *BB : depth_first_ext(Entry, Processed))
327 Changed |= processBasicBlock(MF, *BB);
329 // Process any unreachable blocks in arbitrary order now.
330 if (MF.size() != Processed.size())
331 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
332 if (Processed.insert(BB).second)
333 Changed |= processBasicBlock(MF, *BB);
340 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and
341 /// live-out sets for the FP registers. Consistent means that the set of
342 /// registers live-out from a block is identical to the live-in set of all
343 /// successors. This is not enforced by the normal live-in lists since
344 /// registers may be implicitly defined, or not used by all successors.
345 void FPS::bundleCFG(MachineFunction &MF) {
346 assert(LiveBundles.empty() && "Stale data in LiveBundles");
347 LiveBundles.resize(Bundles->getNumBundles());
349 // Gather the actual live-in masks for all MBBs.
350 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
351 MachineBasicBlock *MBB = I;
352 const unsigned Mask = calcLiveInMask(MBB);
355 // Update MBB ingoing bundle mask.
356 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)].Mask |= Mask;
360 /// processBasicBlock - Loop over all of the instructions in the basic block,
361 /// transforming FP instructions into their stack form.
363 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
364 bool Changed = false;
370 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
371 MachineInstr *MI = I;
372 uint64_t Flags = MI->getDesc().TSFlags;
374 unsigned FPInstClass = Flags & X86II::FPTypeMask;
375 if (MI->isInlineAsm())
376 FPInstClass = X86II::SpecialFP;
378 if (MI->isCopy() && isFPCopy(MI))
379 FPInstClass = X86II::SpecialFP;
381 if (MI->isImplicitDef() &&
382 X86::RFP80RegClass.contains(MI->getOperand(0).getReg()))
383 FPInstClass = X86II::SpecialFP;
386 FPInstClass = X86II::SpecialFP;
388 if (FPInstClass == X86II::NotFP)
389 continue; // Efficiently ignore non-fp insts!
391 MachineInstr *PrevMI = nullptr;
393 PrevMI = std::prev(I);
395 ++NumFP; // Keep track of # of pseudo instrs
396 DEBUG(dbgs() << "\nFPInst:\t" << *MI);
398 // Get dead variables list now because the MI pointer may be deleted as part
400 SmallVector<unsigned, 8> DeadRegs;
401 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
402 const MachineOperand &MO = MI->getOperand(i);
403 if (MO.isReg() && MO.isDead())
404 DeadRegs.push_back(MO.getReg());
407 switch (FPInstClass) {
408 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
409 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
410 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
411 case X86II::TwoArgFP: handleTwoArgFP(I); break;
412 case X86II::CompareFP: handleCompareFP(I); break;
413 case X86II::CondMovFP: handleCondMovFP(I); break;
414 case X86II::SpecialFP: handleSpecialFP(I); break;
415 default: llvm_unreachable("Unknown FP Type!");
418 // Check to see if any of the values defined by this instruction are dead
419 // after definition. If so, pop them.
420 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
421 unsigned Reg = DeadRegs[i];
422 // Check if Reg is live on the stack. An inline-asm register operand that
423 // is in the clobber list and marked dead might not be live on the stack.
424 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
425 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
426 freeStackSlotAfter(I, Reg-X86::FP0);
430 // Print out all of the instructions expanded to if -debug
432 MachineBasicBlock::iterator PrevI(PrevMI);
434 dbgs() << "Just deleted pseudo instruction\n";
436 MachineBasicBlock::iterator Start = I;
437 // Rewind to first instruction newly inserted.
438 while (Start != BB.begin() && std::prev(Start) != PrevI) --Start;
439 dbgs() << "Inserted instructions:\n\t";
440 Start->print(dbgs());
441 while (++Start != std::next(I)) {}
455 /// setupBlockStack - Use the live bundles to set up our model of the stack
456 /// to match predecessors' live out stack.
457 void FPS::setupBlockStack() {
458 DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
459 << " derived from " << MBB->getName() << ".\n");
461 // Get the live-in bundle for MBB.
462 const LiveBundle &Bundle =
463 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)];
466 DEBUG(dbgs() << "Block has no FP live-ins.\n");
470 // Depth-first iteration should ensure that we always have an assigned stack.
471 assert(Bundle.isFixed() && "Reached block before any predecessors");
473 // Push the fixed live-in registers.
474 for (unsigned i = Bundle.FixCount; i > 0; --i) {
475 MBB->addLiveIn(X86::ST0+i-1);
476 DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
477 << unsigned(Bundle.FixStack[i-1]) << '\n');
478 pushReg(Bundle.FixStack[i-1]);
481 // Kill off unwanted live-ins. This can happen with a critical edge.
482 // FIXME: We could keep these live registers around as zombies. They may need
483 // to be revived at the end of a short block. It might save a few instrs.
484 adjustLiveRegs(calcLiveInMask(MBB), MBB->begin());
488 /// finishBlockStack - Revive live-outs that are implicitly defined out of
489 /// MBB. Shuffle live registers to match the expected fixed stack of any
490 /// predecessors, and ensure that all predecessors are expecting the same
492 void FPS::finishBlockStack() {
493 // The RET handling below takes care of return blocks for us.
494 if (MBB->succ_empty())
497 DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
498 << " derived from " << MBB->getName() << ".\n");
500 // Get MBB's live-out bundle.
501 unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true);
502 LiveBundle &Bundle = LiveBundles[BundleIdx];
504 // We may need to kill and define some registers to match successors.
505 // FIXME: This can probably be combined with the shuffle below.
506 MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
507 adjustLiveRegs(Bundle.Mask, Term);
510 DEBUG(dbgs() << "No live-outs.\n");
514 // Has the stack order been fixed yet?
515 DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
516 if (Bundle.isFixed()) {
517 DEBUG(dbgs() << "Shuffling stack to match.\n");
518 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
520 // Not fixed yet, we get to choose.
521 DEBUG(dbgs() << "Fixing stack order now.\n");
522 Bundle.FixCount = StackTop;
523 for (unsigned i = 0; i < StackTop; ++i)
524 Bundle.FixStack[i] = getStackEntry(i);
529 //===----------------------------------------------------------------------===//
530 // Efficient Lookup Table Support
531 //===----------------------------------------------------------------------===//
537 bool operator<(const TableEntry &TE) const { return from < TE.from; }
538 friend bool operator<(const TableEntry &TE, unsigned V) {
541 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V,
542 const TableEntry &TE) {
549 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
550 for (unsigned i = 0; i != NumEntries-1; ++i)
551 if (!(Table[i] < Table[i+1])) return false;
556 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
557 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
558 if (I != Table+N && I->from == Opcode)
564 #define ASSERT_SORTED(TABLE)
566 #define ASSERT_SORTED(TABLE) \
567 { static bool TABLE##Checked = false; \
568 if (!TABLE##Checked) { \
569 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
570 "All lookup tables must be sorted for efficient access!"); \
571 TABLE##Checked = true; \
576 //===----------------------------------------------------------------------===//
577 // Register File -> Register Stack Mapping Methods
578 //===----------------------------------------------------------------------===//
580 // OpcodeTable - Sorted map of register instructions to their stack version.
581 // The first element is an register file pseudo instruction, the second is the
582 // concrete X86 instruction which uses the register stack.
584 static const TableEntry OpcodeTable[] = {
585 { X86::ABS_Fp32 , X86::ABS_F },
586 { X86::ABS_Fp64 , X86::ABS_F },
587 { X86::ABS_Fp80 , X86::ABS_F },
588 { X86::ADD_Fp32m , X86::ADD_F32m },
589 { X86::ADD_Fp64m , X86::ADD_F64m },
590 { X86::ADD_Fp64m32 , X86::ADD_F32m },
591 { X86::ADD_Fp80m32 , X86::ADD_F32m },
592 { X86::ADD_Fp80m64 , X86::ADD_F64m },
593 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
594 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
595 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
596 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
597 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
598 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
599 { X86::CHS_Fp32 , X86::CHS_F },
600 { X86::CHS_Fp64 , X86::CHS_F },
601 { X86::CHS_Fp80 , X86::CHS_F },
602 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
603 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
604 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
605 { X86::CMOVB_Fp32 , X86::CMOVB_F },
606 { X86::CMOVB_Fp64 , X86::CMOVB_F },
607 { X86::CMOVB_Fp80 , X86::CMOVB_F },
608 { X86::CMOVE_Fp32 , X86::CMOVE_F },
609 { X86::CMOVE_Fp64 , X86::CMOVE_F },
610 { X86::CMOVE_Fp80 , X86::CMOVE_F },
611 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
612 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
613 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
614 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
615 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
616 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
617 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
618 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
619 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
620 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
621 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
622 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
623 { X86::CMOVP_Fp32 , X86::CMOVP_F },
624 { X86::CMOVP_Fp64 , X86::CMOVP_F },
625 { X86::CMOVP_Fp80 , X86::CMOVP_F },
626 { X86::COS_Fp32 , X86::COS_F },
627 { X86::COS_Fp64 , X86::COS_F },
628 { X86::COS_Fp80 , X86::COS_F },
629 { X86::DIVR_Fp32m , X86::DIVR_F32m },
630 { X86::DIVR_Fp64m , X86::DIVR_F64m },
631 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
632 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
633 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
634 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
635 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
636 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
637 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
638 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
639 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
640 { X86::DIV_Fp32m , X86::DIV_F32m },
641 { X86::DIV_Fp64m , X86::DIV_F64m },
642 { X86::DIV_Fp64m32 , X86::DIV_F32m },
643 { X86::DIV_Fp80m32 , X86::DIV_F32m },
644 { X86::DIV_Fp80m64 , X86::DIV_F64m },
645 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
646 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
647 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
648 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
649 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
650 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
651 { X86::ILD_Fp16m32 , X86::ILD_F16m },
652 { X86::ILD_Fp16m64 , X86::ILD_F16m },
653 { X86::ILD_Fp16m80 , X86::ILD_F16m },
654 { X86::ILD_Fp32m32 , X86::ILD_F32m },
655 { X86::ILD_Fp32m64 , X86::ILD_F32m },
656 { X86::ILD_Fp32m80 , X86::ILD_F32m },
657 { X86::ILD_Fp64m32 , X86::ILD_F64m },
658 { X86::ILD_Fp64m64 , X86::ILD_F64m },
659 { X86::ILD_Fp64m80 , X86::ILD_F64m },
660 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
661 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
662 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
663 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
664 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
665 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
666 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
667 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
668 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
669 { X86::IST_Fp16m32 , X86::IST_F16m },
670 { X86::IST_Fp16m64 , X86::IST_F16m },
671 { X86::IST_Fp16m80 , X86::IST_F16m },
672 { X86::IST_Fp32m32 , X86::IST_F32m },
673 { X86::IST_Fp32m64 , X86::IST_F32m },
674 { X86::IST_Fp32m80 , X86::IST_F32m },
675 { X86::IST_Fp64m32 , X86::IST_FP64m },
676 { X86::IST_Fp64m64 , X86::IST_FP64m },
677 { X86::IST_Fp64m80 , X86::IST_FP64m },
678 { X86::LD_Fp032 , X86::LD_F0 },
679 { X86::LD_Fp064 , X86::LD_F0 },
680 { X86::LD_Fp080 , X86::LD_F0 },
681 { X86::LD_Fp132 , X86::LD_F1 },
682 { X86::LD_Fp164 , X86::LD_F1 },
683 { X86::LD_Fp180 , X86::LD_F1 },
684 { X86::LD_Fp32m , X86::LD_F32m },
685 { X86::LD_Fp32m64 , X86::LD_F32m },
686 { X86::LD_Fp32m80 , X86::LD_F32m },
687 { X86::LD_Fp64m , X86::LD_F64m },
688 { X86::LD_Fp64m80 , X86::LD_F64m },
689 { X86::LD_Fp80m , X86::LD_F80m },
690 { X86::MUL_Fp32m , X86::MUL_F32m },
691 { X86::MUL_Fp64m , X86::MUL_F64m },
692 { X86::MUL_Fp64m32 , X86::MUL_F32m },
693 { X86::MUL_Fp80m32 , X86::MUL_F32m },
694 { X86::MUL_Fp80m64 , X86::MUL_F64m },
695 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
696 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
697 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
698 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
699 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
700 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
701 { X86::SIN_Fp32 , X86::SIN_F },
702 { X86::SIN_Fp64 , X86::SIN_F },
703 { X86::SIN_Fp80 , X86::SIN_F },
704 { X86::SQRT_Fp32 , X86::SQRT_F },
705 { X86::SQRT_Fp64 , X86::SQRT_F },
706 { X86::SQRT_Fp80 , X86::SQRT_F },
707 { X86::ST_Fp32m , X86::ST_F32m },
708 { X86::ST_Fp64m , X86::ST_F64m },
709 { X86::ST_Fp64m32 , X86::ST_F32m },
710 { X86::ST_Fp80m32 , X86::ST_F32m },
711 { X86::ST_Fp80m64 , X86::ST_F64m },
712 { X86::ST_FpP80m , X86::ST_FP80m },
713 { X86::SUBR_Fp32m , X86::SUBR_F32m },
714 { X86::SUBR_Fp64m , X86::SUBR_F64m },
715 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
716 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
717 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
718 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
719 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
720 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
721 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
722 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
723 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
724 { X86::SUB_Fp32m , X86::SUB_F32m },
725 { X86::SUB_Fp64m , X86::SUB_F64m },
726 { X86::SUB_Fp64m32 , X86::SUB_F32m },
727 { X86::SUB_Fp80m32 , X86::SUB_F32m },
728 { X86::SUB_Fp80m64 , X86::SUB_F64m },
729 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
730 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
731 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
732 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
733 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
734 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
735 { X86::TST_Fp32 , X86::TST_F },
736 { X86::TST_Fp64 , X86::TST_F },
737 { X86::TST_Fp80 , X86::TST_F },
738 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
739 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
740 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
741 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
742 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
743 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
746 static unsigned getConcreteOpcode(unsigned Opcode) {
747 ASSERT_SORTED(OpcodeTable);
748 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
749 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
753 //===----------------------------------------------------------------------===//
755 //===----------------------------------------------------------------------===//
757 // PopTable - Sorted map of instructions to their popping version. The first
758 // element is an instruction, the second is the version which pops.
760 static const TableEntry PopTable[] = {
761 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
763 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
764 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
766 { X86::IST_F16m , X86::IST_FP16m },
767 { X86::IST_F32m , X86::IST_FP32m },
769 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
771 { X86::ST_F32m , X86::ST_FP32m },
772 { X86::ST_F64m , X86::ST_FP64m },
773 { X86::ST_Frr , X86::ST_FPrr },
775 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
776 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
778 { X86::UCOM_FIr , X86::UCOM_FIPr },
780 { X86::UCOM_FPr , X86::UCOM_FPPr },
781 { X86::UCOM_Fr , X86::UCOM_FPr },
784 /// popStackAfter - Pop the current value off of the top of the FP stack after
785 /// the specified instruction. This attempts to be sneaky and combine the pop
786 /// into the instruction itself if possible. The iterator is left pointing to
787 /// the last instruction, be it a new pop instruction inserted, or the old
788 /// instruction if it was modified in place.
790 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
791 MachineInstr* MI = I;
792 DebugLoc dl = MI->getDebugLoc();
793 ASSERT_SORTED(PopTable);
795 report_fatal_error("Cannot pop empty stack!");
796 RegMap[Stack[--StackTop]] = ~0; // Update state
798 // Check to see if there is a popping version of this instruction...
799 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
801 I->setDesc(TII->get(Opcode));
802 if (Opcode == X86::UCOM_FPPr)
804 } else { // Insert an explicit pop
805 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
809 /// freeStackSlotAfter - Free the specified register from the register stack, so
810 /// that it is no longer in a register. If the register is currently at the top
811 /// of the stack, we just pop the current instruction, otherwise we store the
812 /// current top-of-stack into the specified slot, then pop the top of stack.
813 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
814 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
819 // Otherwise, store the top of stack into the dead slot, killing the operand
820 // without having to add in an explicit xchg then pop.
822 I = freeStackSlotBefore(++I, FPRegNo);
825 /// freeStackSlotBefore - Free the specified register without trying any
827 MachineBasicBlock::iterator
828 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
829 unsigned STReg = getSTReg(FPRegNo);
830 unsigned OldSlot = getSlot(FPRegNo);
831 unsigned TopReg = Stack[StackTop-1];
832 Stack[OldSlot] = TopReg;
833 RegMap[TopReg] = OldSlot;
834 RegMap[FPRegNo] = ~0;
835 Stack[--StackTop] = ~0;
836 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
841 /// adjustLiveRegs - Kill and revive registers such that exactly the FP
842 /// registers with a bit in Mask are live.
843 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
844 unsigned Defs = Mask;
846 for (unsigned i = 0; i < StackTop; ++i) {
847 unsigned RegNo = Stack[i];
848 if (!(Defs & (1 << RegNo)))
849 // This register is live, but we don't want it.
850 Kills |= (1 << RegNo);
852 // We don't need to imp-def this live register.
853 Defs &= ~(1 << RegNo);
855 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
857 // Produce implicit-defs for free by using killed registers.
858 while (Kills && Defs) {
859 unsigned KReg = countTrailingZeros(Kills);
860 unsigned DReg = countTrailingZeros(Defs);
861 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
862 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
863 std::swap(RegMap[KReg], RegMap[DReg]);
864 Kills &= ~(1 << KReg);
865 Defs &= ~(1 << DReg);
868 // Kill registers by popping.
869 if (Kills && I != MBB->begin()) {
870 MachineBasicBlock::iterator I2 = std::prev(I);
872 unsigned KReg = getStackEntry(0);
873 if (!(Kills & (1 << KReg)))
875 DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
877 Kills &= ~(1 << KReg);
881 // Manually kill the rest.
883 unsigned KReg = countTrailingZeros(Kills);
884 DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
885 freeStackSlotBefore(I, KReg);
886 Kills &= ~(1 << KReg);
889 // Load zeros for all the imp-defs.
891 unsigned DReg = countTrailingZeros(Defs);
892 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
893 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
895 Defs &= ~(1 << DReg);
898 // Now we should have the correct registers live.
900 assert(StackTop == countPopulation(Mask) && "Live count mismatch");
903 /// shuffleStackTop - emit fxch instructions before I to shuffle the top
904 /// FixCount entries into the order given by FixStack.
905 /// FIXME: Is there a better algorithm than insertion sort?
906 void FPS::shuffleStackTop(const unsigned char *FixStack,
908 MachineBasicBlock::iterator I) {
909 // Move items into place, starting from the desired stack bottom.
911 // Old register at position FixCount.
912 unsigned OldReg = getStackEntry(FixCount);
913 // Desired register at position FixCount.
914 unsigned Reg = FixStack[FixCount];
917 // (Reg st0) (OldReg st0) = (Reg OldReg st0)
920 moveToTop(OldReg, I);
926 //===----------------------------------------------------------------------===//
927 // Instruction transformation implementation
928 //===----------------------------------------------------------------------===//
930 void FPS::handleCall(MachineBasicBlock::iterator &I) {
931 unsigned STReturns = 0;
933 for (const auto &MO : I->operands()) {
937 unsigned R = MO.getReg() - X86::FP0;
940 assert(MO.isDef() && MO.isImplicit());
945 unsigned N = countTrailingOnes(STReturns);
947 // FP registers used for function return must be consecutive starting at
949 assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2));
951 for (unsigned I = 0; I < N; ++I)
955 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
957 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
958 MachineInstr *MI = I;
959 unsigned DestReg = getFPReg(MI->getOperand(0));
961 // Change from the pseudo instruction to the concrete instruction.
962 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
963 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
965 // Result gets pushed on the stack.
969 /// handleOneArgFP - fst <mem>, ST(0)
971 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
972 MachineInstr *MI = I;
973 unsigned NumOps = MI->getDesc().getNumOperands();
974 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
975 "Can only handle fst* & ftst instructions!");
977 // Is this the last use of the source register?
978 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
979 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
981 // FISTP64m is strange because there isn't a non-popping versions.
982 // If we have one _and_ we don't want to pop the operand, duplicate the value
983 // on the stack instead of moving it. This ensure that popping the value is
985 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
988 (MI->getOpcode() == X86::IST_Fp64m32 ||
989 MI->getOpcode() == X86::ISTT_Fp16m32 ||
990 MI->getOpcode() == X86::ISTT_Fp32m32 ||
991 MI->getOpcode() == X86::ISTT_Fp64m32 ||
992 MI->getOpcode() == X86::IST_Fp64m64 ||
993 MI->getOpcode() == X86::ISTT_Fp16m64 ||
994 MI->getOpcode() == X86::ISTT_Fp32m64 ||
995 MI->getOpcode() == X86::ISTT_Fp64m64 ||
996 MI->getOpcode() == X86::IST_Fp64m80 ||
997 MI->getOpcode() == X86::ISTT_Fp16m80 ||
998 MI->getOpcode() == X86::ISTT_Fp32m80 ||
999 MI->getOpcode() == X86::ISTT_Fp64m80 ||
1000 MI->getOpcode() == X86::ST_FpP80m)) {
1001 duplicateToTop(Reg, ScratchFPReg, I);
1003 moveToTop(Reg, I); // Move to the top of the stack...
1006 // Convert from the pseudo instruction to the concrete instruction.
1007 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
1008 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1010 if (MI->getOpcode() == X86::IST_FP64m ||
1011 MI->getOpcode() == X86::ISTT_FP16m ||
1012 MI->getOpcode() == X86::ISTT_FP32m ||
1013 MI->getOpcode() == X86::ISTT_FP64m ||
1014 MI->getOpcode() == X86::ST_FP80m) {
1016 report_fatal_error("Stack empty??");
1018 } else if (KillsSrc) { // Last use of operand?
1024 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
1025 /// replace the value with a newly computed value. These instructions may have
1026 /// non-fp operands after their FP operands.
1030 /// R1 = fadd R2, [mem]
1032 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
1033 MachineInstr *MI = I;
1035 unsigned NumOps = MI->getDesc().getNumOperands();
1036 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1039 // Is this the last use of the source register?
1040 unsigned Reg = getFPReg(MI->getOperand(1));
1041 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
1044 // If this is the last use of the source register, just make sure it's on
1045 // the top of the stack.
1048 report_fatal_error("Stack cannot be empty!");
1050 pushReg(getFPReg(MI->getOperand(0)));
1052 // If this is not the last use of the source register, _copy_ it to the top
1054 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
1057 // Change from the pseudo instruction to the concrete instruction.
1058 MI->RemoveOperand(1); // Drop the source operand.
1059 MI->RemoveOperand(0); // Drop the destination operand.
1060 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1064 //===----------------------------------------------------------------------===//
1065 // Define tables of various ways to map pseudo instructions
1068 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
1069 static const TableEntry ForwardST0Table[] = {
1070 { X86::ADD_Fp32 , X86::ADD_FST0r },
1071 { X86::ADD_Fp64 , X86::ADD_FST0r },
1072 { X86::ADD_Fp80 , X86::ADD_FST0r },
1073 { X86::DIV_Fp32 , X86::DIV_FST0r },
1074 { X86::DIV_Fp64 , X86::DIV_FST0r },
1075 { X86::DIV_Fp80 , X86::DIV_FST0r },
1076 { X86::MUL_Fp32 , X86::MUL_FST0r },
1077 { X86::MUL_Fp64 , X86::MUL_FST0r },
1078 { X86::MUL_Fp80 , X86::MUL_FST0r },
1079 { X86::SUB_Fp32 , X86::SUB_FST0r },
1080 { X86::SUB_Fp64 , X86::SUB_FST0r },
1081 { X86::SUB_Fp80 , X86::SUB_FST0r },
1084 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
1085 static const TableEntry ReverseST0Table[] = {
1086 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1087 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1088 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1089 { X86::DIV_Fp32 , X86::DIVR_FST0r },
1090 { X86::DIV_Fp64 , X86::DIVR_FST0r },
1091 { X86::DIV_Fp80 , X86::DIVR_FST0r },
1092 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1093 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1094 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1095 { X86::SUB_Fp32 , X86::SUBR_FST0r },
1096 { X86::SUB_Fp64 , X86::SUBR_FST0r },
1097 { X86::SUB_Fp80 , X86::SUBR_FST0r },
1100 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
1101 static const TableEntry ForwardSTiTable[] = {
1102 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1103 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1104 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1105 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1106 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1107 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1108 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1109 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1110 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1111 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1112 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1113 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1116 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
1117 static const TableEntry ReverseSTiTable[] = {
1118 { X86::ADD_Fp32 , X86::ADD_FrST0 },
1119 { X86::ADD_Fp64 , X86::ADD_FrST0 },
1120 { X86::ADD_Fp80 , X86::ADD_FrST0 },
1121 { X86::DIV_Fp32 , X86::DIV_FrST0 },
1122 { X86::DIV_Fp64 , X86::DIV_FrST0 },
1123 { X86::DIV_Fp80 , X86::DIV_FrST0 },
1124 { X86::MUL_Fp32 , X86::MUL_FrST0 },
1125 { X86::MUL_Fp64 , X86::MUL_FrST0 },
1126 { X86::MUL_Fp80 , X86::MUL_FrST0 },
1127 { X86::SUB_Fp32 , X86::SUB_FrST0 },
1128 { X86::SUB_Fp64 , X86::SUB_FrST0 },
1129 { X86::SUB_Fp80 , X86::SUB_FrST0 },
1133 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
1134 /// instructions which need to be simplified and possibly transformed.
1136 /// Result: ST(0) = fsub ST(0), ST(i)
1137 /// ST(i) = fsub ST(0), ST(i)
1138 /// ST(0) = fsubr ST(0), ST(i)
1139 /// ST(i) = fsubr ST(0), ST(i)
1141 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
1142 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1143 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1144 MachineInstr *MI = I;
1146 unsigned NumOperands = MI->getDesc().getNumOperands();
1147 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
1148 unsigned Dest = getFPReg(MI->getOperand(0));
1149 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1150 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1151 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1152 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1153 DebugLoc dl = MI->getDebugLoc();
1155 unsigned TOS = getStackEntry(0);
1157 // One of our operands must be on the top of the stack. If neither is yet, we
1158 // need to move one.
1159 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
1160 // We can choose to move either operand to the top of the stack. If one of
1161 // the operands is killed by this instruction, we want that one so that we
1162 // can update right on top of the old version.
1164 moveToTop(Op0, I); // Move dead operand to TOS.
1166 } else if (KillsOp1) {
1170 // All of the operands are live after this instruction executes, so we
1171 // cannot update on top of any operand. Because of this, we must
1172 // duplicate one of the stack elements to the top. It doesn't matter
1173 // which one we pick.
1175 duplicateToTop(Op0, Dest, I);
1179 } else if (!KillsOp0 && !KillsOp1) {
1180 // If we DO have one of our operands at the top of the stack, but we don't
1181 // have a dead operand, we must duplicate one of the operands to a new slot
1183 duplicateToTop(Op0, Dest, I);
1188 // Now we know that one of our operands is on the top of the stack, and at
1189 // least one of our operands is killed by this instruction.
1190 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
1191 "Stack conditions not set up right!");
1193 // We decide which form to use based on what is on the top of the stack, and
1194 // which operand is killed by this instruction.
1195 const TableEntry *InstTable;
1196 bool isForward = TOS == Op0;
1197 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
1200 InstTable = ForwardST0Table;
1202 InstTable = ReverseST0Table;
1205 InstTable = ForwardSTiTable;
1207 InstTable = ReverseSTiTable;
1210 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
1212 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
1214 // NotTOS - The register which is not on the top of stack...
1215 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
1217 // Replace the old instruction with a new instruction
1219 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1221 // If both operands are killed, pop one off of the stack in addition to
1222 // overwriting the other one.
1223 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
1224 assert(!updateST0 && "Should have updated other operand!");
1225 popStackAfter(I); // Pop the top of stack
1228 // Update stack information so that we know the destination register is now on
1230 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
1231 assert(UpdatedSlot < StackTop && Dest < 7);
1232 Stack[UpdatedSlot] = Dest;
1233 RegMap[Dest] = UpdatedSlot;
1234 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
1237 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
1238 /// register arguments and no explicit destinations.
1240 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
1241 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1242 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1243 MachineInstr *MI = I;
1245 unsigned NumOperands = MI->getDesc().getNumOperands();
1246 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
1247 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1248 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1249 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1250 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1252 // Make sure the first operand is on the top of stack, the other one can be
1256 // Change from the pseudo instruction to the concrete instruction.
1257 MI->getOperand(0).setReg(getSTReg(Op1));
1258 MI->RemoveOperand(1);
1259 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1261 // If any of the operands are killed by this instruction, free them.
1262 if (KillsOp0) freeStackSlotAfter(I, Op0);
1263 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
1266 /// handleCondMovFP - Handle two address conditional move instructions. These
1267 /// instructions move a st(i) register to st(0) iff a condition is true. These
1268 /// instructions require that the first operand is at the top of the stack, but
1269 /// otherwise don't modify the stack at all.
1270 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
1271 MachineInstr *MI = I;
1273 unsigned Op0 = getFPReg(MI->getOperand(0));
1274 unsigned Op1 = getFPReg(MI->getOperand(2));
1275 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1277 // The first operand *must* be on the top of the stack.
1280 // Change the second operand to the stack register that the operand is in.
1281 // Change from the pseudo instruction to the concrete instruction.
1282 MI->RemoveOperand(0);
1283 MI->RemoveOperand(1);
1284 MI->getOperand(0).setReg(getSTReg(Op1));
1285 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1287 // If we kill the second operand, make sure to pop it from the stack.
1288 if (Op0 != Op1 && KillsOp1) {
1289 // Get this value off of the register stack.
1290 freeStackSlotAfter(I, Op1);
1295 /// handleSpecialFP - Handle special instructions which behave unlike other
1296 /// floating point instructions. This is primarily intended for use by pseudo
1299 void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
1300 MachineInstr *MI = Inst;
1307 switch (MI->getOpcode()) {
1308 default: llvm_unreachable("Unknown SpecialFP instruction!");
1309 case TargetOpcode::COPY: {
1310 // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.
1311 const MachineOperand &MO1 = MI->getOperand(1);
1312 const MachineOperand &MO0 = MI->getOperand(0);
1313 bool KillsSrc = MI->killsRegister(MO1.getReg());
1316 unsigned DstFP = getFPReg(MO0);
1317 unsigned SrcFP = getFPReg(MO1);
1318 assert(isLive(SrcFP) && "Cannot copy dead register");
1320 // If the input operand is killed, we can just change the owner of the
1321 // incoming stack slot into the result.
1322 unsigned Slot = getSlot(SrcFP);
1323 Stack[Slot] = DstFP;
1324 RegMap[DstFP] = Slot;
1326 // For COPY we just duplicate the specified value to a new stack slot.
1327 // This could be made better, but would require substantial changes.
1328 duplicateToTop(SrcFP, DstFP, Inst);
1333 case TargetOpcode::IMPLICIT_DEF: {
1334 // All FP registers must be explicitly defined, so load a 0 instead.
1335 unsigned Reg = MI->getOperand(0).getReg() - X86::FP0;
1336 DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
1337 BuildMI(*MBB, Inst, MI->getDebugLoc(), TII->get(X86::LD_F0));
1342 case TargetOpcode::INLINEASM: {
1343 // The inline asm MachineInstr currently only *uses* FP registers for the
1344 // 'f' constraint. These should be turned into the current ST(x) register
1345 // in the machine instr.
1347 // There are special rules for x87 inline assembly. The compiler must know
1348 // exactly how many registers are popped and pushed implicitly by the asm.
1349 // Otherwise it is not possible to restore the stack state after the inline
1352 // There are 3 kinds of input operands:
1354 // 1. Popped inputs. These must appear at the stack top in ST0-STn. A
1355 // popped input operand must be in a fixed stack slot, and it is either
1356 // tied to an output operand, or in the clobber list. The MI has ST use
1357 // and def operands for these inputs.
1359 // 2. Fixed inputs. These inputs appear in fixed stack slots, but are
1360 // preserved by the inline asm. The fixed stack slots must be STn-STm
1361 // following the popped inputs. A fixed input operand cannot be tied to
1362 // an output or appear in the clobber list. The MI has ST use operands
1363 // and no defs for these inputs.
1365 // 3. Preserved inputs. These inputs use the "f" constraint which is
1366 // represented as an FP register. The inline asm won't change these
1369 // Outputs must be in ST registers, FP outputs are not allowed. Clobbered
1370 // registers do not count as output operands. The inline asm changes the
1371 // stack as if it popped all the popped inputs and then pushed all the
1374 // Scan the assembly for ST registers used, defined and clobbered. We can
1375 // only tell clobbers from defs by looking at the asm descriptor.
1376 unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
1377 unsigned NumOps = 0;
1378 SmallSet<unsigned, 1> FRegIdx;
1381 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
1382 i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) {
1383 unsigned Flags = MI->getOperand(i).getImm();
1385 NumOps = InlineAsm::getNumOperandRegisters(Flags);
1388 const MachineOperand &MO = MI->getOperand(i + 1);
1391 unsigned STReg = MO.getReg() - X86::FP0;
1395 // If the flag has a register class constraint, this must be an operand
1396 // with constraint "f". Record its index and continue.
1397 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
1398 FRegIdx.insert(i + 1);
1402 switch (InlineAsm::getKind(Flags)) {
1403 case InlineAsm::Kind_RegUse:
1404 STUses |= (1u << STReg);
1406 case InlineAsm::Kind_RegDef:
1407 case InlineAsm::Kind_RegDefEarlyClobber:
1408 STDefs |= (1u << STReg);
1410 STDeadDefs |= (1u << STReg);
1412 case InlineAsm::Kind_Clobber:
1413 STClobbers |= (1u << STReg);
1420 if (STUses && !isMask_32(STUses))
1421 MI->emitError("fixed input regs must be last on the x87 stack");
1422 unsigned NumSTUses = countTrailingOnes(STUses);
1424 // Defs must be contiguous from the stack top. ST0-STn.
1425 if (STDefs && !isMask_32(STDefs)) {
1426 MI->emitError("output regs must be last on the x87 stack");
1427 STDefs = NextPowerOf2(STDefs) - 1;
1429 unsigned NumSTDefs = countTrailingOnes(STDefs);
1431 // So must the clobbered stack slots. ST0-STm, m >= n.
1432 if (STClobbers && !isMask_32(STDefs | STClobbers))
1433 MI->emitError("clobbers must be last on the x87 stack");
1435 // Popped inputs are the ones that are also clobbered or defined.
1436 unsigned STPopped = STUses & (STDefs | STClobbers);
1437 if (STPopped && !isMask_32(STPopped))
1438 MI->emitError("implicitly popped regs must be last on the x87 stack");
1439 unsigned NumSTPopped = countTrailingOnes(STPopped);
1441 DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
1442 << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");
1445 // If any input operand uses constraint "f", all output register
1446 // constraints must be early-clobber defs.
1447 for (unsigned I = 0, E = MI->getNumOperands(); I < E; ++I)
1448 if (FRegIdx.count(I)) {
1449 assert((1 << getFPReg(MI->getOperand(I)) & STDefs) == 0 &&
1450 "Operands with constraint \"f\" cannot overlap with defs");
1454 // Collect all FP registers (register operands with constraints "t", "u",
1455 // and "f") to kill afer the instruction.
1456 unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
1457 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1458 MachineOperand &Op = MI->getOperand(i);
1459 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1461 unsigned FPReg = getFPReg(Op);
1463 // If we kill this operand, make sure to pop it from the stack after the
1464 // asm. We just remember it for now, and pop them all off at the end in
1466 if (Op.isUse() && Op.isKill())
1467 FPKills |= 1U << FPReg;
1470 // Do not include registers that are implicitly popped by defs/clobbers.
1471 FPKills &= ~(STDefs | STClobbers);
1473 // Now we can rearrange the live registers to match what was requested.
1474 unsigned char STUsesArray[8];
1476 for (unsigned I = 0; I < NumSTUses; ++I)
1479 shuffleStackTop(STUsesArray, NumSTUses, Inst);
1480 DEBUG({dbgs() << "Before asm: "; dumpStack();});
1482 // With the stack layout fixed, rewrite the FP registers.
1483 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1484 MachineOperand &Op = MI->getOperand(i);
1485 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1488 unsigned FPReg = getFPReg(Op);
1490 if (FRegIdx.count(i))
1491 // Operand with constraint "f".
1492 Op.setReg(getSTReg(FPReg));
1494 // Operand with a single register class constraint ("t" or "u").
1495 Op.setReg(X86::ST0 + FPReg);
1498 // Simulate the inline asm popping its inputs and pushing its outputs.
1499 StackTop -= NumSTPopped;
1501 for (unsigned i = 0; i < NumSTDefs; ++i)
1502 pushReg(NumSTDefs - i - 1);
1504 // If this asm kills any FP registers (is the last use of them) we must
1505 // explicitly emit pop instructions for them. Do this now after the asm has
1506 // executed so that the ST(x) numbers are not off (which would happen if we
1507 // did this inline with operand rewriting).
1509 // Note: this might be a non-optimal pop sequence. We might be able to do
1510 // better by trying to pop in stack order or something.
1512 unsigned FPReg = countTrailingZeros(FPKills);
1514 freeStackSlotAfter(Inst, FPReg);
1515 FPKills &= ~(1U << FPReg);
1518 // Don't delete the inline asm!
1526 // If RET has an FP register use operand, pass the first one in ST(0) and
1527 // the second one in ST(1).
1529 // Find the register operands.
1530 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1531 unsigned LiveMask = 0;
1533 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1534 MachineOperand &Op = MI->getOperand(i);
1535 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1537 // FP Register uses must be kills unless there are two uses of the same
1538 // register, in which case only one will be a kill.
1539 assert(Op.isUse() &&
1540 (Op.isKill() || // Marked kill.
1541 getFPReg(Op) == FirstFPRegOp || // Second instance.
1542 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1543 "Ret only defs operands, and values aren't live beyond it");
1545 if (FirstFPRegOp == ~0U)
1546 FirstFPRegOp = getFPReg(Op);
1548 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1549 SecondFPRegOp = getFPReg(Op);
1551 LiveMask |= (1 << getFPReg(Op));
1553 // Remove the operand so that later passes don't see it.
1554 MI->RemoveOperand(i);
1558 // We may have been carrying spurious live-ins, so make sure only the returned
1559 // registers are left live.
1560 adjustLiveRegs(LiveMask, MI);
1561 if (!LiveMask) return; // Quick check to see if any are possible.
1563 // There are only four possibilities here:
1564 // 1) we are returning a single FP value. In this case, it has to be in
1565 // ST(0) already, so just declare success by removing the value from the
1567 if (SecondFPRegOp == ~0U) {
1568 // Assert that the top of stack contains the right FP register.
1569 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1570 "Top of stack not the right register for RET!");
1572 // Ok, everything is good, mark the value as not being on the stack
1573 // anymore so that our assertion about the stack being empty at end of
1574 // block doesn't fire.
1579 // Otherwise, we are returning two values:
1580 // 2) If returning the same value for both, we only have one thing in the FP
1581 // stack. Consider: RET FP1, FP1
1582 if (StackTop == 1) {
1583 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1584 "Stack misconfiguration for RET!");
1586 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1587 // register to hold it.
1588 unsigned NewReg = ScratchFPReg;
1589 duplicateToTop(FirstFPRegOp, NewReg, MI);
1590 FirstFPRegOp = NewReg;
1593 /// Okay we know we have two different FPx operands now:
1594 assert(StackTop == 2 && "Must have two values live!");
1596 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1597 /// in ST(1). In this case, emit an fxch.
1598 if (getStackEntry(0) == SecondFPRegOp) {
1599 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1600 moveToTop(FirstFPRegOp, MI);
1603 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1604 /// ST(1). Just remove both from our understanding of the stack and return.
1605 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1606 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1611 Inst = MBB->erase(Inst); // Remove the pseudo instruction
1613 // We want to leave I pointing to the previous instruction, but what if we
1614 // just erased the first instruction?
1615 if (Inst == MBB->begin()) {
1616 DEBUG(dbgs() << "Inserting dummy KILL\n");
1617 Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
1622 void FPS::setKillFlags(MachineBasicBlock &MBB) const {
1623 const TargetRegisterInfo *TRI =
1624 MBB.getParent()->getSubtarget().getRegisterInfo();
1625 LivePhysRegs LPR(TRI);
1627 LPR.addLiveOuts(&MBB);
1629 for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
1631 if (I->isDebugValue())
1634 std::bitset<8> Defs;
1635 SmallVector<MachineOperand *, 2> Uses;
1636 MachineInstr &MI = *I;
1638 for (auto &MO : I->operands()) {
1642 unsigned Reg = MO.getReg() - X86::FP0;
1649 if (!LPR.contains(MO.getReg()))
1652 Uses.push_back(&MO);
1655 for (auto *MO : Uses)
1656 if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg()))
1659 LPR.stepBackward(MI);