1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "x86-codegen"
33 #include "X86InstrInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/ADT/DepthFirstIterator.h"
43 #include "llvm/ADT/SmallPtrSet.h"
44 #include "llvm/ADT/SmallVector.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/STLExtras.h"
50 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
51 STATISTIC(NumFP , "Number of floating point instructions");
54 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
56 FPS() : MachineFunctionPass(&ID) {}
58 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
59 AU.addPreservedID(MachineLoopInfoID);
60 AU.addPreservedID(MachineDominatorsID);
61 MachineFunctionPass::getAnalysisUsage(AU);
64 virtual bool runOnMachineFunction(MachineFunction &MF);
66 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
69 const TargetInstrInfo *TII; // Machine instruction info.
70 MachineBasicBlock *MBB; // Current basic block
71 unsigned Stack[8]; // FP<n> Registers in each stack slot...
72 unsigned RegMap[8]; // Track which stack slot contains each register
73 unsigned StackTop; // The current top of the FP stack.
75 void dumpStack() const {
76 cerr << "Stack contents:";
77 for (unsigned i = 0; i != StackTop; ++i) {
78 cerr << " FP" << Stack[i];
79 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
84 /// isStackEmpty - Return true if the FP stack is empty.
85 bool isStackEmpty() const {
89 // getSlot - Return the stack slot number a particular register number is
91 unsigned getSlot(unsigned RegNo) const {
92 assert(RegNo < 8 && "Regno out of range!");
96 // getStackEntry - Return the X86::FP<n> register in register ST(i).
97 unsigned getStackEntry(unsigned STi) const {
98 assert(STi < StackTop && "Access past stack top!");
99 return Stack[StackTop-1-STi];
102 // getSTReg - Return the X86::ST(i) register which contains the specified
103 // FP<RegNo> register.
104 unsigned getSTReg(unsigned RegNo) const {
105 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
108 // pushReg - Push the specified FP<n> register onto the stack.
109 void pushReg(unsigned Reg) {
110 assert(Reg < 8 && "Register number out of range!");
111 assert(StackTop < 8 && "Stack overflow!");
112 Stack[StackTop] = Reg;
113 RegMap[Reg] = StackTop++;
116 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
117 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
118 if (isAtTop(RegNo)) return;
120 unsigned STReg = getSTReg(RegNo);
121 unsigned RegOnTop = getStackEntry(0);
123 // Swap the slots the regs are in.
124 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
126 // Swap stack slot contents.
127 assert(RegMap[RegOnTop] < StackTop);
128 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
130 // Emit an fxch to update the runtime processors version of the state.
131 BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg);
135 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
136 unsigned STReg = getSTReg(RegNo);
137 pushReg(AsReg); // New register on top of stack
139 BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg);
142 // popStackAfter - Pop the current value off of the top of the FP stack
143 // after the specified instruction.
144 void popStackAfter(MachineBasicBlock::iterator &I);
146 // freeStackSlotAfter - Free the specified register from the register stack,
147 // so that it is no longer in a register. If the register is currently at
148 // the top of the stack, we just pop the current instruction, otherwise we
149 // store the current top-of-stack into the specified slot, then pop the top
151 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
153 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
155 void handleZeroArgFP(MachineBasicBlock::iterator &I);
156 void handleOneArgFP(MachineBasicBlock::iterator &I);
157 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
158 void handleTwoArgFP(MachineBasicBlock::iterator &I);
159 void handleCompareFP(MachineBasicBlock::iterator &I);
160 void handleCondMovFP(MachineBasicBlock::iterator &I);
161 void handleSpecialFP(MachineBasicBlock::iterator &I);
166 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
168 /// getFPReg - Return the X86::FPx register number for the specified operand.
169 /// For example, this returns 3 for X86::FP3.
170 static unsigned getFPReg(const MachineOperand &MO) {
171 assert(MO.isReg() && "Expected an FP register!");
172 unsigned Reg = MO.getReg();
173 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
174 return Reg - X86::FP0;
178 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
179 /// register references into FP stack references.
181 bool FPS::runOnMachineFunction(MachineFunction &MF) {
182 // We only need to run this pass if there are any FP registers used in this
183 // function. If it is all integer, there is nothing for us to do!
184 bool FPIsUsed = false;
186 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
187 for (unsigned i = 0; i <= 6; ++i)
188 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
194 if (!FPIsUsed) return false;
196 TII = MF.getTarget().getInstrInfo();
199 // Process the function in depth first order so that we process at least one
200 // of the predecessors for every reachable block in the function.
201 SmallPtrSet<MachineBasicBlock*, 8> Processed;
202 MachineBasicBlock *Entry = MF.begin();
204 bool Changed = false;
205 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
206 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
208 Changed |= processBasicBlock(MF, **I);
213 /// processBasicBlock - Loop over all of the instructions in the basic block,
214 /// transforming FP instructions into their stack form.
216 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
217 bool Changed = false;
220 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
221 MachineInstr *MI = I;
222 unsigned Flags = MI->getDesc().TSFlags;
224 unsigned FPInstClass = Flags & X86II::FPTypeMask;
225 if (MI->getOpcode() == TargetInstrInfo::INLINEASM)
226 FPInstClass = X86II::SpecialFP;
228 if (FPInstClass == X86II::NotFP)
229 continue; // Efficiently ignore non-fp insts!
231 MachineInstr *PrevMI = 0;
235 ++NumFP; // Keep track of # of pseudo instrs
236 DOUT << "\nFPInst:\t" << *MI;
238 // Get dead variables list now because the MI pointer may be deleted as part
240 SmallVector<unsigned, 8> DeadRegs;
241 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
242 const MachineOperand &MO = MI->getOperand(i);
243 if (MO.isReg() && MO.isDead())
244 DeadRegs.push_back(MO.getReg());
247 switch (FPInstClass) {
248 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
249 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
250 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
251 case X86II::TwoArgFP: handleTwoArgFP(I); break;
252 case X86II::CompareFP: handleCompareFP(I); break;
253 case X86II::CondMovFP: handleCondMovFP(I); break;
254 case X86II::SpecialFP: handleSpecialFP(I); break;
255 default: assert(0 && "Unknown FP Type!");
258 // Check to see if any of the values defined by this instruction are dead
259 // after definition. If so, pop them.
260 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
261 unsigned Reg = DeadRegs[i];
262 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
263 DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
264 freeStackSlotAfter(I, Reg-X86::FP0);
268 // Print out all of the instructions expanded to if -debug
270 MachineBasicBlock::iterator PrevI(PrevMI);
272 cerr << "Just deleted pseudo instruction\n";
274 MachineBasicBlock::iterator Start = I;
275 // Rewind to first instruction newly inserted.
276 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
277 cerr << "Inserted instructions:\n\t";
278 Start->print(*cerr.stream(), &MF.getTarget());
279 while (++Start != next(I)) {}
287 assert(isStackEmpty() && "Stack not empty at end of basic block?");
291 //===----------------------------------------------------------------------===//
292 // Efficient Lookup Table Support
293 //===----------------------------------------------------------------------===//
299 bool operator<(const TableEntry &TE) const { return from < TE.from; }
300 friend bool operator<(const TableEntry &TE, unsigned V) {
303 friend bool operator<(unsigned V, const TableEntry &TE) {
310 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
311 for (unsigned i = 0; i != NumEntries-1; ++i)
312 if (!(Table[i] < Table[i+1])) return false;
317 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
318 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
319 if (I != Table+N && I->from == Opcode)
325 #define ASSERT_SORTED(TABLE)
327 #define ASSERT_SORTED(TABLE) \
328 { static bool TABLE##Checked = false; \
329 if (!TABLE##Checked) { \
330 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
331 "All lookup tables must be sorted for efficient access!"); \
332 TABLE##Checked = true; \
337 //===----------------------------------------------------------------------===//
338 // Register File -> Register Stack Mapping Methods
339 //===----------------------------------------------------------------------===//
341 // OpcodeTable - Sorted map of register instructions to their stack version.
342 // The first element is an register file pseudo instruction, the second is the
343 // concrete X86 instruction which uses the register stack.
345 static const TableEntry OpcodeTable[] = {
346 { X86::ABS_Fp32 , X86::ABS_F },
347 { X86::ABS_Fp64 , X86::ABS_F },
348 { X86::ABS_Fp80 , X86::ABS_F },
349 { X86::ADD_Fp32m , X86::ADD_F32m },
350 { X86::ADD_Fp64m , X86::ADD_F64m },
351 { X86::ADD_Fp64m32 , X86::ADD_F32m },
352 { X86::ADD_Fp80m32 , X86::ADD_F32m },
353 { X86::ADD_Fp80m64 , X86::ADD_F64m },
354 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
355 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
356 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
357 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
358 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
359 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
360 { X86::CHS_Fp32 , X86::CHS_F },
361 { X86::CHS_Fp64 , X86::CHS_F },
362 { X86::CHS_Fp80 , X86::CHS_F },
363 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
364 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
365 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
366 { X86::CMOVB_Fp32 , X86::CMOVB_F },
367 { X86::CMOVB_Fp64 , X86::CMOVB_F },
368 { X86::CMOVB_Fp80 , X86::CMOVB_F },
369 { X86::CMOVE_Fp32 , X86::CMOVE_F },
370 { X86::CMOVE_Fp64 , X86::CMOVE_F },
371 { X86::CMOVE_Fp80 , X86::CMOVE_F },
372 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
373 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
374 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
375 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
376 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
377 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
378 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
379 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
380 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
381 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
382 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
383 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
384 { X86::CMOVP_Fp32 , X86::CMOVP_F },
385 { X86::CMOVP_Fp64 , X86::CMOVP_F },
386 { X86::CMOVP_Fp80 , X86::CMOVP_F },
387 { X86::COS_Fp32 , X86::COS_F },
388 { X86::COS_Fp64 , X86::COS_F },
389 { X86::COS_Fp80 , X86::COS_F },
390 { X86::DIVR_Fp32m , X86::DIVR_F32m },
391 { X86::DIVR_Fp64m , X86::DIVR_F64m },
392 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
393 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
394 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
395 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
396 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
397 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
398 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
399 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
400 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
401 { X86::DIV_Fp32m , X86::DIV_F32m },
402 { X86::DIV_Fp64m , X86::DIV_F64m },
403 { X86::DIV_Fp64m32 , X86::DIV_F32m },
404 { X86::DIV_Fp80m32 , X86::DIV_F32m },
405 { X86::DIV_Fp80m64 , X86::DIV_F64m },
406 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
407 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
408 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
409 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
410 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
411 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
412 { X86::ILD_Fp16m32 , X86::ILD_F16m },
413 { X86::ILD_Fp16m64 , X86::ILD_F16m },
414 { X86::ILD_Fp16m80 , X86::ILD_F16m },
415 { X86::ILD_Fp32m32 , X86::ILD_F32m },
416 { X86::ILD_Fp32m64 , X86::ILD_F32m },
417 { X86::ILD_Fp32m80 , X86::ILD_F32m },
418 { X86::ILD_Fp64m32 , X86::ILD_F64m },
419 { X86::ILD_Fp64m64 , X86::ILD_F64m },
420 { X86::ILD_Fp64m80 , X86::ILD_F64m },
421 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
422 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
423 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
424 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
425 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
426 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
427 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
428 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
429 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
430 { X86::IST_Fp16m32 , X86::IST_F16m },
431 { X86::IST_Fp16m64 , X86::IST_F16m },
432 { X86::IST_Fp16m80 , X86::IST_F16m },
433 { X86::IST_Fp32m32 , X86::IST_F32m },
434 { X86::IST_Fp32m64 , X86::IST_F32m },
435 { X86::IST_Fp32m80 , X86::IST_F32m },
436 { X86::IST_Fp64m32 , X86::IST_FP64m },
437 { X86::IST_Fp64m64 , X86::IST_FP64m },
438 { X86::IST_Fp64m80 , X86::IST_FP64m },
439 { X86::LD_Fp032 , X86::LD_F0 },
440 { X86::LD_Fp064 , X86::LD_F0 },
441 { X86::LD_Fp080 , X86::LD_F0 },
442 { X86::LD_Fp132 , X86::LD_F1 },
443 { X86::LD_Fp164 , X86::LD_F1 },
444 { X86::LD_Fp180 , X86::LD_F1 },
445 { X86::LD_Fp32m , X86::LD_F32m },
446 { X86::LD_Fp32m64 , X86::LD_F32m },
447 { X86::LD_Fp32m80 , X86::LD_F32m },
448 { X86::LD_Fp64m , X86::LD_F64m },
449 { X86::LD_Fp64m80 , X86::LD_F64m },
450 { X86::LD_Fp80m , X86::LD_F80m },
451 { X86::MUL_Fp32m , X86::MUL_F32m },
452 { X86::MUL_Fp64m , X86::MUL_F64m },
453 { X86::MUL_Fp64m32 , X86::MUL_F32m },
454 { X86::MUL_Fp80m32 , X86::MUL_F32m },
455 { X86::MUL_Fp80m64 , X86::MUL_F64m },
456 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
457 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
458 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
459 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
460 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
461 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
462 { X86::SIN_Fp32 , X86::SIN_F },
463 { X86::SIN_Fp64 , X86::SIN_F },
464 { X86::SIN_Fp80 , X86::SIN_F },
465 { X86::SQRT_Fp32 , X86::SQRT_F },
466 { X86::SQRT_Fp64 , X86::SQRT_F },
467 { X86::SQRT_Fp80 , X86::SQRT_F },
468 { X86::ST_Fp32m , X86::ST_F32m },
469 { X86::ST_Fp64m , X86::ST_F64m },
470 { X86::ST_Fp64m32 , X86::ST_F32m },
471 { X86::ST_Fp80m32 , X86::ST_F32m },
472 { X86::ST_Fp80m64 , X86::ST_F64m },
473 { X86::ST_FpP80m , X86::ST_FP80m },
474 { X86::SUBR_Fp32m , X86::SUBR_F32m },
475 { X86::SUBR_Fp64m , X86::SUBR_F64m },
476 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
477 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
478 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
479 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
480 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
481 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
482 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
483 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
484 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
485 { X86::SUB_Fp32m , X86::SUB_F32m },
486 { X86::SUB_Fp64m , X86::SUB_F64m },
487 { X86::SUB_Fp64m32 , X86::SUB_F32m },
488 { X86::SUB_Fp80m32 , X86::SUB_F32m },
489 { X86::SUB_Fp80m64 , X86::SUB_F64m },
490 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
491 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
492 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
493 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
494 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
495 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
496 { X86::TST_Fp32 , X86::TST_F },
497 { X86::TST_Fp64 , X86::TST_F },
498 { X86::TST_Fp80 , X86::TST_F },
499 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
500 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
501 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
502 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
503 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
504 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
507 static unsigned getConcreteOpcode(unsigned Opcode) {
508 ASSERT_SORTED(OpcodeTable);
509 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
510 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
514 //===----------------------------------------------------------------------===//
516 //===----------------------------------------------------------------------===//
518 // PopTable - Sorted map of instructions to their popping version. The first
519 // element is an instruction, the second is the version which pops.
521 static const TableEntry PopTable[] = {
522 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
524 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
525 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
527 { X86::IST_F16m , X86::IST_FP16m },
528 { X86::IST_F32m , X86::IST_FP32m },
530 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
532 { X86::ST_F32m , X86::ST_FP32m },
533 { X86::ST_F64m , X86::ST_FP64m },
534 { X86::ST_Frr , X86::ST_FPrr },
536 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
537 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
539 { X86::UCOM_FIr , X86::UCOM_FIPr },
541 { X86::UCOM_FPr , X86::UCOM_FPPr },
542 { X86::UCOM_Fr , X86::UCOM_FPr },
545 /// popStackAfter - Pop the current value off of the top of the FP stack after
546 /// the specified instruction. This attempts to be sneaky and combine the pop
547 /// into the instruction itself if possible. The iterator is left pointing to
548 /// the last instruction, be it a new pop instruction inserted, or the old
549 /// instruction if it was modified in place.
551 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
552 ASSERT_SORTED(PopTable);
553 assert(StackTop > 0 && "Cannot pop empty stack!");
554 RegMap[Stack[--StackTop]] = ~0; // Update state
556 // Check to see if there is a popping version of this instruction...
557 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
559 I->setDesc(TII->get(Opcode));
560 if (Opcode == X86::UCOM_FPPr)
562 } else { // Insert an explicit pop
563 I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
567 /// freeStackSlotAfter - Free the specified register from the register stack, so
568 /// that it is no longer in a register. If the register is currently at the top
569 /// of the stack, we just pop the current instruction, otherwise we store the
570 /// current top-of-stack into the specified slot, then pop the top of stack.
571 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
572 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
577 // Otherwise, store the top of stack into the dead slot, killing the operand
578 // without having to add in an explicit xchg then pop.
580 unsigned STReg = getSTReg(FPRegNo);
581 unsigned OldSlot = getSlot(FPRegNo);
582 unsigned TopReg = Stack[StackTop-1];
583 Stack[OldSlot] = TopReg;
584 RegMap[TopReg] = OldSlot;
585 RegMap[FPRegNo] = ~0;
586 Stack[--StackTop] = ~0;
587 I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg);
591 //===----------------------------------------------------------------------===//
592 // Instruction transformation implementation
593 //===----------------------------------------------------------------------===//
595 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
597 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
598 MachineInstr *MI = I;
599 unsigned DestReg = getFPReg(MI->getOperand(0));
601 // Change from the pseudo instruction to the concrete instruction.
602 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
603 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
605 // Result gets pushed on the stack.
609 /// handleOneArgFP - fst <mem>, ST(0)
611 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
612 MachineInstr *MI = I;
613 unsigned NumOps = MI->getDesc().getNumOperands();
614 assert((NumOps == 5 || NumOps == 1) &&
615 "Can only handle fst* & ftst instructions!");
617 // Is this the last use of the source register?
618 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
619 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
621 // FISTP64m is strange because there isn't a non-popping versions.
622 // If we have one _and_ we don't want to pop the operand, duplicate the value
623 // on the stack instead of moving it. This ensure that popping the value is
625 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
628 (MI->getOpcode() == X86::IST_Fp64m32 ||
629 MI->getOpcode() == X86::ISTT_Fp16m32 ||
630 MI->getOpcode() == X86::ISTT_Fp32m32 ||
631 MI->getOpcode() == X86::ISTT_Fp64m32 ||
632 MI->getOpcode() == X86::IST_Fp64m64 ||
633 MI->getOpcode() == X86::ISTT_Fp16m64 ||
634 MI->getOpcode() == X86::ISTT_Fp32m64 ||
635 MI->getOpcode() == X86::ISTT_Fp64m64 ||
636 MI->getOpcode() == X86::IST_Fp64m80 ||
637 MI->getOpcode() == X86::ISTT_Fp16m80 ||
638 MI->getOpcode() == X86::ISTT_Fp32m80 ||
639 MI->getOpcode() == X86::ISTT_Fp64m80 ||
640 MI->getOpcode() == X86::ST_FpP80m)) {
641 duplicateToTop(Reg, 7 /*temp register*/, I);
643 moveToTop(Reg, I); // Move to the top of the stack...
646 // Convert from the pseudo instruction to the concrete instruction.
647 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
648 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
650 if (MI->getOpcode() == X86::IST_FP64m ||
651 MI->getOpcode() == X86::ISTT_FP16m ||
652 MI->getOpcode() == X86::ISTT_FP32m ||
653 MI->getOpcode() == X86::ISTT_FP64m ||
654 MI->getOpcode() == X86::ST_FP80m) {
655 assert(StackTop > 0 && "Stack empty??");
657 } else if (KillsSrc) { // Last use of operand?
663 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
664 /// replace the value with a newly computed value. These instructions may have
665 /// non-fp operands after their FP operands.
669 /// R1 = fadd R2, [mem]
671 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
672 MachineInstr *MI = I;
674 unsigned NumOps = MI->getDesc().getNumOperands();
675 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
678 // Is this the last use of the source register?
679 unsigned Reg = getFPReg(MI->getOperand(1));
680 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
683 // If this is the last use of the source register, just make sure it's on
684 // the top of the stack.
686 assert(StackTop > 0 && "Stack cannot be empty!");
688 pushReg(getFPReg(MI->getOperand(0)));
690 // If this is not the last use of the source register, _copy_ it to the top
692 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
695 // Change from the pseudo instruction to the concrete instruction.
696 MI->RemoveOperand(1); // Drop the source operand.
697 MI->RemoveOperand(0); // Drop the destination operand.
698 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
702 //===----------------------------------------------------------------------===//
703 // Define tables of various ways to map pseudo instructions
706 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
707 static const TableEntry ForwardST0Table[] = {
708 { X86::ADD_Fp32 , X86::ADD_FST0r },
709 { X86::ADD_Fp64 , X86::ADD_FST0r },
710 { X86::ADD_Fp80 , X86::ADD_FST0r },
711 { X86::DIV_Fp32 , X86::DIV_FST0r },
712 { X86::DIV_Fp64 , X86::DIV_FST0r },
713 { X86::DIV_Fp80 , X86::DIV_FST0r },
714 { X86::MUL_Fp32 , X86::MUL_FST0r },
715 { X86::MUL_Fp64 , X86::MUL_FST0r },
716 { X86::MUL_Fp80 , X86::MUL_FST0r },
717 { X86::SUB_Fp32 , X86::SUB_FST0r },
718 { X86::SUB_Fp64 , X86::SUB_FST0r },
719 { X86::SUB_Fp80 , X86::SUB_FST0r },
722 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
723 static const TableEntry ReverseST0Table[] = {
724 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
725 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
726 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
727 { X86::DIV_Fp32 , X86::DIVR_FST0r },
728 { X86::DIV_Fp64 , X86::DIVR_FST0r },
729 { X86::DIV_Fp80 , X86::DIVR_FST0r },
730 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
731 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
732 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
733 { X86::SUB_Fp32 , X86::SUBR_FST0r },
734 { X86::SUB_Fp64 , X86::SUBR_FST0r },
735 { X86::SUB_Fp80 , X86::SUBR_FST0r },
738 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
739 static const TableEntry ForwardSTiTable[] = {
740 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
741 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
742 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
743 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
744 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
745 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
746 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
747 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
748 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
749 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
750 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
751 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
754 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
755 static const TableEntry ReverseSTiTable[] = {
756 { X86::ADD_Fp32 , X86::ADD_FrST0 },
757 { X86::ADD_Fp64 , X86::ADD_FrST0 },
758 { X86::ADD_Fp80 , X86::ADD_FrST0 },
759 { X86::DIV_Fp32 , X86::DIV_FrST0 },
760 { X86::DIV_Fp64 , X86::DIV_FrST0 },
761 { X86::DIV_Fp80 , X86::DIV_FrST0 },
762 { X86::MUL_Fp32 , X86::MUL_FrST0 },
763 { X86::MUL_Fp64 , X86::MUL_FrST0 },
764 { X86::MUL_Fp80 , X86::MUL_FrST0 },
765 { X86::SUB_Fp32 , X86::SUB_FrST0 },
766 { X86::SUB_Fp64 , X86::SUB_FrST0 },
767 { X86::SUB_Fp80 , X86::SUB_FrST0 },
771 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
772 /// instructions which need to be simplified and possibly transformed.
774 /// Result: ST(0) = fsub ST(0), ST(i)
775 /// ST(i) = fsub ST(0), ST(i)
776 /// ST(0) = fsubr ST(0), ST(i)
777 /// ST(i) = fsubr ST(0), ST(i)
779 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
780 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
781 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
782 MachineInstr *MI = I;
784 unsigned NumOperands = MI->getDesc().getNumOperands();
785 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
786 unsigned Dest = getFPReg(MI->getOperand(0));
787 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
788 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
789 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
790 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
792 unsigned TOS = getStackEntry(0);
794 // One of our operands must be on the top of the stack. If neither is yet, we
796 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
797 // We can choose to move either operand to the top of the stack. If one of
798 // the operands is killed by this instruction, we want that one so that we
799 // can update right on top of the old version.
801 moveToTop(Op0, I); // Move dead operand to TOS.
803 } else if (KillsOp1) {
807 // All of the operands are live after this instruction executes, so we
808 // cannot update on top of any operand. Because of this, we must
809 // duplicate one of the stack elements to the top. It doesn't matter
810 // which one we pick.
812 duplicateToTop(Op0, Dest, I);
816 } else if (!KillsOp0 && !KillsOp1) {
817 // If we DO have one of our operands at the top of the stack, but we don't
818 // have a dead operand, we must duplicate one of the operands to a new slot
820 duplicateToTop(Op0, Dest, I);
825 // Now we know that one of our operands is on the top of the stack, and at
826 // least one of our operands is killed by this instruction.
827 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
828 "Stack conditions not set up right!");
830 // We decide which form to use based on what is on the top of the stack, and
831 // which operand is killed by this instruction.
832 const TableEntry *InstTable;
833 bool isForward = TOS == Op0;
834 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
837 InstTable = ForwardST0Table;
839 InstTable = ReverseST0Table;
842 InstTable = ForwardSTiTable;
844 InstTable = ReverseSTiTable;
847 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
849 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
851 // NotTOS - The register which is not on the top of stack...
852 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
854 // Replace the old instruction with a new instruction
856 I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
858 // If both operands are killed, pop one off of the stack in addition to
859 // overwriting the other one.
860 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
861 assert(!updateST0 && "Should have updated other operand!");
862 popStackAfter(I); // Pop the top of stack
865 // Update stack information so that we know the destination register is now on
867 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
868 assert(UpdatedSlot < StackTop && Dest < 7);
869 Stack[UpdatedSlot] = Dest;
870 RegMap[Dest] = UpdatedSlot;
871 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
874 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
875 /// register arguments and no explicit destinations.
877 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
878 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
879 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
880 MachineInstr *MI = I;
882 unsigned NumOperands = MI->getDesc().getNumOperands();
883 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
884 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
885 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
886 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
887 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
889 // Make sure the first operand is on the top of stack, the other one can be
893 // Change from the pseudo instruction to the concrete instruction.
894 MI->getOperand(0).setReg(getSTReg(Op1));
895 MI->RemoveOperand(1);
896 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
898 // If any of the operands are killed by this instruction, free them.
899 if (KillsOp0) freeStackSlotAfter(I, Op0);
900 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
903 /// handleCondMovFP - Handle two address conditional move instructions. These
904 /// instructions move a st(i) register to st(0) iff a condition is true. These
905 /// instructions require that the first operand is at the top of the stack, but
906 /// otherwise don't modify the stack at all.
907 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
908 MachineInstr *MI = I;
910 unsigned Op0 = getFPReg(MI->getOperand(0));
911 unsigned Op1 = getFPReg(MI->getOperand(2));
912 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
914 // The first operand *must* be on the top of the stack.
917 // Change the second operand to the stack register that the operand is in.
918 // Change from the pseudo instruction to the concrete instruction.
919 MI->RemoveOperand(0);
920 MI->RemoveOperand(1);
921 MI->getOperand(0).setReg(getSTReg(Op1));
922 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
924 // If we kill the second operand, make sure to pop it from the stack.
925 if (Op0 != Op1 && KillsOp1) {
926 // Get this value off of the register stack.
927 freeStackSlotAfter(I, Op1);
932 /// handleSpecialFP - Handle special instructions which behave unlike other
933 /// floating point instructions. This is primarily intended for use by pseudo
936 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
937 MachineInstr *MI = I;
938 switch (MI->getOpcode()) {
939 default: assert(0 && "Unknown SpecialFP instruction!");
940 case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
941 case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
942 case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
943 assert(StackTop == 0 && "Stack should be empty after a call!");
944 pushReg(getFPReg(MI->getOperand(0)));
946 case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
947 case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
948 case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
949 // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
950 // The pattern we expect is:
955 // At this point, we've pushed FP1 on the top of stack, so it should be
956 // present if it isn't dead. If it was dead, we already emitted a pop to
957 // remove it from the stack and StackTop = 0.
959 // Push FP4 as top of stack next.
960 pushReg(getFPReg(MI->getOperand(0)));
962 // If StackTop was 0 before we pushed our operand, then ST(0) must have been
963 // dead. In this case, the ST(1) value is the only thing that is live, so
964 // it should be on the TOS (after the pop that was emitted) and is. Just
965 // continue in this case.
969 // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
970 // elements so that our accounting is correct.
971 unsigned RegOnTop = getStackEntry(0);
972 unsigned RegNo = getStackEntry(1);
974 // Swap the slots the regs are in.
975 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
977 // Swap stack slot contents.
978 assert(RegMap[RegOnTop] < StackTop);
979 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
982 case X86::FpSET_ST0_32:
983 case X86::FpSET_ST0_64:
984 case X86::FpSET_ST0_80:
985 assert(StackTop == 1 && "Stack should have one element on it to return!");
986 --StackTop; // "Forget" we have something on the top of stack!
988 case X86::MOV_Fp3232:
989 case X86::MOV_Fp3264:
990 case X86::MOV_Fp6432:
991 case X86::MOV_Fp6464:
992 case X86::MOV_Fp3280:
993 case X86::MOV_Fp6480:
994 case X86::MOV_Fp8032:
995 case X86::MOV_Fp8064:
996 case X86::MOV_Fp8080: {
997 unsigned SrcReg = getFPReg(MI->getOperand(1));
998 unsigned DestReg = getFPReg(MI->getOperand(0));
1000 if (MI->killsRegister(X86::FP0+SrcReg)) {
1001 // If the input operand is killed, we can just change the owner of the
1002 // incoming stack slot into the result.
1003 unsigned Slot = getSlot(SrcReg);
1004 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
1005 Stack[Slot] = DestReg;
1006 RegMap[DestReg] = Slot;
1009 // For FMOV we just duplicate the specified value to a new stack slot.
1010 // This could be made better, but would require substantial changes.
1011 duplicateToTop(SrcReg, DestReg, I);
1015 case TargetInstrInfo::INLINEASM: {
1016 // The inline asm MachineInstr currently only *uses* FP registers for the
1017 // 'f' constraint. These should be turned into the current ST(x) register
1018 // in the machine instr. Also, any kills should be explicitly popped after
1021 unsigned NumKills = 0;
1022 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1023 MachineOperand &Op = MI->getOperand(i);
1024 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1026 assert(Op.isUse() && "Only handle inline asm uses right now");
1028 unsigned FPReg = getFPReg(Op);
1029 Op.setReg(getSTReg(FPReg));
1031 // If we kill this operand, make sure to pop it from the stack after the
1032 // asm. We just remember it for now, and pop them all off at the end in
1035 Kills[NumKills++] = FPReg;
1038 // If this asm kills any FP registers (is the last use of them) we must
1039 // explicitly emit pop instructions for them. Do this now after the asm has
1040 // executed so that the ST(x) numbers are not off (which would happen if we
1041 // did this inline with operand rewriting).
1043 // Note: this might be a non-optimal pop sequence. We might be able to do
1044 // better by trying to pop in stack order or something.
1045 MachineBasicBlock::iterator InsertPt = MI;
1047 freeStackSlotAfter(InsertPt, Kills[--NumKills]);
1049 // Don't delete the inline asm!
1055 // If RET has an FP register use operand, pass the first one in ST(0) and
1056 // the second one in ST(1).
1057 if (isStackEmpty()) return; // Quick check to see if any are possible.
1059 // Find the register operands.
1060 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1062 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1063 MachineOperand &Op = MI->getOperand(i);
1064 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1066 // FP Register uses must be kills unless there are two uses of the same
1067 // register, in which case only one will be a kill.
1068 assert(Op.isUse() &&
1069 (Op.isKill() || // Marked kill.
1070 getFPReg(Op) == FirstFPRegOp || // Second instance.
1071 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1072 "Ret only defs operands, and values aren't live beyond it");
1074 if (FirstFPRegOp == ~0U)
1075 FirstFPRegOp = getFPReg(Op);
1077 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1078 SecondFPRegOp = getFPReg(Op);
1081 // Remove the operand so that later passes don't see it.
1082 MI->RemoveOperand(i);
1086 // There are only four possibilities here:
1087 // 1) we are returning a single FP value. In this case, it has to be in
1088 // ST(0) already, so just declare success by removing the value from the
1090 if (SecondFPRegOp == ~0U) {
1091 // Assert that the top of stack contains the right FP register.
1092 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1093 "Top of stack not the right register for RET!");
1095 // Ok, everything is good, mark the value as not being on the stack
1096 // anymore so that our assertion about the stack being empty at end of
1097 // block doesn't fire.
1102 // Otherwise, we are returning two values:
1103 // 2) If returning the same value for both, we only have one thing in the FP
1104 // stack. Consider: RET FP1, FP1
1105 if (StackTop == 1) {
1106 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1107 "Stack misconfiguration for RET!");
1109 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1110 // register to hold it.
1111 unsigned NewReg = (FirstFPRegOp+1)%7;
1112 duplicateToTop(FirstFPRegOp, NewReg, MI);
1113 FirstFPRegOp = NewReg;
1116 /// Okay we know we have two different FPx operands now:
1117 assert(StackTop == 2 && "Must have two values live!");
1119 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1120 /// in ST(1). In this case, emit an fxch.
1121 if (getStackEntry(0) == SecondFPRegOp) {
1122 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1123 moveToTop(FirstFPRegOp, MI);
1126 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1127 /// ST(1). Just remove both from our understanding of the stack and return.
1128 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1129 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1134 I = MBB->erase(I); // Remove the pseudo instruction