1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "x86-codegen"
33 #include "X86InstrInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/LiveVariables.h"
38 #include "llvm/CodeGen/Passes.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/ADT/DepthFirstIterator.h"
44 #include "llvm/ADT/SmallVector.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/STLExtras.h"
51 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
52 STATISTIC(NumFP , "Number of floating point instructions");
55 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
57 FPS() : MachineFunctionPass((intptr_t)&ID) {}
59 virtual bool runOnMachineFunction(MachineFunction &MF);
61 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 AU.addRequired<LiveVariables>();
65 MachineFunctionPass::getAnalysisUsage(AU);
68 const TargetInstrInfo *TII; // Machine instruction info.
69 LiveVariables *LV; // Live variable info for current function...
70 MachineBasicBlock *MBB; // Current basic block
71 unsigned Stack[8]; // FP<n> Registers in each stack slot...
72 unsigned RegMap[8]; // Track which stack slot contains each register
73 unsigned StackTop; // The current top of the FP stack.
75 void dumpStack() const {
76 cerr << "Stack contents:";
77 for (unsigned i = 0; i != StackTop; ++i) {
78 cerr << " FP" << Stack[i];
79 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
84 // getSlot - Return the stack slot number a particular register number is
86 unsigned getSlot(unsigned RegNo) const {
87 assert(RegNo < 8 && "Regno out of range!");
91 // getStackEntry - Return the X86::FP<n> register in register ST(i)
92 unsigned getStackEntry(unsigned STi) const {
93 assert(STi < StackTop && "Access past stack top!");
94 return Stack[StackTop-1-STi];
97 // getSTReg - Return the X86::ST(i) register which contains the specified
99 unsigned getSTReg(unsigned RegNo) const {
100 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
103 // pushReg - Push the specified FP<n> register onto the stack
104 void pushReg(unsigned Reg) {
105 assert(Reg < 8 && "Register number out of range!");
106 assert(StackTop < 8 && "Stack overflow!");
107 Stack[StackTop] = Reg;
108 RegMap[Reg] = StackTop++;
111 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
112 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
113 if (!isAtTop(RegNo)) {
114 unsigned STReg = getSTReg(RegNo);
115 unsigned RegOnTop = getStackEntry(0);
117 // Swap the slots the regs are in
118 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
120 // Swap stack slot contents
121 assert(RegMap[RegOnTop] < StackTop);
122 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
124 // Emit an fxch to update the runtime processors version of the state
125 BuildMI(*MBB, I, TII->get(X86::XCH_F)).addReg(STReg);
130 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
131 unsigned STReg = getSTReg(RegNo);
132 pushReg(AsReg); // New register on top of stack
134 BuildMI(*MBB, I, TII->get(X86::LD_Frr)).addReg(STReg);
137 // popStackAfter - Pop the current value off of the top of the FP stack
138 // after the specified instruction.
139 void popStackAfter(MachineBasicBlock::iterator &I);
141 // freeStackSlotAfter - Free the specified register from the register stack,
142 // so that it is no longer in a register. If the register is currently at
143 // the top of the stack, we just pop the current instruction, otherwise we
144 // store the current top-of-stack into the specified slot, then pop the top
146 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
148 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
150 void handleZeroArgFP(MachineBasicBlock::iterator &I);
151 void handleOneArgFP(MachineBasicBlock::iterator &I);
152 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
153 void handleTwoArgFP(MachineBasicBlock::iterator &I);
154 void handleCompareFP(MachineBasicBlock::iterator &I);
155 void handleCondMovFP(MachineBasicBlock::iterator &I);
156 void handleSpecialFP(MachineBasicBlock::iterator &I);
161 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
163 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
164 /// register references into FP stack references.
166 bool FPS::runOnMachineFunction(MachineFunction &MF) {
167 // We only need to run this pass if there are any FP registers used in this
168 // function. If it is all integer, there is nothing for us to do!
169 bool FPIsUsed = false;
171 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
172 for (unsigned i = 0; i <= 6; ++i)
173 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
179 if (!FPIsUsed) return false;
181 TII = MF.getTarget().getInstrInfo();
182 LV = &getAnalysis<LiveVariables>();
185 // Process the function in depth first order so that we process at least one
186 // of the predecessors for every reachable block in the function.
187 std::set<MachineBasicBlock*> Processed;
188 MachineBasicBlock *Entry = MF.begin();
190 bool Changed = false;
191 for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> >
192 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
194 Changed |= processBasicBlock(MF, **I);
199 /// processBasicBlock - Loop over all of the instructions in the basic block,
200 /// transforming FP instructions into their stack form.
202 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
203 bool Changed = false;
206 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
207 MachineInstr *MI = I;
208 unsigned Flags = MI->getDesc()->TSFlags;
209 if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
210 continue; // Efficiently ignore non-fp insts!
212 MachineInstr *PrevMI = 0;
216 ++NumFP; // Keep track of # of pseudo instrs
217 DOUT << "\nFPInst:\t" << *MI;
219 // Get dead variables list now because the MI pointer may be deleted as part
221 SmallVector<unsigned, 8> DeadRegs;
222 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
223 const MachineOperand &MO = MI->getOperand(i);
224 if (MO.isRegister() && MO.isDead())
225 DeadRegs.push_back(MO.getReg());
228 switch (Flags & X86II::FPTypeMask) {
229 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
230 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
231 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
232 case X86II::TwoArgFP: handleTwoArgFP(I); break;
233 case X86II::CompareFP: handleCompareFP(I); break;
234 case X86II::CondMovFP: handleCondMovFP(I); break;
235 case X86II::SpecialFP: handleSpecialFP(I); break;
236 default: assert(0 && "Unknown FP Type!");
239 // Check to see if any of the values defined by this instruction are dead
240 // after definition. If so, pop them.
241 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
242 unsigned Reg = DeadRegs[i];
243 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
244 DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
245 freeStackSlotAfter(I, Reg-X86::FP0);
249 // Print out all of the instructions expanded to if -debug
251 MachineBasicBlock::iterator PrevI(PrevMI);
253 cerr << "Just deleted pseudo instruction\n";
255 MachineBasicBlock::iterator Start = I;
256 // Rewind to first instruction newly inserted.
257 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
258 cerr << "Inserted instructions:\n\t";
259 Start->print(*cerr.stream(), &MF.getTarget());
260 while (++Start != next(I)) {}
268 assert(StackTop == 0 && "Stack not empty at end of basic block?");
272 //===----------------------------------------------------------------------===//
273 // Efficient Lookup Table Support
274 //===----------------------------------------------------------------------===//
280 bool operator<(const TableEntry &TE) const { return from < TE.from; }
281 friend bool operator<(const TableEntry &TE, unsigned V) {
284 friend bool operator<(unsigned V, const TableEntry &TE) {
290 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
291 for (unsigned i = 0; i != NumEntries-1; ++i)
292 if (!(Table[i] < Table[i+1])) return false;
296 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
297 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
298 if (I != Table+N && I->from == Opcode)
304 #define ASSERT_SORTED(TABLE)
306 #define ASSERT_SORTED(TABLE) \
307 { static bool TABLE##Checked = false; \
308 if (!TABLE##Checked) { \
309 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
310 "All lookup tables must be sorted for efficient access!"); \
311 TABLE##Checked = true; \
316 //===----------------------------------------------------------------------===//
317 // Register File -> Register Stack Mapping Methods
318 //===----------------------------------------------------------------------===//
320 // OpcodeTable - Sorted map of register instructions to their stack version.
321 // The first element is an register file pseudo instruction, the second is the
322 // concrete X86 instruction which uses the register stack.
324 static const TableEntry OpcodeTable[] = {
325 { X86::ABS_Fp32 , X86::ABS_F },
326 { X86::ABS_Fp64 , X86::ABS_F },
327 { X86::ABS_Fp80 , X86::ABS_F },
328 { X86::ADD_Fp32m , X86::ADD_F32m },
329 { X86::ADD_Fp64m , X86::ADD_F64m },
330 { X86::ADD_Fp64m32 , X86::ADD_F32m },
331 { X86::ADD_Fp80m32 , X86::ADD_F32m },
332 { X86::ADD_Fp80m64 , X86::ADD_F64m },
333 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
334 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
335 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
336 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
337 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
338 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
339 { X86::CHS_Fp32 , X86::CHS_F },
340 { X86::CHS_Fp64 , X86::CHS_F },
341 { X86::CHS_Fp80 , X86::CHS_F },
342 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
343 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
344 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
345 { X86::CMOVB_Fp32 , X86::CMOVB_F },
346 { X86::CMOVB_Fp64 , X86::CMOVB_F },
347 { X86::CMOVB_Fp80 , X86::CMOVB_F },
348 { X86::CMOVE_Fp32 , X86::CMOVE_F },
349 { X86::CMOVE_Fp64 , X86::CMOVE_F },
350 { X86::CMOVE_Fp80 , X86::CMOVE_F },
351 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
352 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
353 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
354 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
355 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
356 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
357 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
358 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
359 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
360 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
361 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
362 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
363 { X86::CMOVP_Fp32 , X86::CMOVP_F },
364 { X86::CMOVP_Fp64 , X86::CMOVP_F },
365 { X86::CMOVP_Fp80 , X86::CMOVP_F },
366 { X86::COS_Fp32 , X86::COS_F },
367 { X86::COS_Fp64 , X86::COS_F },
368 { X86::COS_Fp80 , X86::COS_F },
369 { X86::DIVR_Fp32m , X86::DIVR_F32m },
370 { X86::DIVR_Fp64m , X86::DIVR_F64m },
371 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
372 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
373 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
374 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
375 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
376 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
377 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
378 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
379 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
380 { X86::DIV_Fp32m , X86::DIV_F32m },
381 { X86::DIV_Fp64m , X86::DIV_F64m },
382 { X86::DIV_Fp64m32 , X86::DIV_F32m },
383 { X86::DIV_Fp80m32 , X86::DIV_F32m },
384 { X86::DIV_Fp80m64 , X86::DIV_F64m },
385 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
386 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
387 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
388 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
389 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
390 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
391 { X86::ILD_Fp16m32 , X86::ILD_F16m },
392 { X86::ILD_Fp16m64 , X86::ILD_F16m },
393 { X86::ILD_Fp16m80 , X86::ILD_F16m },
394 { X86::ILD_Fp32m32 , X86::ILD_F32m },
395 { X86::ILD_Fp32m64 , X86::ILD_F32m },
396 { X86::ILD_Fp32m80 , X86::ILD_F32m },
397 { X86::ILD_Fp64m32 , X86::ILD_F64m },
398 { X86::ILD_Fp64m64 , X86::ILD_F64m },
399 { X86::ILD_Fp64m80 , X86::ILD_F64m },
400 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
401 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
402 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
403 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
404 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
405 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
406 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
407 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
408 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
409 { X86::IST_Fp16m32 , X86::IST_F16m },
410 { X86::IST_Fp16m64 , X86::IST_F16m },
411 { X86::IST_Fp16m80 , X86::IST_F16m },
412 { X86::IST_Fp32m32 , X86::IST_F32m },
413 { X86::IST_Fp32m64 , X86::IST_F32m },
414 { X86::IST_Fp32m80 , X86::IST_F32m },
415 { X86::IST_Fp64m32 , X86::IST_FP64m },
416 { X86::IST_Fp64m64 , X86::IST_FP64m },
417 { X86::IST_Fp64m80 , X86::IST_FP64m },
418 { X86::LD_Fp032 , X86::LD_F0 },
419 { X86::LD_Fp064 , X86::LD_F0 },
420 { X86::LD_Fp080 , X86::LD_F0 },
421 { X86::LD_Fp132 , X86::LD_F1 },
422 { X86::LD_Fp164 , X86::LD_F1 },
423 { X86::LD_Fp180 , X86::LD_F1 },
424 { X86::LD_Fp32m , X86::LD_F32m },
425 { X86::LD_Fp32m64 , X86::LD_F32m },
426 { X86::LD_Fp32m80 , X86::LD_F32m },
427 { X86::LD_Fp64m , X86::LD_F64m },
428 { X86::LD_Fp64m80 , X86::LD_F64m },
429 { X86::LD_Fp80m , X86::LD_F80m },
430 { X86::MUL_Fp32m , X86::MUL_F32m },
431 { X86::MUL_Fp64m , X86::MUL_F64m },
432 { X86::MUL_Fp64m32 , X86::MUL_F32m },
433 { X86::MUL_Fp80m32 , X86::MUL_F32m },
434 { X86::MUL_Fp80m64 , X86::MUL_F64m },
435 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
436 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
437 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
438 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
439 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
440 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
441 { X86::SIN_Fp32 , X86::SIN_F },
442 { X86::SIN_Fp64 , X86::SIN_F },
443 { X86::SIN_Fp80 , X86::SIN_F },
444 { X86::SQRT_Fp32 , X86::SQRT_F },
445 { X86::SQRT_Fp64 , X86::SQRT_F },
446 { X86::SQRT_Fp80 , X86::SQRT_F },
447 { X86::ST_Fp32m , X86::ST_F32m },
448 { X86::ST_Fp64m , X86::ST_F64m },
449 { X86::ST_Fp64m32 , X86::ST_F32m },
450 { X86::ST_Fp80m32 , X86::ST_F32m },
451 { X86::ST_Fp80m64 , X86::ST_F64m },
452 { X86::ST_FpP80m , X86::ST_FP80m },
453 { X86::SUBR_Fp32m , X86::SUBR_F32m },
454 { X86::SUBR_Fp64m , X86::SUBR_F64m },
455 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
456 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
457 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
458 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
459 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
460 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
461 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
462 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
463 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
464 { X86::SUB_Fp32m , X86::SUB_F32m },
465 { X86::SUB_Fp64m , X86::SUB_F64m },
466 { X86::SUB_Fp64m32 , X86::SUB_F32m },
467 { X86::SUB_Fp80m32 , X86::SUB_F32m },
468 { X86::SUB_Fp80m64 , X86::SUB_F64m },
469 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
470 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
471 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
472 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
473 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
474 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
475 { X86::TST_Fp32 , X86::TST_F },
476 { X86::TST_Fp64 , X86::TST_F },
477 { X86::TST_Fp80 , X86::TST_F },
478 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
479 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
480 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
481 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
482 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
483 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
486 static unsigned getConcreteOpcode(unsigned Opcode) {
487 ASSERT_SORTED(OpcodeTable);
488 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
489 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
493 //===----------------------------------------------------------------------===//
495 //===----------------------------------------------------------------------===//
497 // PopTable - Sorted map of instructions to their popping version. The first
498 // element is an instruction, the second is the version which pops.
500 static const TableEntry PopTable[] = {
501 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
503 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
504 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
506 { X86::IST_F16m , X86::IST_FP16m },
507 { X86::IST_F32m , X86::IST_FP32m },
509 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
511 { X86::ST_F32m , X86::ST_FP32m },
512 { X86::ST_F64m , X86::ST_FP64m },
513 { X86::ST_Frr , X86::ST_FPrr },
515 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
516 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
518 { X86::UCOM_FIr , X86::UCOM_FIPr },
520 { X86::UCOM_FPr , X86::UCOM_FPPr },
521 { X86::UCOM_Fr , X86::UCOM_FPr },
524 /// popStackAfter - Pop the current value off of the top of the FP stack after
525 /// the specified instruction. This attempts to be sneaky and combine the pop
526 /// into the instruction itself if possible. The iterator is left pointing to
527 /// the last instruction, be it a new pop instruction inserted, or the old
528 /// instruction if it was modified in place.
530 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
531 ASSERT_SORTED(PopTable);
532 assert(StackTop > 0 && "Cannot pop empty stack!");
533 RegMap[Stack[--StackTop]] = ~0; // Update state
535 // Check to see if there is a popping version of this instruction...
536 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
538 I->setInstrDescriptor(TII->get(Opcode));
539 if (Opcode == X86::UCOM_FPPr)
541 } else { // Insert an explicit pop
542 I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
546 /// freeStackSlotAfter - Free the specified register from the register stack, so
547 /// that it is no longer in a register. If the register is currently at the top
548 /// of the stack, we just pop the current instruction, otherwise we store the
549 /// current top-of-stack into the specified slot, then pop the top of stack.
550 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
551 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
556 // Otherwise, store the top of stack into the dead slot, killing the operand
557 // without having to add in an explicit xchg then pop.
559 unsigned STReg = getSTReg(FPRegNo);
560 unsigned OldSlot = getSlot(FPRegNo);
561 unsigned TopReg = Stack[StackTop-1];
562 Stack[OldSlot] = TopReg;
563 RegMap[TopReg] = OldSlot;
564 RegMap[FPRegNo] = ~0;
565 Stack[--StackTop] = ~0;
566 I = BuildMI(*MBB, ++I, TII->get(X86::ST_FPrr)).addReg(STReg);
570 static unsigned getFPReg(const MachineOperand &MO) {
571 assert(MO.isRegister() && "Expected an FP register!");
572 unsigned Reg = MO.getReg();
573 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
574 return Reg - X86::FP0;
578 //===----------------------------------------------------------------------===//
579 // Instruction transformation implementation
580 //===----------------------------------------------------------------------===//
582 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
584 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
585 MachineInstr *MI = I;
586 unsigned DestReg = getFPReg(MI->getOperand(0));
588 // Change from the pseudo instruction to the concrete instruction.
589 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
590 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
592 // Result gets pushed on the stack.
596 /// handleOneArgFP - fst <mem>, ST(0)
598 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
599 MachineInstr *MI = I;
600 unsigned NumOps = MI->getDesc()->getNumOperands();
601 assert((NumOps == 5 || NumOps == 1) &&
602 "Can only handle fst* & ftst instructions!");
604 // Is this the last use of the source register?
605 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
606 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
608 // FISTP64m is strange because there isn't a non-popping versions.
609 // If we have one _and_ we don't want to pop the operand, duplicate the value
610 // on the stack instead of moving it. This ensure that popping the value is
612 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
615 (MI->getOpcode() == X86::IST_Fp64m32 ||
616 MI->getOpcode() == X86::ISTT_Fp16m32 ||
617 MI->getOpcode() == X86::ISTT_Fp32m32 ||
618 MI->getOpcode() == X86::ISTT_Fp64m32 ||
619 MI->getOpcode() == X86::IST_Fp64m64 ||
620 MI->getOpcode() == X86::ISTT_Fp16m64 ||
621 MI->getOpcode() == X86::ISTT_Fp32m64 ||
622 MI->getOpcode() == X86::ISTT_Fp64m64 ||
623 MI->getOpcode() == X86::IST_Fp64m80 ||
624 MI->getOpcode() == X86::ISTT_Fp16m80 ||
625 MI->getOpcode() == X86::ISTT_Fp32m80 ||
626 MI->getOpcode() == X86::ISTT_Fp64m80 ||
627 MI->getOpcode() == X86::ST_FpP80m)) {
628 duplicateToTop(Reg, 7 /*temp register*/, I);
630 moveToTop(Reg, I); // Move to the top of the stack...
633 // Convert from the pseudo instruction to the concrete instruction.
634 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
635 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
637 if (MI->getOpcode() == X86::IST_FP64m ||
638 MI->getOpcode() == X86::ISTT_FP16m ||
639 MI->getOpcode() == X86::ISTT_FP32m ||
640 MI->getOpcode() == X86::ISTT_FP64m ||
641 MI->getOpcode() == X86::ST_FP80m) {
642 assert(StackTop > 0 && "Stack empty??");
644 } else if (KillsSrc) { // Last use of operand?
650 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
651 /// replace the value with a newly computed value. These instructions may have
652 /// non-fp operands after their FP operands.
656 /// R1 = fadd R2, [mem]
658 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
659 MachineInstr *MI = I;
660 unsigned NumOps = MI->getDesc()->getNumOperands();
661 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
663 // Is this the last use of the source register?
664 unsigned Reg = getFPReg(MI->getOperand(1));
665 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
668 // If this is the last use of the source register, just make sure it's on
669 // the top of the stack.
671 assert(StackTop > 0 && "Stack cannot be empty!");
673 pushReg(getFPReg(MI->getOperand(0)));
675 // If this is not the last use of the source register, _copy_ it to the top
677 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
680 // Change from the pseudo instruction to the concrete instruction.
681 MI->RemoveOperand(1); // Drop the source operand.
682 MI->RemoveOperand(0); // Drop the destination operand.
683 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
687 //===----------------------------------------------------------------------===//
688 // Define tables of various ways to map pseudo instructions
691 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
692 static const TableEntry ForwardST0Table[] = {
693 { X86::ADD_Fp32 , X86::ADD_FST0r },
694 { X86::ADD_Fp64 , X86::ADD_FST0r },
695 { X86::ADD_Fp80 , X86::ADD_FST0r },
696 { X86::DIV_Fp32 , X86::DIV_FST0r },
697 { X86::DIV_Fp64 , X86::DIV_FST0r },
698 { X86::DIV_Fp80 , X86::DIV_FST0r },
699 { X86::MUL_Fp32 , X86::MUL_FST0r },
700 { X86::MUL_Fp64 , X86::MUL_FST0r },
701 { X86::MUL_Fp80 , X86::MUL_FST0r },
702 { X86::SUB_Fp32 , X86::SUB_FST0r },
703 { X86::SUB_Fp64 , X86::SUB_FST0r },
704 { X86::SUB_Fp80 , X86::SUB_FST0r },
707 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
708 static const TableEntry ReverseST0Table[] = {
709 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
710 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
711 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
712 { X86::DIV_Fp32 , X86::DIVR_FST0r },
713 { X86::DIV_Fp64 , X86::DIVR_FST0r },
714 { X86::DIV_Fp80 , X86::DIVR_FST0r },
715 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
716 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
717 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
718 { X86::SUB_Fp32 , X86::SUBR_FST0r },
719 { X86::SUB_Fp64 , X86::SUBR_FST0r },
720 { X86::SUB_Fp80 , X86::SUBR_FST0r },
723 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
724 static const TableEntry ForwardSTiTable[] = {
725 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
726 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
727 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
728 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
729 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
730 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
731 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
732 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
733 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
734 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
735 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
736 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
739 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
740 static const TableEntry ReverseSTiTable[] = {
741 { X86::ADD_Fp32 , X86::ADD_FrST0 },
742 { X86::ADD_Fp64 , X86::ADD_FrST0 },
743 { X86::ADD_Fp80 , X86::ADD_FrST0 },
744 { X86::DIV_Fp32 , X86::DIV_FrST0 },
745 { X86::DIV_Fp64 , X86::DIV_FrST0 },
746 { X86::DIV_Fp80 , X86::DIV_FrST0 },
747 { X86::MUL_Fp32 , X86::MUL_FrST0 },
748 { X86::MUL_Fp64 , X86::MUL_FrST0 },
749 { X86::MUL_Fp80 , X86::MUL_FrST0 },
750 { X86::SUB_Fp32 , X86::SUB_FrST0 },
751 { X86::SUB_Fp64 , X86::SUB_FrST0 },
752 { X86::SUB_Fp80 , X86::SUB_FrST0 },
756 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
757 /// instructions which need to be simplified and possibly transformed.
759 /// Result: ST(0) = fsub ST(0), ST(i)
760 /// ST(i) = fsub ST(0), ST(i)
761 /// ST(0) = fsubr ST(0), ST(i)
762 /// ST(i) = fsubr ST(0), ST(i)
764 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
765 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
766 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
767 MachineInstr *MI = I;
769 unsigned NumOperands = MI->getDesc()->getNumOperands();
770 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
771 unsigned Dest = getFPReg(MI->getOperand(0));
772 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
773 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
774 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
775 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
777 unsigned TOS = getStackEntry(0);
779 // One of our operands must be on the top of the stack. If neither is yet, we
781 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
782 // We can choose to move either operand to the top of the stack. If one of
783 // the operands is killed by this instruction, we want that one so that we
784 // can update right on top of the old version.
786 moveToTop(Op0, I); // Move dead operand to TOS.
788 } else if (KillsOp1) {
792 // All of the operands are live after this instruction executes, so we
793 // cannot update on top of any operand. Because of this, we must
794 // duplicate one of the stack elements to the top. It doesn't matter
795 // which one we pick.
797 duplicateToTop(Op0, Dest, I);
801 } else if (!KillsOp0 && !KillsOp1) {
802 // If we DO have one of our operands at the top of the stack, but we don't
803 // have a dead operand, we must duplicate one of the operands to a new slot
805 duplicateToTop(Op0, Dest, I);
810 // Now we know that one of our operands is on the top of the stack, and at
811 // least one of our operands is killed by this instruction.
812 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
813 "Stack conditions not set up right!");
815 // We decide which form to use based on what is on the top of the stack, and
816 // which operand is killed by this instruction.
817 const TableEntry *InstTable;
818 bool isForward = TOS == Op0;
819 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
822 InstTable = ForwardST0Table;
824 InstTable = ReverseST0Table;
827 InstTable = ForwardSTiTable;
829 InstTable = ReverseSTiTable;
832 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
834 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
836 // NotTOS - The register which is not on the top of stack...
837 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
839 // Replace the old instruction with a new instruction
841 I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
843 // If both operands are killed, pop one off of the stack in addition to
844 // overwriting the other one.
845 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
846 assert(!updateST0 && "Should have updated other operand!");
847 popStackAfter(I); // Pop the top of stack
850 // Update stack information so that we know the destination register is now on
852 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
853 assert(UpdatedSlot < StackTop && Dest < 7);
854 Stack[UpdatedSlot] = Dest;
855 RegMap[Dest] = UpdatedSlot;
856 delete MI; // Remove the old instruction
859 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
860 /// register arguments and no explicit destinations.
862 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
863 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
864 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
865 MachineInstr *MI = I;
867 unsigned NumOperands = MI->getDesc()->getNumOperands();
868 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
869 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
870 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
871 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
872 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
874 // Make sure the first operand is on the top of stack, the other one can be
878 // Change from the pseudo instruction to the concrete instruction.
879 MI->getOperand(0).setReg(getSTReg(Op1));
880 MI->RemoveOperand(1);
881 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
883 // If any of the operands are killed by this instruction, free them.
884 if (KillsOp0) freeStackSlotAfter(I, Op0);
885 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
888 /// handleCondMovFP - Handle two address conditional move instructions. These
889 /// instructions move a st(i) register to st(0) iff a condition is true. These
890 /// instructions require that the first operand is at the top of the stack, but
891 /// otherwise don't modify the stack at all.
892 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
893 MachineInstr *MI = I;
895 unsigned Op0 = getFPReg(MI->getOperand(0));
896 unsigned Op1 = getFPReg(MI->getOperand(2));
897 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
899 // The first operand *must* be on the top of the stack.
902 // Change the second operand to the stack register that the operand is in.
903 // Change from the pseudo instruction to the concrete instruction.
904 MI->RemoveOperand(0);
905 MI->RemoveOperand(1);
906 MI->getOperand(0).setReg(getSTReg(Op1));
907 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
909 // If we kill the second operand, make sure to pop it from the stack.
910 if (Op0 != Op1 && KillsOp1) {
911 // Get this value off of the register stack.
912 freeStackSlotAfter(I, Op1);
917 /// handleSpecialFP - Handle special instructions which behave unlike other
918 /// floating point instructions. This is primarily intended for use by pseudo
921 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
922 MachineInstr *MI = I;
923 switch (MI->getOpcode()) {
924 default: assert(0 && "Unknown SpecialFP instruction!");
925 case X86::FpGETRESULT32: // Appears immediately after a call returning FP type!
926 case X86::FpGETRESULT64: // Appears immediately after a call returning FP type!
927 case X86::FpGETRESULT80:
928 assert(StackTop == 0 && "Stack should be empty after a call!");
929 pushReg(getFPReg(MI->getOperand(0)));
931 case X86::FpSETRESULT32:
932 case X86::FpSETRESULT64:
933 case X86::FpSETRESULT80:
934 assert(StackTop == 1 && "Stack should have one element on it to return!");
935 --StackTop; // "Forget" we have something on the top of stack!
937 case X86::MOV_Fp3232:
938 case X86::MOV_Fp3264:
939 case X86::MOV_Fp6432:
940 case X86::MOV_Fp6464:
941 case X86::MOV_Fp3280:
942 case X86::MOV_Fp6480:
943 case X86::MOV_Fp8032:
944 case X86::MOV_Fp8064:
945 case X86::MOV_Fp8080: {
946 unsigned SrcReg = getFPReg(MI->getOperand(1));
947 unsigned DestReg = getFPReg(MI->getOperand(0));
949 if (LV->KillsRegister(MI, X86::FP0+SrcReg)) {
950 // If the input operand is killed, we can just change the owner of the
951 // incoming stack slot into the result.
952 unsigned Slot = getSlot(SrcReg);
953 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
954 Stack[Slot] = DestReg;
955 RegMap[DestReg] = Slot;
958 // For FMOV we just duplicate the specified value to a new stack slot.
959 // This could be made better, but would require substantial changes.
960 duplicateToTop(SrcReg, DestReg, I);
966 I = MBB->erase(I); // Remove the pseudo instruction