1 //===-- FloatingPoint.cpp - Floating point Reg -> Stack converter ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "fp"
33 #include "X86InstrInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/LiveVariables.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Function.h" // FIXME: remove when using MBB CFG!
41 #include "llvm/Support/CFG.h" // FIXME: remove when using MBB CFG!
42 #include "Support/Debug.h"
43 #include "Support/DepthFirstIterator.h"
44 #include "Support/Statistic.h"
45 #include "Support/STLExtras.h"
51 Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
52 Statistic<> NumFP ("x86-codegen", "Number of floating point instructions");
54 struct FPS : public MachineFunctionPass {
55 virtual bool runOnMachineFunction(MachineFunction &MF);
57 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
59 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
60 AU.addRequired<LiveVariables>();
61 MachineFunctionPass::getAnalysisUsage(AU);
64 LiveVariables *LV; // Live variable info for current function...
65 MachineBasicBlock *MBB; // Current basic block
66 unsigned Stack[8]; // FP<n> Registers in each stack slot...
67 unsigned RegMap[8]; // Track which stack slot contains each register
68 unsigned StackTop; // The current top of the FP stack.
70 void dumpStack() const {
71 std::cerr << "Stack contents:";
72 for (unsigned i = 0; i != StackTop; ++i) {
73 std::cerr << " FP" << Stack[i];
74 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
79 // getSlot - Return the stack slot number a particular register number is
81 unsigned getSlot(unsigned RegNo) const {
82 assert(RegNo < 8 && "Regno out of range!");
86 // getStackEntry - Return the X86::FP<n> register in register ST(i)
87 unsigned getStackEntry(unsigned STi) const {
88 assert(STi < StackTop && "Access past stack top!");
89 return Stack[StackTop-1-STi];
92 // getSTReg - Return the X86::ST(i) register which contains the specified
94 unsigned getSTReg(unsigned RegNo) const {
95 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
98 // pushReg - Push the specified FP<n> register onto the stack
99 void pushReg(unsigned Reg) {
100 assert(Reg < 8 && "Register number out of range!");
101 assert(StackTop < 8 && "Stack overflow!");
102 Stack[StackTop] = Reg;
103 RegMap[Reg] = StackTop++;
106 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
107 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
108 if (!isAtTop(RegNo)) {
109 unsigned Slot = getSlot(RegNo);
110 unsigned STReg = getSTReg(RegNo);
111 unsigned RegOnTop = getStackEntry(0);
113 // Swap the slots the regs are in
114 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
116 // Swap stack slot contents
117 assert(RegMap[RegOnTop] < StackTop);
118 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
120 // Emit an fxch to update the runtime processors version of the state
121 MachineInstr *MI = BuildMI(X86::FXCH, 1).addReg(STReg);
127 void duplicateToTop(unsigned RegNo, unsigned AsReg,
128 MachineBasicBlock::iterator &I) {
129 unsigned STReg = getSTReg(RegNo);
130 pushReg(AsReg); // New register on top of stack
132 MachineInstr *MI = BuildMI(X86::FLDrr, 1).addReg(STReg);
136 // popStackAfter - Pop the current value off of the top of the FP stack
137 // after the specified instruction.
138 void popStackAfter(MachineBasicBlock::iterator &I);
140 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
142 void handleZeroArgFP(MachineBasicBlock::iterator &I);
143 void handleOneArgFP(MachineBasicBlock::iterator &I);
144 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
145 void handleTwoArgFP(MachineBasicBlock::iterator &I);
146 void handleSpecialFP(MachineBasicBlock::iterator &I);
150 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
152 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
153 /// register references into FP stack references.
155 bool FPS::runOnMachineFunction(MachineFunction &MF) {
156 LV = &getAnalysis<LiveVariables>();
159 // Figure out the mapping of MBB's to BB's.
161 // FIXME: Eventually we should be able to traverse the MBB CFG directly, and
162 // we will need to extend this when one llvm basic block can codegen to
165 // FIXME again: Just use the mapping established by LiveVariables!
167 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
168 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
169 MBBMap[I->getBasicBlock()] = I;
171 // Process the function in depth first order so that we process at least one
172 // of the predecessors for every reachable block in the function.
173 std::set<const BasicBlock*> Processed;
174 const BasicBlock *Entry = MF.getFunction()->begin();
176 bool Changed = false;
177 for (df_ext_iterator<const BasicBlock*, std::set<const BasicBlock*> >
178 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
180 Changed |= processBasicBlock(MF, *MBBMap[*I]);
182 assert(MBBMap.size() == Processed.size() &&
183 "Doesn't handle unreachable code yet!");
188 /// processBasicBlock - Loop over all of the instructions in the basic block,
189 /// transforming FP instructions into their stack form.
191 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
192 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
193 bool Changed = false;
196 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
197 MachineInstr *MI = I;
198 unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
199 if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
200 continue; // Efficiently ignore non-fp insts!
202 MachineInstr *PrevMI = 0;
206 ++NumFP; // Keep track of # of pseudo instrs
207 DEBUG(std::cerr << "\nFPInst:\t";
208 MI->print(std::cerr, MF.getTarget()));
210 // Get dead variables list now because the MI pointer may be deleted as part
212 LiveVariables::killed_iterator IB = LV->dead_begin(MI);
213 LiveVariables::killed_iterator IE = LV->dead_end(MI);
215 DEBUG(const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
216 LiveVariables::killed_iterator I = LV->killed_begin(MI);
217 LiveVariables::killed_iterator E = LV->killed_end(MI);
219 std::cerr << "Killed Operands:";
221 std::cerr << " %" << MRI->getName(I->second);
225 switch (Flags & X86II::FPTypeMask) {
226 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
227 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
228 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
229 case X86II::TwoArgFP: handleTwoArgFP(I); break;
230 case X86II::SpecialFP: handleSpecialFP(I); break;
231 default: assert(0 && "Unknown FP Type!");
234 // Check to see if any of the values defined by this instruction are dead
235 // after definition. If so, pop them.
236 for (; IB != IE; ++IB) {
237 unsigned Reg = IB->second;
238 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
239 DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
240 ++I; // Insert fxch AFTER the instruction
241 moveToTop(Reg-X86::FP0, I); // Insert fxch if necessary
242 --I; // Move to fxch or old instruction
243 popStackAfter(I); // Pop the top of the stack, killing value
247 // Print out all of the instructions expanded to if -debug
249 MachineBasicBlock::iterator PrevI(PrevMI);
251 std::cerr<< "Just deleted pseudo instruction\n";
253 MachineBasicBlock::iterator Start = I;
254 // Rewind to first instruction newly inserted.
255 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
256 std::cerr << "Inserted instructions:\n\t";
257 Start->print(std::cerr, MF.getTarget());
258 while (++Start != next(I));
266 assert(StackTop == 0 && "Stack not empty at end of basic block?");
270 //===----------------------------------------------------------------------===//
271 // Efficient Lookup Table Support
272 //===----------------------------------------------------------------------===//
278 bool operator<(const TableEntry &TE) const { return from < TE.from; }
279 bool operator<(unsigned V) const { return from < V; }
283 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
284 for (unsigned i = 0; i != NumEntries-1; ++i)
285 if (!(Table[i] < Table[i+1])) return false;
289 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
290 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
291 if (I != Table+N && I->from == Opcode)
296 #define ARRAY_SIZE(TABLE) \
297 (sizeof(TABLE)/sizeof(TABLE[0]))
300 #define ASSERT_SORTED(TABLE)
302 #define ASSERT_SORTED(TABLE) \
303 { static bool TABLE##Checked = false; \
304 if (!TABLE##Checked) \
305 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
306 "All lookup tables must be sorted for efficient access!"); \
311 //===----------------------------------------------------------------------===//
313 //===----------------------------------------------------------------------===//
315 // PopTable - Sorted map of instructions to their popping version. The first
316 // element is an instruction, the second is the version which pops.
318 static const TableEntry PopTable[] = {
319 { X86::FADDrST0 , X86::FADDPrST0 },
321 { X86::FDIVRrST0, X86::FDIVRPrST0 },
322 { X86::FDIVrST0 , X86::FDIVPrST0 },
324 { X86::FISTm16 , X86::FISTPm16 },
325 { X86::FISTm32 , X86::FISTPm32 },
327 { X86::FMULrST0 , X86::FMULPrST0 },
329 { X86::FSTm32 , X86::FSTPm32 },
330 { X86::FSTm64 , X86::FSTPm64 },
331 { X86::FSTrr , X86::FSTPrr },
333 { X86::FSUBRrST0, X86::FSUBRPrST0 },
334 { X86::FSUBrST0 , X86::FSUBPrST0 },
336 { X86::FUCOMPr , X86::FUCOMPPr },
337 { X86::FUCOMr , X86::FUCOMPr },
340 /// popStackAfter - Pop the current value off of the top of the FP stack after
341 /// the specified instruction. This attempts to be sneaky and combine the pop
342 /// into the instruction itself if possible. The iterator is left pointing to
343 /// the last instruction, be it a new pop instruction inserted, or the old
344 /// instruction if it was modified in place.
346 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
347 ASSERT_SORTED(PopTable);
348 assert(StackTop > 0 && "Cannot pop empty stack!");
349 RegMap[Stack[--StackTop]] = ~0; // Update state
351 // Check to see if there is a popping version of this instruction...
352 int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
354 I->setOpcode(Opcode);
355 if (Opcode == X86::FUCOMPPr)
358 } else { // Insert an explicit pop
359 MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(X86::ST0);
360 I = MBB->insert(++I, MI);
364 static unsigned getFPReg(const MachineOperand &MO) {
365 assert(MO.isRegister() && "Expected an FP register!");
366 unsigned Reg = MO.getReg();
367 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
368 return Reg - X86::FP0;
372 //===----------------------------------------------------------------------===//
373 // Instruction transformation implementation
374 //===----------------------------------------------------------------------===//
376 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
378 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
379 MachineInstr *MI = I;
380 unsigned DestReg = getFPReg(MI->getOperand(0));
381 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
383 // Result gets pushed on the stack...
387 /// handleOneArgFP - fst <mem>, ST(0)
389 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
390 MachineInstr *MI = I;
391 assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) &&
392 "Can only handle fst* & ftst instructions!");
394 // Is this the last use of the source register?
395 unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1));
396 bool KillsSrc = false;
397 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
398 E = LV->killed_end(MI); KI != E; ++KI)
399 KillsSrc |= KI->second == X86::FP0+Reg;
401 // FSTPr80 and FISTPr64 are strange because there are no non-popping versions.
402 // If we have one _and_ we don't want to pop the operand, duplicate the value
403 // on the stack instead of moving it. This ensure that popping the value is
406 if ((MI->getOpcode() == X86::FSTPm80 ||
407 MI->getOpcode() == X86::FISTPm64) && !KillsSrc) {
408 duplicateToTop(Reg, 7 /*temp register*/, I);
410 moveToTop(Reg, I); // Move to the top of the stack...
412 MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand
414 if (MI->getOpcode() == X86::FSTPm80 || MI->getOpcode() == X86::FISTPm64) {
415 assert(StackTop > 0 && "Stack empty??");
417 } else if (KillsSrc) { // Last use of operand?
423 /// handleOneArgFPRW - fchs - ST(0) = -ST(0)
425 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
426 MachineInstr *MI = I;
427 assert(MI->getNumOperands() == 2 && "Can only handle fst* instructions!");
429 // Is this the last use of the source register?
430 unsigned Reg = getFPReg(MI->getOperand(1));
431 bool KillsSrc = false;
432 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
433 E = LV->killed_end(MI); KI != E; ++KI)
434 KillsSrc |= KI->second == X86::FP0+Reg;
437 // If this is the last use of the source register, just make sure it's on
438 // the top of the stack.
440 assert(StackTop > 0 && "Stack cannot be empty!");
442 pushReg(getFPReg(MI->getOperand(0)));
444 // If this is not the last use of the source register, _copy_ it to the top
446 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
449 MI->RemoveOperand(1); // Drop the source operand.
450 MI->RemoveOperand(0); // Drop the destination operand.
454 //===----------------------------------------------------------------------===//
455 // Define tables of various ways to map pseudo instructions
458 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
459 static const TableEntry ForwardST0Table[] = {
460 { X86::FpADD, X86::FADDST0r },
461 { X86::FpDIV, X86::FDIVST0r },
462 { X86::FpMUL, X86::FMULST0r },
463 { X86::FpSUB, X86::FSUBST0r },
464 { X86::FpUCOM, X86::FUCOMr },
467 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
468 static const TableEntry ReverseST0Table[] = {
469 { X86::FpADD, X86::FADDST0r }, // commutative
470 { X86::FpDIV, X86::FDIVRST0r },
471 { X86::FpMUL, X86::FMULST0r }, // commutative
472 { X86::FpSUB, X86::FSUBRST0r },
476 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
477 static const TableEntry ForwardSTiTable[] = {
478 { X86::FpADD, X86::FADDrST0 }, // commutative
479 { X86::FpDIV, X86::FDIVRrST0 },
480 { X86::FpMUL, X86::FMULrST0 }, // commutative
481 { X86::FpSUB, X86::FSUBRrST0 },
482 { X86::FpUCOM, X86::FUCOMr },
485 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
486 static const TableEntry ReverseSTiTable[] = {
487 { X86::FpADD, X86::FADDrST0 },
488 { X86::FpDIV, X86::FDIVrST0 },
489 { X86::FpMUL, X86::FMULrST0 },
490 { X86::FpSUB, X86::FSUBrST0 },
495 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
496 /// instructions which need to be simplified and possibly transformed.
498 /// Result: ST(0) = fsub ST(0), ST(i)
499 /// ST(i) = fsub ST(0), ST(i)
500 /// ST(0) = fsubr ST(0), ST(i)
501 /// ST(i) = fsubr ST(0), ST(i)
503 /// In addition to three address instructions, this also handles the FpUCOM
504 /// instruction which only has two operands, but no destination. This
505 /// instruction is also annoying because there is no "reverse" form of it
508 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
509 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
510 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
511 MachineInstr *MI = I;
513 unsigned NumOperands = MI->getNumOperands();
514 assert(NumOperands == 3 ||
515 (NumOperands == 2 && MI->getOpcode() == X86::FpUCOM) &&
516 "Illegal TwoArgFP instruction!");
517 unsigned Dest = getFPReg(MI->getOperand(0));
518 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
519 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
520 bool KillsOp0 = false, KillsOp1 = false;
522 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
523 E = LV->killed_end(MI); KI != E; ++KI) {
524 KillsOp0 |= (KI->second == X86::FP0+Op0);
525 KillsOp1 |= (KI->second == X86::FP0+Op1);
528 // If this is an FpUCOM instruction, we must make sure the first operand is on
529 // the top of stack, the other one can be anywhere...
530 if (MI->getOpcode() == X86::FpUCOM)
533 unsigned TOS = getStackEntry(0);
535 // One of our operands must be on the top of the stack. If neither is yet, we
537 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
538 // We can choose to move either operand to the top of the stack. If one of
539 // the operands is killed by this instruction, we want that one so that we
540 // can update right on top of the old version.
542 moveToTop(Op0, I); // Move dead operand to TOS.
544 } else if (KillsOp1) {
548 // All of the operands are live after this instruction executes, so we
549 // cannot update on top of any operand. Because of this, we must
550 // duplicate one of the stack elements to the top. It doesn't matter
551 // which one we pick.
553 duplicateToTop(Op0, Dest, I);
557 } else if (!KillsOp0 && !KillsOp1 && MI->getOpcode() != X86::FpUCOM) {
558 // If we DO have one of our operands at the top of the stack, but we don't
559 // have a dead operand, we must duplicate one of the operands to a new slot
561 duplicateToTop(Op0, Dest, I);
566 // Now we know that one of our operands is on the top of the stack, and at
567 // least one of our operands is killed by this instruction.
568 assert((TOS == Op0 || TOS == Op1) &&
569 (KillsOp0 || KillsOp1 || MI->getOpcode() == X86::FpUCOM) &&
570 "Stack conditions not set up right!");
572 // We decide which form to use based on what is on the top of the stack, and
573 // which operand is killed by this instruction.
574 const TableEntry *InstTable;
575 bool isForward = TOS == Op0;
576 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
579 InstTable = ForwardST0Table;
581 InstTable = ReverseST0Table;
584 InstTable = ForwardSTiTable;
586 InstTable = ReverseSTiTable;
589 int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
590 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
592 // NotTOS - The register which is not on the top of stack...
593 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
595 // Replace the old instruction with a new instruction
597 I = MBB->insert(I, BuildMI(Opcode, 1).addReg(getSTReg(NotTOS)));
599 // If both operands are killed, pop one off of the stack in addition to
600 // overwriting the other one.
601 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
602 assert(!updateST0 && "Should have updated other operand!");
603 popStackAfter(I); // Pop the top of stack
606 // Insert an explicit pop of the "updated" operand for FUCOM
607 if (MI->getOpcode() == X86::FpUCOM) {
608 if (KillsOp0 && !KillsOp1)
609 popStackAfter(I); // If we kill the first operand, pop it!
610 else if (KillsOp1 && Op0 != Op1) {
611 if (getStackEntry(0) == Op1) {
612 popStackAfter(I); // If it's right at the top of stack, just pop it
614 // Otherwise, move the top of stack into the dead slot, killing the
615 // operand without having to add in an explicit xchg then pop.
617 unsigned STReg = getSTReg(Op1);
618 unsigned OldSlot = getSlot(Op1);
619 unsigned TopReg = Stack[StackTop-1];
620 Stack[OldSlot] = TopReg;
621 RegMap[TopReg] = OldSlot;
623 Stack[--StackTop] = ~0;
625 MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(STReg);
626 I = MBB->insert(++I, MI);
631 // Update stack information so that we know the destination register is now on
633 if (MI->getOpcode() != X86::FpUCOM) {
634 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
635 assert(UpdatedSlot < StackTop && Dest < 7);
636 Stack[UpdatedSlot] = Dest;
637 RegMap[Dest] = UpdatedSlot;
639 delete MI; // Remove the old instruction
643 /// handleSpecialFP - Handle special instructions which behave unlike other
644 /// floating point instructions. This is primarily intended for use by pseudo
647 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
648 MachineInstr *MI = I;
649 switch (MI->getOpcode()) {
650 default: assert(0 && "Unknown SpecialFP instruction!");
651 case X86::FpGETRESULT: // Appears immediately after a call returning FP type!
652 assert(StackTop == 0 && "Stack should be empty after a call!");
653 pushReg(getFPReg(MI->getOperand(0)));
655 case X86::FpSETRESULT:
656 assert(StackTop == 1 && "Stack should have one element on it to return!");
657 --StackTop; // "Forget" we have something on the top of stack!
660 unsigned SrcReg = getFPReg(MI->getOperand(1));
661 unsigned DestReg = getFPReg(MI->getOperand(0));
662 bool KillsSrc = false;
663 for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
664 E = LV->killed_end(MI); KI != E; ++KI)
665 KillsSrc |= KI->second == X86::FP0+SrcReg;
668 // If the input operand is killed, we can just change the owner of the
669 // incoming stack slot into the result.
670 unsigned Slot = getSlot(SrcReg);
671 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
672 Stack[Slot] = DestReg;
673 RegMap[DestReg] = Slot;
676 // For FMOV we just duplicate the specified value to a new stack slot.
677 // This could be made better, but would require substantial changes.
678 duplicateToTop(SrcReg, DestReg, I);
684 I = MBB->erase(I); // Remove the pseudo instruction