1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "x86-codegen"
33 #include "X86InstrInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/LiveVariables.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/ADT/DepthFirstIterator.h"
43 #include "llvm/ADT/SmallVector.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/STLExtras.h"
50 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
51 STATISTIC(NumFP , "Number of floating point instructions");
54 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
55 virtual bool runOnMachineFunction(MachineFunction &MF);
57 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
59 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
60 AU.addRequired<LiveVariables>();
61 MachineFunctionPass::getAnalysisUsage(AU);
64 const TargetInstrInfo *TII; // Machine instruction info.
65 LiveVariables *LV; // Live variable info for current function...
66 MachineBasicBlock *MBB; // Current basic block
67 unsigned Stack[8]; // FP<n> Registers in each stack slot...
68 unsigned RegMap[8]; // Track which stack slot contains each register
69 unsigned StackTop; // The current top of the FP stack.
71 void dumpStack() const {
72 cerr << "Stack contents:";
73 for (unsigned i = 0; i != StackTop; ++i) {
74 cerr << " FP" << Stack[i];
75 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
80 // getSlot - Return the stack slot number a particular register number is
82 unsigned getSlot(unsigned RegNo) const {
83 assert(RegNo < 8 && "Regno out of range!");
87 // getStackEntry - Return the X86::FP<n> register in register ST(i)
88 unsigned getStackEntry(unsigned STi) const {
89 assert(STi < StackTop && "Access past stack top!");
90 return Stack[StackTop-1-STi];
93 // getSTReg - Return the X86::ST(i) register which contains the specified
95 unsigned getSTReg(unsigned RegNo) const {
96 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
99 // pushReg - Push the specified FP<n> register onto the stack
100 void pushReg(unsigned Reg) {
101 assert(Reg < 8 && "Register number out of range!");
102 assert(StackTop < 8 && "Stack overflow!");
103 Stack[StackTop] = Reg;
104 RegMap[Reg] = StackTop++;
107 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
108 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
109 if (!isAtTop(RegNo)) {
110 unsigned STReg = getSTReg(RegNo);
111 unsigned RegOnTop = getStackEntry(0);
113 // Swap the slots the regs are in
114 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
116 // Swap stack slot contents
117 assert(RegMap[RegOnTop] < StackTop);
118 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
120 // Emit an fxch to update the runtime processors version of the state
121 BuildMI(*MBB, I, TII->get(X86::FXCH)).addReg(STReg);
126 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
127 unsigned STReg = getSTReg(RegNo);
128 pushReg(AsReg); // New register on top of stack
130 BuildMI(*MBB, I, TII->get(X86::FLDrr)).addReg(STReg);
133 // popStackAfter - Pop the current value off of the top of the FP stack
134 // after the specified instruction.
135 void popStackAfter(MachineBasicBlock::iterator &I);
137 // freeStackSlotAfter - Free the specified register from the register stack,
138 // so that it is no longer in a register. If the register is currently at
139 // the top of the stack, we just pop the current instruction, otherwise we
140 // store the current top-of-stack into the specified slot, then pop the top
142 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
144 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
146 void handleZeroArgFP(MachineBasicBlock::iterator &I);
147 void handleOneArgFP(MachineBasicBlock::iterator &I);
148 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
149 void handleTwoArgFP(MachineBasicBlock::iterator &I);
150 void handleCompareFP(MachineBasicBlock::iterator &I);
151 void handleCondMovFP(MachineBasicBlock::iterator &I);
152 void handleSpecialFP(MachineBasicBlock::iterator &I);
156 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
158 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
159 /// register references into FP stack references.
161 bool FPS::runOnMachineFunction(MachineFunction &MF) {
162 // We only need to run this pass if there are any FP registers used in this
163 // function. If it is all integer, there is nothing for us to do!
164 const bool *PhysRegsUsed = MF.getUsedPhysregs();
165 bool FPIsUsed = false;
167 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
168 for (unsigned i = 0; i <= 6; ++i)
169 if (PhysRegsUsed[X86::FP0+i]) {
175 if (!FPIsUsed) return false;
177 TII = MF.getTarget().getInstrInfo();
178 LV = &getAnalysis<LiveVariables>();
181 // Process the function in depth first order so that we process at least one
182 // of the predecessors for every reachable block in the function.
183 std::set<MachineBasicBlock*> Processed;
184 MachineBasicBlock *Entry = MF.begin();
186 bool Changed = false;
187 for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> >
188 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
190 Changed |= processBasicBlock(MF, **I);
195 /// processBasicBlock - Loop over all of the instructions in the basic block,
196 /// transforming FP instructions into their stack form.
198 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
199 bool Changed = false;
202 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
203 MachineInstr *MI = I;
204 unsigned Flags = MI->getInstrDescriptor()->TSFlags;
205 if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
206 continue; // Efficiently ignore non-fp insts!
208 MachineInstr *PrevMI = 0;
212 ++NumFP; // Keep track of # of pseudo instrs
213 DOUT << "\nFPInst:\t" << *MI;
215 // Get dead variables list now because the MI pointer may be deleted as part
217 SmallVector<unsigned, 8> DeadRegs;
218 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
219 const MachineOperand &MO = MI->getOperand(i);
220 if (MO.isReg() && MO.isDead())
221 DeadRegs.push_back(MO.getReg());
224 switch (Flags & X86II::FPTypeMask) {
225 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
226 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
227 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
228 case X86II::TwoArgFP: handleTwoArgFP(I); break;
229 case X86II::CompareFP: handleCompareFP(I); break;
230 case X86II::CondMovFP: handleCondMovFP(I); break;
231 case X86II::SpecialFP: handleSpecialFP(I); break;
232 default: assert(0 && "Unknown FP Type!");
235 // Check to see if any of the values defined by this instruction are dead
236 // after definition. If so, pop them.
237 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
238 unsigned Reg = DeadRegs[i];
239 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
240 DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
241 freeStackSlotAfter(I, Reg-X86::FP0);
245 // Print out all of the instructions expanded to if -debug
247 MachineBasicBlock::iterator PrevI(PrevMI);
249 cerr << "Just deleted pseudo instruction\n";
251 MachineBasicBlock::iterator Start = I;
252 // Rewind to first instruction newly inserted.
253 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
254 cerr << "Inserted instructions:\n\t";
255 Start->print(*cerr.stream(), &MF.getTarget());
256 while (++Start != next(I));
264 assert(StackTop == 0 && "Stack not empty at end of basic block?");
268 //===----------------------------------------------------------------------===//
269 // Efficient Lookup Table Support
270 //===----------------------------------------------------------------------===//
276 bool operator<(const TableEntry &TE) const { return from < TE.from; }
277 friend bool operator<(const TableEntry &TE, unsigned V) {
280 friend bool operator<(unsigned V, const TableEntry &TE) {
286 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
287 for (unsigned i = 0; i != NumEntries-1; ++i)
288 if (!(Table[i] < Table[i+1])) return false;
292 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
293 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
294 if (I != Table+N && I->from == Opcode)
299 #define ARRAY_SIZE(TABLE) \
300 (sizeof(TABLE)/sizeof(TABLE[0]))
303 #define ASSERT_SORTED(TABLE)
305 #define ASSERT_SORTED(TABLE) \
306 { static bool TABLE##Checked = false; \
307 if (!TABLE##Checked) { \
308 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
309 "All lookup tables must be sorted for efficient access!"); \
310 TABLE##Checked = true; \
315 //===----------------------------------------------------------------------===//
316 // Register File -> Register Stack Mapping Methods
317 //===----------------------------------------------------------------------===//
319 // OpcodeTable - Sorted map of register instructions to their stack version.
320 // The first element is an register file pseudo instruction, the second is the
321 // concrete X86 instruction which uses the register stack.
323 static const TableEntry OpcodeTable[] = {
324 { X86::FpABS , X86::FABS },
325 { X86::FpADD32m , X86::FADD32m },
326 { X86::FpADD64m , X86::FADD64m },
327 { X86::FpCHS , X86::FCHS },
328 { X86::FpCMOVB , X86::FCMOVB },
329 { X86::FpCMOVBE , X86::FCMOVBE },
330 { X86::FpCMOVE , X86::FCMOVE },
331 { X86::FpCMOVNB , X86::FCMOVNB },
332 { X86::FpCMOVNBE , X86::FCMOVNBE },
333 { X86::FpCMOVNE , X86::FCMOVNE },
334 { X86::FpCMOVNP , X86::FCMOVNP },
335 { X86::FpCMOVP , X86::FCMOVP },
336 { X86::FpCOS , X86::FCOS },
337 { X86::FpDIV32m , X86::FDIV32m },
338 { X86::FpDIV64m , X86::FDIV64m },
339 { X86::FpDIVR32m , X86::FDIVR32m },
340 { X86::FpDIVR64m , X86::FDIVR64m },
341 { X86::FpIADD16m , X86::FIADD16m },
342 { X86::FpIADD32m , X86::FIADD32m },
343 { X86::FpIDIV16m , X86::FIDIV16m },
344 { X86::FpIDIV32m , X86::FIDIV32m },
345 { X86::FpIDIVR16m, X86::FIDIVR16m},
346 { X86::FpIDIVR32m, X86::FIDIVR32m},
347 { X86::FpILD16m , X86::FILD16m },
348 { X86::FpILD32m , X86::FILD32m },
349 { X86::FpILD64m , X86::FILD64m },
350 { X86::FpIMUL16m , X86::FIMUL16m },
351 { X86::FpIMUL32m , X86::FIMUL32m },
352 { X86::FpIST16m , X86::FIST16m },
353 { X86::FpIST32m , X86::FIST32m },
354 { X86::FpIST64m , X86::FISTP64m },
355 { X86::FpISTT16m , X86::FISTTP16m},
356 { X86::FpISTT32m , X86::FISTTP32m},
357 { X86::FpISTT64m , X86::FISTTP64m},
358 { X86::FpISUB16m , X86::FISUB16m },
359 { X86::FpISUB32m , X86::FISUB32m },
360 { X86::FpISUBR16m, X86::FISUBR16m},
361 { X86::FpISUBR32m, X86::FISUBR32m},
362 { X86::FpLD0 , X86::FLD0 },
363 { X86::FpLD1 , X86::FLD1 },
364 { X86::FpLD32m , X86::FLD32m },
365 { X86::FpLD64m , X86::FLD64m },
366 { X86::FpMUL32m , X86::FMUL32m },
367 { X86::FpMUL64m , X86::FMUL64m },
368 { X86::FpSIN , X86::FSIN },
369 { X86::FpSQRT , X86::FSQRT },
370 { X86::FpST32m , X86::FST32m },
371 { X86::FpST64m , X86::FST64m },
372 { X86::FpSUB32m , X86::FSUB32m },
373 { X86::FpSUB64m , X86::FSUB64m },
374 { X86::FpSUBR32m , X86::FSUBR32m },
375 { X86::FpSUBR64m , X86::FSUBR64m },
376 { X86::FpTST , X86::FTST },
377 { X86::FpUCOMIr , X86::FUCOMIr },
378 { X86::FpUCOMr , X86::FUCOMr },
381 static unsigned getConcreteOpcode(unsigned Opcode) {
382 ASSERT_SORTED(OpcodeTable);
383 int Opc = Lookup(OpcodeTable, ARRAY_SIZE(OpcodeTable), Opcode);
384 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
388 //===----------------------------------------------------------------------===//
390 //===----------------------------------------------------------------------===//
392 // PopTable - Sorted map of instructions to their popping version. The first
393 // element is an instruction, the second is the version which pops.
395 static const TableEntry PopTable[] = {
396 { X86::FADDrST0 , X86::FADDPrST0 },
398 { X86::FDIVRrST0, X86::FDIVRPrST0 },
399 { X86::FDIVrST0 , X86::FDIVPrST0 },
401 { X86::FIST16m , X86::FISTP16m },
402 { X86::FIST32m , X86::FISTP32m },
404 { X86::FMULrST0 , X86::FMULPrST0 },
406 { X86::FST32m , X86::FSTP32m },
407 { X86::FST64m , X86::FSTP64m },
408 { X86::FSTrr , X86::FSTPrr },
410 { X86::FSUBRrST0, X86::FSUBRPrST0 },
411 { X86::FSUBrST0 , X86::FSUBPrST0 },
413 { X86::FUCOMIr , X86::FUCOMIPr },
415 { X86::FUCOMPr , X86::FUCOMPPr },
416 { X86::FUCOMr , X86::FUCOMPr },
419 /// popStackAfter - Pop the current value off of the top of the FP stack after
420 /// the specified instruction. This attempts to be sneaky and combine the pop
421 /// into the instruction itself if possible. The iterator is left pointing to
422 /// the last instruction, be it a new pop instruction inserted, or the old
423 /// instruction if it was modified in place.
425 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
426 ASSERT_SORTED(PopTable);
427 assert(StackTop > 0 && "Cannot pop empty stack!");
428 RegMap[Stack[--StackTop]] = ~0; // Update state
430 // Check to see if there is a popping version of this instruction...
431 int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
433 I->setInstrDescriptor(TII->get(Opcode));
434 if (Opcode == X86::FUCOMPPr)
436 } else { // Insert an explicit pop
437 I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(X86::ST0);
441 /// freeStackSlotAfter - Free the specified register from the register stack, so
442 /// that it is no longer in a register. If the register is currently at the top
443 /// of the stack, we just pop the current instruction, otherwise we store the
444 /// current top-of-stack into the specified slot, then pop the top of stack.
445 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
446 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
451 // Otherwise, store the top of stack into the dead slot, killing the operand
452 // without having to add in an explicit xchg then pop.
454 unsigned STReg = getSTReg(FPRegNo);
455 unsigned OldSlot = getSlot(FPRegNo);
456 unsigned TopReg = Stack[StackTop-1];
457 Stack[OldSlot] = TopReg;
458 RegMap[TopReg] = OldSlot;
459 RegMap[FPRegNo] = ~0;
460 Stack[--StackTop] = ~0;
461 I = BuildMI(*MBB, ++I, TII->get(X86::FSTPrr)).addReg(STReg);
465 static unsigned getFPReg(const MachineOperand &MO) {
466 assert(MO.isRegister() && "Expected an FP register!");
467 unsigned Reg = MO.getReg();
468 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
469 return Reg - X86::FP0;
473 //===----------------------------------------------------------------------===//
474 // Instruction transformation implementation
475 //===----------------------------------------------------------------------===//
477 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
479 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
480 MachineInstr *MI = I;
481 unsigned DestReg = getFPReg(MI->getOperand(0));
483 // Change from the pseudo instruction to the concrete instruction.
484 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
485 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
487 // Result gets pushed on the stack.
491 /// handleOneArgFP - fst <mem>, ST(0)
493 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
494 MachineInstr *MI = I;
495 unsigned NumOps = MI->getInstrDescriptor()->numOperands;
496 assert((NumOps == 5 || NumOps == 1) &&
497 "Can only handle fst* & ftst instructions!");
499 // Is this the last use of the source register?
500 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
501 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
503 // FISTP64m is strange because there isn't a non-popping versions.
504 // If we have one _and_ we don't want to pop the operand, duplicate the value
505 // on the stack instead of moving it. This ensure that popping the value is
507 // Ditto FISTTP16m, FISTTP32m, FISTTP64m.
510 (MI->getOpcode() == X86::FpIST64m ||
511 MI->getOpcode() == X86::FpISTT16m ||
512 MI->getOpcode() == X86::FpISTT32m ||
513 MI->getOpcode() == X86::FpISTT64m)) {
514 duplicateToTop(Reg, 7 /*temp register*/, I);
516 moveToTop(Reg, I); // Move to the top of the stack...
519 // Convert from the pseudo instruction to the concrete instruction.
520 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
521 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
523 if (MI->getOpcode() == X86::FISTP64m ||
524 MI->getOpcode() == X86::FISTTP16m ||
525 MI->getOpcode() == X86::FISTTP32m ||
526 MI->getOpcode() == X86::FISTTP64m) {
527 assert(StackTop > 0 && "Stack empty??");
529 } else if (KillsSrc) { // Last use of operand?
535 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
536 /// replace the value with a newly computed value. These instructions may have
537 /// non-fp operands after their FP operands.
541 /// R1 = fadd R2, [mem]
543 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
544 MachineInstr *MI = I;
545 unsigned NumOps = MI->getInstrDescriptor()->numOperands;
546 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
548 // Is this the last use of the source register?
549 unsigned Reg = getFPReg(MI->getOperand(1));
550 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
553 // If this is the last use of the source register, just make sure it's on
554 // the top of the stack.
556 assert(StackTop > 0 && "Stack cannot be empty!");
558 pushReg(getFPReg(MI->getOperand(0)));
560 // If this is not the last use of the source register, _copy_ it to the top
562 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
565 // Change from the pseudo instruction to the concrete instruction.
566 MI->RemoveOperand(1); // Drop the source operand.
567 MI->RemoveOperand(0); // Drop the destination operand.
568 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
572 //===----------------------------------------------------------------------===//
573 // Define tables of various ways to map pseudo instructions
576 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
577 static const TableEntry ForwardST0Table[] = {
578 { X86::FpADD , X86::FADDST0r },
579 { X86::FpDIV , X86::FDIVST0r },
580 { X86::FpMUL , X86::FMULST0r },
581 { X86::FpSUB , X86::FSUBST0r },
584 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
585 static const TableEntry ReverseST0Table[] = {
586 { X86::FpADD , X86::FADDST0r }, // commutative
587 { X86::FpDIV , X86::FDIVRST0r },
588 { X86::FpMUL , X86::FMULST0r }, // commutative
589 { X86::FpSUB , X86::FSUBRST0r },
592 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
593 static const TableEntry ForwardSTiTable[] = {
594 { X86::FpADD , X86::FADDrST0 }, // commutative
595 { X86::FpDIV , X86::FDIVRrST0 },
596 { X86::FpMUL , X86::FMULrST0 }, // commutative
597 { X86::FpSUB , X86::FSUBRrST0 },
600 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
601 static const TableEntry ReverseSTiTable[] = {
602 { X86::FpADD , X86::FADDrST0 },
603 { X86::FpDIV , X86::FDIVrST0 },
604 { X86::FpMUL , X86::FMULrST0 },
605 { X86::FpSUB , X86::FSUBrST0 },
609 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
610 /// instructions which need to be simplified and possibly transformed.
612 /// Result: ST(0) = fsub ST(0), ST(i)
613 /// ST(i) = fsub ST(0), ST(i)
614 /// ST(0) = fsubr ST(0), ST(i)
615 /// ST(i) = fsubr ST(0), ST(i)
617 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
618 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
619 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
620 MachineInstr *MI = I;
622 unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
623 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
624 unsigned Dest = getFPReg(MI->getOperand(0));
625 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
626 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
627 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
628 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
630 unsigned TOS = getStackEntry(0);
632 // One of our operands must be on the top of the stack. If neither is yet, we
634 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
635 // We can choose to move either operand to the top of the stack. If one of
636 // the operands is killed by this instruction, we want that one so that we
637 // can update right on top of the old version.
639 moveToTop(Op0, I); // Move dead operand to TOS.
641 } else if (KillsOp1) {
645 // All of the operands are live after this instruction executes, so we
646 // cannot update on top of any operand. Because of this, we must
647 // duplicate one of the stack elements to the top. It doesn't matter
648 // which one we pick.
650 duplicateToTop(Op0, Dest, I);
654 } else if (!KillsOp0 && !KillsOp1) {
655 // If we DO have one of our operands at the top of the stack, but we don't
656 // have a dead operand, we must duplicate one of the operands to a new slot
658 duplicateToTop(Op0, Dest, I);
663 // Now we know that one of our operands is on the top of the stack, and at
664 // least one of our operands is killed by this instruction.
665 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
666 "Stack conditions not set up right!");
668 // We decide which form to use based on what is on the top of the stack, and
669 // which operand is killed by this instruction.
670 const TableEntry *InstTable;
671 bool isForward = TOS == Op0;
672 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
675 InstTable = ForwardST0Table;
677 InstTable = ReverseST0Table;
680 InstTable = ForwardSTiTable;
682 InstTable = ReverseSTiTable;
685 int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
686 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
688 // NotTOS - The register which is not on the top of stack...
689 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
691 // Replace the old instruction with a new instruction
693 I = BuildMI(*MBB, I, TII->get(Opcode)).addReg(getSTReg(NotTOS));
695 // If both operands are killed, pop one off of the stack in addition to
696 // overwriting the other one.
697 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
698 assert(!updateST0 && "Should have updated other operand!");
699 popStackAfter(I); // Pop the top of stack
702 // Update stack information so that we know the destination register is now on
704 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
705 assert(UpdatedSlot < StackTop && Dest < 7);
706 Stack[UpdatedSlot] = Dest;
707 RegMap[Dest] = UpdatedSlot;
708 delete MI; // Remove the old instruction
711 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
712 /// register arguments and no explicit destinations.
714 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
715 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
716 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
717 MachineInstr *MI = I;
719 unsigned NumOperands = MI->getInstrDescriptor()->numOperands;
720 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
721 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
722 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
723 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
724 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
726 // Make sure the first operand is on the top of stack, the other one can be
730 // Change from the pseudo instruction to the concrete instruction.
731 MI->getOperand(0).setReg(getSTReg(Op1));
732 MI->RemoveOperand(1);
733 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
735 // If any of the operands are killed by this instruction, free them.
736 if (KillsOp0) freeStackSlotAfter(I, Op0);
737 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
740 /// handleCondMovFP - Handle two address conditional move instructions. These
741 /// instructions move a st(i) register to st(0) iff a condition is true. These
742 /// instructions require that the first operand is at the top of the stack, but
743 /// otherwise don't modify the stack at all.
744 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
745 MachineInstr *MI = I;
747 unsigned Op0 = getFPReg(MI->getOperand(0));
748 unsigned Op1 = getFPReg(MI->getOperand(2));
749 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
751 // The first operand *must* be on the top of the stack.
754 // Change the second operand to the stack register that the operand is in.
755 // Change from the pseudo instruction to the concrete instruction.
756 MI->RemoveOperand(0);
757 MI->RemoveOperand(1);
758 MI->getOperand(0).setReg(getSTReg(Op1));
759 MI->setInstrDescriptor(TII->get(getConcreteOpcode(MI->getOpcode())));
761 // If we kill the second operand, make sure to pop it from the stack.
762 if (Op0 != Op1 && KillsOp1) {
763 // Get this value off of the register stack.
764 freeStackSlotAfter(I, Op1);
769 /// handleSpecialFP - Handle special instructions which behave unlike other
770 /// floating point instructions. This is primarily intended for use by pseudo
773 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
774 MachineInstr *MI = I;
775 switch (MI->getOpcode()) {
776 default: assert(0 && "Unknown SpecialFP instruction!");
777 case X86::FpGETRESULT: // Appears immediately after a call returning FP type!
778 assert(StackTop == 0 && "Stack should be empty after a call!");
779 pushReg(getFPReg(MI->getOperand(0)));
781 case X86::FpSETRESULT:
782 assert(StackTop == 1 && "Stack should have one element on it to return!");
783 --StackTop; // "Forget" we have something on the top of stack!
786 unsigned SrcReg = getFPReg(MI->getOperand(1));
787 unsigned DestReg = getFPReg(MI->getOperand(0));
789 if (LV->KillsRegister(MI, X86::FP0+SrcReg)) {
790 // If the input operand is killed, we can just change the owner of the
791 // incoming stack slot into the result.
792 unsigned Slot = getSlot(SrcReg);
793 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
794 Stack[Slot] = DestReg;
795 RegMap[DestReg] = Slot;
798 // For FMOV we just duplicate the specified value to a new stack slot.
799 // This could be made better, but would require substantial changes.
800 duplicateToTop(SrcReg, DestReg, I);
806 I = MBB->erase(I); // Remove the pseudo instruction