1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "fp"
33 #include "X86InstrInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/LiveVariables.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/ADT/DepthFirstIterator.h"
42 #include "llvm/ADT/Statistic.h"
43 #include "llvm/ADT/STLExtras.h"
50 Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
51 Statistic<> NumFP ("x86-codegen", "Number of floating point instructions");
53 struct FPS : public MachineFunctionPass {
54 virtual bool runOnMachineFunction(MachineFunction &MF);
56 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
58 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
59 AU.addRequired<LiveVariables>();
60 MachineFunctionPass::getAnalysisUsage(AU);
63 LiveVariables *LV; // Live variable info for current function...
64 MachineBasicBlock *MBB; // Current basic block
65 unsigned Stack[8]; // FP<n> Registers in each stack slot...
66 unsigned RegMap[8]; // Track which stack slot contains each register
67 unsigned StackTop; // The current top of the FP stack.
69 void dumpStack() const {
70 std::cerr << "Stack contents:";
71 for (unsigned i = 0; i != StackTop; ++i) {
72 std::cerr << " FP" << Stack[i];
73 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
78 // getSlot - Return the stack slot number a particular register number is
80 unsigned getSlot(unsigned RegNo) const {
81 assert(RegNo < 8 && "Regno out of range!");
85 // getStackEntry - Return the X86::FP<n> register in register ST(i)
86 unsigned getStackEntry(unsigned STi) const {
87 assert(STi < StackTop && "Access past stack top!");
88 return Stack[StackTop-1-STi];
91 // getSTReg - Return the X86::ST(i) register which contains the specified
93 unsigned getSTReg(unsigned RegNo) const {
94 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
97 // pushReg - Push the specified FP<n> register onto the stack
98 void pushReg(unsigned Reg) {
99 assert(Reg < 8 && "Register number out of range!");
100 assert(StackTop < 8 && "Stack overflow!");
101 Stack[StackTop] = Reg;
102 RegMap[Reg] = StackTop++;
105 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
106 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
107 if (!isAtTop(RegNo)) {
108 unsigned Slot = getSlot(RegNo);
109 unsigned STReg = getSTReg(RegNo);
110 unsigned RegOnTop = getStackEntry(0);
112 // Swap the slots the regs are in
113 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
115 // Swap stack slot contents
116 assert(RegMap[RegOnTop] < StackTop);
117 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
119 // Emit an fxch to update the runtime processors version of the state
120 BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg);
125 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
126 unsigned STReg = getSTReg(RegNo);
127 pushReg(AsReg); // New register on top of stack
129 BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg);
132 // popStackAfter - Pop the current value off of the top of the FP stack
133 // after the specified instruction.
134 void popStackAfter(MachineBasicBlock::iterator &I);
136 // freeStackSlotAfter - Free the specified register from the register stack,
137 // so that it is no longer in a register. If the register is currently at
138 // the top of the stack, we just pop the current instruction, otherwise we
139 // store the current top-of-stack into the specified slot, then pop the top
141 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
143 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
145 void handleZeroArgFP(MachineBasicBlock::iterator &I);
146 void handleOneArgFP(MachineBasicBlock::iterator &I);
147 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
148 void handleTwoArgFP(MachineBasicBlock::iterator &I);
149 void handleCompareFP(MachineBasicBlock::iterator &I);
150 void handleCondMovFP(MachineBasicBlock::iterator &I);
151 void handleSpecialFP(MachineBasicBlock::iterator &I);
155 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
157 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
158 /// register references into FP stack references.
160 bool FPS::runOnMachineFunction(MachineFunction &MF) {
161 // We only need to run this pass if there are any FP registers used in this
162 // function. If it is all integer, there is nothing for us to do!
163 const bool *PhysRegsUsed = MF.getUsedPhysregs();
164 bool FPIsUsed = false;
166 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
167 for (unsigned i = 0; i <= 6; ++i)
168 if (PhysRegsUsed[X86::FP0+i]) {
174 if (!FPIsUsed) return false;
176 LV = &getAnalysis<LiveVariables>();
179 // Process the function in depth first order so that we process at least one
180 // of the predecessors for every reachable block in the function.
181 std::set<MachineBasicBlock*> Processed;
182 MachineBasicBlock *Entry = MF.begin();
184 bool Changed = false;
185 for (df_ext_iterator<MachineBasicBlock*, std::set<MachineBasicBlock*> >
186 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
188 Changed |= processBasicBlock(MF, **I);
193 /// processBasicBlock - Loop over all of the instructions in the basic block,
194 /// transforming FP instructions into their stack form.
196 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
197 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
198 bool Changed = false;
201 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
202 MachineInstr *MI = I;
203 unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
204 if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
205 continue; // Efficiently ignore non-fp insts!
207 MachineInstr *PrevMI = 0;
211 ++NumFP; // Keep track of # of pseudo instrs
212 DEBUG(std::cerr << "\nFPInst:\t"; MI->print(std::cerr, &(MF.getTarget())));
214 // Get dead variables list now because the MI pointer may be deleted as part
216 LiveVariables::killed_iterator IB, IE;
217 tie(IB, IE) = LV->dead_range(MI);
220 const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
221 LiveVariables::killed_iterator I = LV->killed_begin(MI);
222 LiveVariables::killed_iterator E = LV->killed_end(MI);
224 std::cerr << "Killed Operands:";
226 std::cerr << " %" << MRI->getName(*I);
231 switch (Flags & X86II::FPTypeMask) {
232 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
233 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
234 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
235 case X86II::TwoArgFP: handleTwoArgFP(I); break;
236 case X86II::CompareFP: handleCompareFP(I); break;
237 case X86II::CondMovFP: handleCondMovFP(I); break;
238 case X86II::SpecialFP: handleSpecialFP(I); break;
239 default: assert(0 && "Unknown FP Type!");
242 // Check to see if any of the values defined by this instruction are dead
243 // after definition. If so, pop them.
244 for (; IB != IE; ++IB) {
246 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
247 DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
248 freeStackSlotAfter(I, Reg-X86::FP0);
252 // Print out all of the instructions expanded to if -debug
254 MachineBasicBlock::iterator PrevI(PrevMI);
256 std::cerr << "Just deleted pseudo instruction\n";
258 MachineBasicBlock::iterator Start = I;
259 // Rewind to first instruction newly inserted.
260 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
261 std::cerr << "Inserted instructions:\n\t";
262 Start->print(std::cerr, &MF.getTarget());
263 while (++Start != next(I));
271 assert(StackTop == 0 && "Stack not empty at end of basic block?");
275 //===----------------------------------------------------------------------===//
276 // Efficient Lookup Table Support
277 //===----------------------------------------------------------------------===//
283 bool operator<(const TableEntry &TE) const { return from < TE.from; }
284 friend bool operator<(const TableEntry &TE, unsigned V) {
287 friend bool operator<(unsigned V, const TableEntry &TE) {
293 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
294 for (unsigned i = 0; i != NumEntries-1; ++i)
295 if (!(Table[i] < Table[i+1])) return false;
299 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
300 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
301 if (I != Table+N && I->from == Opcode)
306 #define ARRAY_SIZE(TABLE) \
307 (sizeof(TABLE)/sizeof(TABLE[0]))
310 #define ASSERT_SORTED(TABLE)
312 #define ASSERT_SORTED(TABLE) \
313 { static bool TABLE##Checked = false; \
314 if (!TABLE##Checked) \
315 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
316 "All lookup tables must be sorted for efficient access!"); \
320 //===----------------------------------------------------------------------===//
321 // Register File -> Register Stack Mapping Methods
322 //===----------------------------------------------------------------------===//
324 // OpcodeTable - Sorted map of register instructions to their stack version.
325 // The first element is an register file pseudo instruction, the second is the
326 // concrete X86 instruction which uses the register stack.
328 static const TableEntry OpcodeTable[] = {
329 { X86::FpABS , X86::FABS },
330 { X86::FpADD32m , X86::FADD32m },
331 { X86::FpADD64m , X86::FADD64m },
332 { X86::FpCHS , X86::FCHS },
333 { X86::FpCMOVB , X86::FCMOVB },
334 { X86::FpCMOVBE , X86::FCMOVBE },
335 { X86::FpCMOVE , X86::FCMOVE },
336 { X86::FpCMOVNB , X86::FCMOVNB },
337 { X86::FpCMOVNBE , X86::FCMOVNBE },
338 { X86::FpCMOVNE , X86::FCMOVNE },
339 { X86::FpCMOVNP , X86::FCMOVNP },
340 { X86::FpCMOVP , X86::FCMOVP },
341 { X86::FpCOS , X86::FCOS },
342 { X86::FpDIV32m , X86::FDIV32m },
343 { X86::FpDIV64m , X86::FDIV64m },
344 { X86::FpDIVR32m , X86::FDIVR32m },
345 { X86::FpDIVR64m , X86::FDIVR64m },
346 { X86::FpIADD16m , X86::FIADD16m },
347 { X86::FpIADD32m , X86::FIADD32m },
348 { X86::FpIDIV16m , X86::FIDIV16m },
349 { X86::FpIDIV32m , X86::FIDIV32m },
350 { X86::FpIDIVR16m, X86::FIDIVR16m},
351 { X86::FpIDIVR32m, X86::FIDIVR32m},
352 { X86::FpILD16m , X86::FILD16m },
353 { X86::FpILD32m , X86::FILD32m },
354 { X86::FpILD64m , X86::FILD64m },
355 { X86::FpIMUL16m , X86::FIMUL16m },
356 { X86::FpIMUL32m , X86::FIMUL32m },
357 { X86::FpIST16m , X86::FIST16m },
358 { X86::FpIST32m , X86::FIST32m },
359 { X86::FpIST64m , X86::FISTP64m },
360 { X86::FpISTT16m , X86::FISTTP16m},
361 { X86::FpISTT32m , X86::FISTTP32m},
362 { X86::FpISTT64m , X86::FISTTP64m},
363 { X86::FpISUB16m , X86::FISUB16m },
364 { X86::FpISUB32m , X86::FISUB32m },
365 { X86::FpISUBR16m, X86::FISUBR16m},
366 { X86::FpISUBR32m, X86::FISUBR32m},
367 { X86::FpLD0 , X86::FLD0 },
368 { X86::FpLD1 , X86::FLD1 },
369 { X86::FpLD32m , X86::FLD32m },
370 { X86::FpLD64m , X86::FLD64m },
371 { X86::FpMUL32m , X86::FMUL32m },
372 { X86::FpMUL64m , X86::FMUL64m },
373 { X86::FpSIN , X86::FSIN },
374 { X86::FpSQRT , X86::FSQRT },
375 { X86::FpST32m , X86::FST32m },
376 { X86::FpST64m , X86::FST64m },
377 { X86::FpSUB32m , X86::FSUB32m },
378 { X86::FpSUB64m , X86::FSUB64m },
379 { X86::FpSUBR32m , X86::FSUBR32m },
380 { X86::FpSUBR64m , X86::FSUBR64m },
381 { X86::FpTST , X86::FTST },
382 { X86::FpUCOMIr , X86::FUCOMIr },
383 { X86::FpUCOMr , X86::FUCOMr },
386 static unsigned getConcreteOpcode(unsigned Opcode) {
387 ASSERT_SORTED(OpcodeTable);
388 int Opc = Lookup(OpcodeTable, ARRAY_SIZE(OpcodeTable), Opcode);
389 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
393 //===----------------------------------------------------------------------===//
395 //===----------------------------------------------------------------------===//
397 // PopTable - Sorted map of instructions to their popping version. The first
398 // element is an instruction, the second is the version which pops.
400 static const TableEntry PopTable[] = {
401 { X86::FADDrST0 , X86::FADDPrST0 },
403 { X86::FDIVRrST0, X86::FDIVRPrST0 },
404 { X86::FDIVrST0 , X86::FDIVPrST0 },
406 { X86::FIST16m , X86::FISTP16m },
407 { X86::FIST32m , X86::FISTP32m },
409 { X86::FMULrST0 , X86::FMULPrST0 },
411 { X86::FST32m , X86::FSTP32m },
412 { X86::FST64m , X86::FSTP64m },
413 { X86::FSTrr , X86::FSTPrr },
415 { X86::FSUBRrST0, X86::FSUBRPrST0 },
416 { X86::FSUBrST0 , X86::FSUBPrST0 },
418 { X86::FUCOMIr , X86::FUCOMIPr },
420 { X86::FUCOMPr , X86::FUCOMPPr },
421 { X86::FUCOMr , X86::FUCOMPr },
424 /// popStackAfter - Pop the current value off of the top of the FP stack after
425 /// the specified instruction. This attempts to be sneaky and combine the pop
426 /// into the instruction itself if possible. The iterator is left pointing to
427 /// the last instruction, be it a new pop instruction inserted, or the old
428 /// instruction if it was modified in place.
430 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
431 ASSERT_SORTED(PopTable);
432 assert(StackTop > 0 && "Cannot pop empty stack!");
433 RegMap[Stack[--StackTop]] = ~0; // Update state
435 // Check to see if there is a popping version of this instruction...
436 int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
438 I->setOpcode(Opcode);
439 if (Opcode == X86::FUCOMPPr)
442 } else { // Insert an explicit pop
443 I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0);
447 /// freeStackSlotAfter - Free the specified register from the register stack, so
448 /// that it is no longer in a register. If the register is currently at the top
449 /// of the stack, we just pop the current instruction, otherwise we store the
450 /// current top-of-stack into the specified slot, then pop the top of stack.
451 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
452 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
457 // Otherwise, store the top of stack into the dead slot, killing the operand
458 // without having to add in an explicit xchg then pop.
460 unsigned STReg = getSTReg(FPRegNo);
461 unsigned OldSlot = getSlot(FPRegNo);
462 unsigned TopReg = Stack[StackTop-1];
463 Stack[OldSlot] = TopReg;
464 RegMap[TopReg] = OldSlot;
465 RegMap[FPRegNo] = ~0;
466 Stack[--StackTop] = ~0;
467 I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg);
471 static unsigned getFPReg(const MachineOperand &MO) {
472 assert(MO.isRegister() && "Expected an FP register!");
473 unsigned Reg = MO.getReg();
474 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
475 return Reg - X86::FP0;
479 //===----------------------------------------------------------------------===//
480 // Instruction transformation implementation
481 //===----------------------------------------------------------------------===//
483 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
485 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
486 MachineInstr *MI = I;
487 unsigned DestReg = getFPReg(MI->getOperand(0));
489 // Change from the pseudo instruction to the concrete instruction.
490 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
491 MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
493 // Result gets pushed on the stack.
497 /// handleOneArgFP - fst <mem>, ST(0)
499 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
500 MachineInstr *MI = I;
501 assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) &&
502 "Can only handle fst* & ftst instructions!");
504 // Is this the last use of the source register?
505 unsigned Reg = getFPReg(MI->getOperand(MI->getNumOperands()-1));
506 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
508 // FISTP64m is strange because there isn't a non-popping versions.
509 // If we have one _and_ we don't want to pop the operand, duplicate the value
510 // on the stack instead of moving it. This ensure that popping the value is
512 // Ditto FISTTP16m, FISTTP32m, FISTTP64m.
515 (MI->getOpcode() == X86::FpIST64m ||
516 MI->getOpcode() == X86::FpISTT16m ||
517 MI->getOpcode() == X86::FpISTT32m ||
518 MI->getOpcode() == X86::FpISTT64m)) {
519 duplicateToTop(Reg, 7 /*temp register*/, I);
521 moveToTop(Reg, I); // Move to the top of the stack...
524 // Convert from the pseudo instruction to the concrete instruction.
525 MI->RemoveOperand(MI->getNumOperands()-1); // Remove explicit ST(0) operand
526 MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
528 if (MI->getOpcode() == X86::FISTP64m ||
529 MI->getOpcode() == X86::FISTTP16m ||
530 MI->getOpcode() == X86::FISTTP32m ||
531 MI->getOpcode() == X86::FISTTP64m) {
532 assert(StackTop > 0 && "Stack empty??");
534 } else if (KillsSrc) { // Last use of operand?
540 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
541 /// replace the value with a newly computed value. These instructions may have
542 /// non-fp operands after their FP operands.
546 /// R1 = fadd R2, [mem]
548 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
549 MachineInstr *MI = I;
550 assert(MI->getNumOperands() >= 2 && "FPRW instructions must have 2 ops!!");
552 // Is this the last use of the source register?
553 unsigned Reg = getFPReg(MI->getOperand(1));
554 bool KillsSrc = LV->KillsRegister(MI, X86::FP0+Reg);
557 // If this is the last use of the source register, just make sure it's on
558 // the top of the stack.
560 assert(StackTop > 0 && "Stack cannot be empty!");
562 pushReg(getFPReg(MI->getOperand(0)));
564 // If this is not the last use of the source register, _copy_ it to the top
566 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
569 // Change from the pseudo instruction to the concrete instruction.
570 MI->RemoveOperand(1); // Drop the source operand.
571 MI->RemoveOperand(0); // Drop the destination operand.
572 MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
576 //===----------------------------------------------------------------------===//
577 // Define tables of various ways to map pseudo instructions
580 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
581 static const TableEntry ForwardST0Table[] = {
582 { X86::FpADD , X86::FADDST0r },
583 { X86::FpDIV , X86::FDIVST0r },
584 { X86::FpMUL , X86::FMULST0r },
585 { X86::FpSUB , X86::FSUBST0r },
588 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
589 static const TableEntry ReverseST0Table[] = {
590 { X86::FpADD , X86::FADDST0r }, // commutative
591 { X86::FpDIV , X86::FDIVRST0r },
592 { X86::FpMUL , X86::FMULST0r }, // commutative
593 { X86::FpSUB , X86::FSUBRST0r },
596 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
597 static const TableEntry ForwardSTiTable[] = {
598 { X86::FpADD , X86::FADDrST0 }, // commutative
599 { X86::FpDIV , X86::FDIVRrST0 },
600 { X86::FpMUL , X86::FMULrST0 }, // commutative
601 { X86::FpSUB , X86::FSUBRrST0 },
604 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
605 static const TableEntry ReverseSTiTable[] = {
606 { X86::FpADD , X86::FADDrST0 },
607 { X86::FpDIV , X86::FDIVrST0 },
608 { X86::FpMUL , X86::FMULrST0 },
609 { X86::FpSUB , X86::FSUBrST0 },
613 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
614 /// instructions which need to be simplified and possibly transformed.
616 /// Result: ST(0) = fsub ST(0), ST(i)
617 /// ST(i) = fsub ST(0), ST(i)
618 /// ST(0) = fsubr ST(0), ST(i)
619 /// ST(i) = fsubr ST(0), ST(i)
621 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
622 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
623 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
624 MachineInstr *MI = I;
626 unsigned NumOperands = MI->getNumOperands();
627 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
628 unsigned Dest = getFPReg(MI->getOperand(0));
629 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
630 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
631 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
632 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
634 unsigned TOS = getStackEntry(0);
636 // One of our operands must be on the top of the stack. If neither is yet, we
638 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
639 // We can choose to move either operand to the top of the stack. If one of
640 // the operands is killed by this instruction, we want that one so that we
641 // can update right on top of the old version.
643 moveToTop(Op0, I); // Move dead operand to TOS.
645 } else if (KillsOp1) {
649 // All of the operands are live after this instruction executes, so we
650 // cannot update on top of any operand. Because of this, we must
651 // duplicate one of the stack elements to the top. It doesn't matter
652 // which one we pick.
654 duplicateToTop(Op0, Dest, I);
658 } else if (!KillsOp0 && !KillsOp1) {
659 // If we DO have one of our operands at the top of the stack, but we don't
660 // have a dead operand, we must duplicate one of the operands to a new slot
662 duplicateToTop(Op0, Dest, I);
667 // Now we know that one of our operands is on the top of the stack, and at
668 // least one of our operands is killed by this instruction.
669 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
670 "Stack conditions not set up right!");
672 // We decide which form to use based on what is on the top of the stack, and
673 // which operand is killed by this instruction.
674 const TableEntry *InstTable;
675 bool isForward = TOS == Op0;
676 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
679 InstTable = ForwardST0Table;
681 InstTable = ReverseST0Table;
684 InstTable = ForwardSTiTable;
686 InstTable = ReverseSTiTable;
689 int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
690 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
692 // NotTOS - The register which is not on the top of stack...
693 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
695 // Replace the old instruction with a new instruction
697 I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS));
699 // If both operands are killed, pop one off of the stack in addition to
700 // overwriting the other one.
701 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
702 assert(!updateST0 && "Should have updated other operand!");
703 popStackAfter(I); // Pop the top of stack
706 // Update stack information so that we know the destination register is now on
708 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
709 assert(UpdatedSlot < StackTop && Dest < 7);
710 Stack[UpdatedSlot] = Dest;
711 RegMap[Dest] = UpdatedSlot;
712 delete MI; // Remove the old instruction
715 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
716 /// register arguments and no explicit destinations.
718 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
719 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
720 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
721 MachineInstr *MI = I;
723 unsigned NumOperands = MI->getNumOperands();
724 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
725 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
726 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
727 bool KillsOp0 = LV->KillsRegister(MI, X86::FP0+Op0);
728 bool KillsOp1 = LV->KillsRegister(MI, X86::FP0+Op1);
730 // Make sure the first operand is on the top of stack, the other one can be
734 // Change from the pseudo instruction to the concrete instruction.
735 MI->getOperand(0).setReg(getSTReg(Op1));
736 MI->RemoveOperand(1);
737 MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
739 // If any of the operands are killed by this instruction, free them.
740 if (KillsOp0) freeStackSlotAfter(I, Op0);
741 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
744 /// handleCondMovFP - Handle two address conditional move instructions. These
745 /// instructions move a st(i) register to st(0) iff a condition is true. These
746 /// instructions require that the first operand is at the top of the stack, but
747 /// otherwise don't modify the stack at all.
748 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
749 MachineInstr *MI = I;
751 unsigned Op0 = getFPReg(MI->getOperand(0));
752 unsigned Op1 = getFPReg(MI->getOperand(1));
754 // The first operand *must* be on the top of the stack.
757 // Change the second operand to the stack register that the operand is in.
758 // Change from the pseudo instruction to the concrete instruction.
759 MI->RemoveOperand(0);
760 MI->getOperand(0).setReg(getSTReg(Op1));
761 MI->setOpcode(getConcreteOpcode(MI->getOpcode()));
764 // If we kill the second operand, make sure to pop it from the stack.
765 if (Op0 != Op1 && LV->KillsRegister(MI, X86::FP0+Op1)) {
766 // Get this value off of the register stack.
767 freeStackSlotAfter(I, Op1);
772 /// handleSpecialFP - Handle special instructions which behave unlike other
773 /// floating point instructions. This is primarily intended for use by pseudo
776 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
777 MachineInstr *MI = I;
778 switch (MI->getOpcode()) {
779 default: assert(0 && "Unknown SpecialFP instruction!");
780 case X86::FpGETRESULT: // Appears immediately after a call returning FP type!
781 assert(StackTop == 0 && "Stack should be empty after a call!");
782 pushReg(getFPReg(MI->getOperand(0)));
784 case X86::FpSETRESULT:
785 assert(StackTop == 1 && "Stack should have one element on it to return!");
786 --StackTop; // "Forget" we have something on the top of stack!
789 unsigned SrcReg = getFPReg(MI->getOperand(1));
790 unsigned DestReg = getFPReg(MI->getOperand(0));
792 if (LV->KillsRegister(MI, X86::FP0+SrcReg)) {
793 // If the input operand is killed, we can just change the owner of the
794 // incoming stack slot into the result.
795 unsigned Slot = getSlot(SrcReg);
796 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
797 Stack[Slot] = DestReg;
798 RegMap[DestReg] = Slot;
801 // For FMOV we just duplicate the specified value to a new stack slot.
802 // This could be made better, but would require substantial changes.
803 duplicateToTop(SrcReg, DestReg, I);
809 I = MBB->erase(I); // Remove the pseudo instruction