1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // pseudo registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // The x87 hardware tracks liveness of the stack registers, so it is necessary
16 // to implement exact liveness tracking between basic blocks. The CFG edges are
17 // partitioned into bundles where the same FP registers must be live in
18 // identical stack positions. Instructions are inserted at the end of each basic
19 // block to rearrange the live registers to match the outgoing bundle.
21 // This approach avoids splitting critical edges at the potential cost of more
22 // live register shuffling instructions when critical edges are present.
24 //===----------------------------------------------------------------------===//
27 #include "X86InstrInfo.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/DepthFirstIterator.h"
30 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/CodeGen/EdgeBundles.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/LivePhysRegs.h"
40 #include "llvm/CodeGen/Passes.h"
41 #include "llvm/IR/InlineAsm.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetSubtargetInfo.h"
51 #define DEBUG_TYPE "x86-codegen"
53 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
54 STATISTIC(NumFP , "Number of floating point instructions");
57 const unsigned ScratchFPReg = 7;
59 struct FPS : public MachineFunctionPass {
61 FPS() : MachineFunctionPass(ID) {
62 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
63 // This is really only to keep valgrind quiet.
64 // The logic in isLive() is too much for it.
65 memset(Stack, 0, sizeof(Stack));
66 memset(RegMap, 0, sizeof(RegMap));
69 void getAnalysisUsage(AnalysisUsage &AU) const override {
71 AU.addRequired<EdgeBundles>();
72 AU.addPreservedID(MachineLoopInfoID);
73 AU.addPreservedID(MachineDominatorsID);
74 MachineFunctionPass::getAnalysisUsage(AU);
77 bool runOnMachineFunction(MachineFunction &MF) override;
79 const char *getPassName() const override { return "X86 FP Stackifier"; }
82 const TargetInstrInfo *TII; // Machine instruction info.
84 // Two CFG edges are related if they leave the same block, or enter the same
85 // block. The transitive closure of an edge under this relation is a
86 // LiveBundle. It represents a set of CFG edges where the live FP stack
87 // registers must be allocated identically in the x87 stack.
89 // A LiveBundle is usually all the edges leaving a block, or all the edges
90 // entering a block, but it can contain more edges if critical edges are
93 // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
94 // but the exact mapping of FP registers to stack slots is fixed later.
96 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
99 // Number of pre-assigned live registers in FixStack. This is 0 when the
100 // stack order has not yet been fixed.
103 // Assigned stack order for live-in registers.
104 // FixStack[i] == getStackEntry(i) for all i < FixCount.
105 unsigned char FixStack[8];
107 LiveBundle() : Mask(0), FixCount(0) {}
109 // Have the live registers been assigned a stack order yet?
110 bool isFixed() const { return !Mask || FixCount; }
113 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
114 // with no live FP registers.
115 SmallVector<LiveBundle, 8> LiveBundles;
117 // The edge bundle analysis provides indices into the LiveBundles vector.
118 EdgeBundles *Bundles;
120 // Return a bitmask of FP registers in block's live-in list.
121 static unsigned calcLiveInMask(MachineBasicBlock *MBB) {
123 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
124 E = MBB->livein_end(); I != E; ++I) {
126 if (Reg < X86::FP0 || Reg > X86::FP6)
128 Mask |= 1 << (Reg - X86::FP0);
133 // Partition all the CFG edges into LiveBundles.
134 void bundleCFG(MachineFunction &MF);
136 MachineBasicBlock *MBB; // Current basic block
138 // The hardware keeps track of how many FP registers are live, so we have
139 // to model that exactly. Usually, each live register corresponds to an
140 // FP<n> register, but when dealing with calls, returns, and inline
141 // assembly, it is sometimes necessary to have live scratch registers.
142 unsigned Stack[8]; // FP<n> Registers in each stack slot...
143 unsigned StackTop; // The current top of the FP stack.
146 NumFPRegs = 8 // Including scratch pseudo-registers.
149 // For each live FP<n> register, point to its Stack[] entry.
150 // The first entries correspond to FP0-FP6, the rest are scratch registers
151 // used when we need slightly different live registers than what the
152 // register allocator thinks.
153 unsigned RegMap[NumFPRegs];
155 // Set up our stack model to match the incoming registers to MBB.
156 void setupBlockStack();
158 // Shuffle live registers to match the expectations of successor blocks.
159 void finishBlockStack();
161 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
162 void dumpStack() const {
163 dbgs() << "Stack contents:";
164 for (unsigned i = 0; i != StackTop; ++i) {
165 dbgs() << " FP" << Stack[i];
166 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
171 /// getSlot - Return the stack slot number a particular register number is
173 unsigned getSlot(unsigned RegNo) const {
174 assert(RegNo < NumFPRegs && "Regno out of range!");
175 return RegMap[RegNo];
178 /// isLive - Is RegNo currently live in the stack?
179 bool isLive(unsigned RegNo) const {
180 unsigned Slot = getSlot(RegNo);
181 return Slot < StackTop && Stack[Slot] == RegNo;
184 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
185 unsigned getStackEntry(unsigned STi) const {
187 report_fatal_error("Access past stack top!");
188 return Stack[StackTop-1-STi];
191 /// getSTReg - Return the X86::ST(i) register which contains the specified
192 /// FP<RegNo> register.
193 unsigned getSTReg(unsigned RegNo) const {
194 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
197 // pushReg - Push the specified FP<n> register onto the stack.
198 void pushReg(unsigned Reg) {
199 assert(Reg < NumFPRegs && "Register number out of range!");
201 report_fatal_error("Stack overflow!");
202 Stack[StackTop] = Reg;
203 RegMap[Reg] = StackTop++;
206 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
207 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
208 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
209 if (isAtTop(RegNo)) return;
211 unsigned STReg = getSTReg(RegNo);
212 unsigned RegOnTop = getStackEntry(0);
214 // Swap the slots the regs are in.
215 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
217 // Swap stack slot contents.
218 if (RegMap[RegOnTop] >= StackTop)
219 report_fatal_error("Access past stack top!");
220 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
222 // Emit an fxch to update the runtime processors version of the state.
223 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
227 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
228 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
229 unsigned STReg = getSTReg(RegNo);
230 pushReg(AsReg); // New register on top of stack
232 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
235 /// popStackAfter - Pop the current value off of the top of the FP stack
236 /// after the specified instruction.
237 void popStackAfter(MachineBasicBlock::iterator &I);
239 /// freeStackSlotAfter - Free the specified register from the register
240 /// stack, so that it is no longer in a register. If the register is
241 /// currently at the top of the stack, we just pop the current instruction,
242 /// otherwise we store the current top-of-stack into the specified slot,
243 /// then pop the top of stack.
244 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
246 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
248 MachineBasicBlock::iterator
249 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
251 /// Adjust the live registers to be the set in Mask.
252 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
254 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
255 /// st(0), FP reg FixStack[1] is st(1) etc.
256 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
257 MachineBasicBlock::iterator I);
259 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
261 void handleCall(MachineBasicBlock::iterator &I);
262 void handleZeroArgFP(MachineBasicBlock::iterator &I);
263 void handleOneArgFP(MachineBasicBlock::iterator &I);
264 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
265 void handleTwoArgFP(MachineBasicBlock::iterator &I);
266 void handleCompareFP(MachineBasicBlock::iterator &I);
267 void handleCondMovFP(MachineBasicBlock::iterator &I);
268 void handleSpecialFP(MachineBasicBlock::iterator &I);
270 // Check if a COPY instruction is using FP registers.
271 static bool isFPCopy(MachineInstr *MI) {
272 unsigned DstReg = MI->getOperand(0).getReg();
273 unsigned SrcReg = MI->getOperand(1).getReg();
275 return X86::RFP80RegClass.contains(DstReg) ||
276 X86::RFP80RegClass.contains(SrcReg);
279 void setKillFlags(MachineBasicBlock &MBB) const;
284 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
286 /// getFPReg - Return the X86::FPx register number for the specified operand.
287 /// For example, this returns 3 for X86::FP3.
288 static unsigned getFPReg(const MachineOperand &MO) {
289 assert(MO.isReg() && "Expected an FP register!");
290 unsigned Reg = MO.getReg();
291 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
292 return Reg - X86::FP0;
295 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
296 /// register references into FP stack references.
298 bool FPS::runOnMachineFunction(MachineFunction &MF) {
299 // We only need to run this pass if there are any FP registers used in this
300 // function. If it is all integer, there is nothing for us to do!
301 bool FPIsUsed = false;
303 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
304 for (unsigned i = 0; i <= 6; ++i)
305 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
311 if (!FPIsUsed) return false;
313 Bundles = &getAnalysis<EdgeBundles>();
314 TII = MF.getSubtarget().getInstrInfo();
316 // Prepare cross-MBB liveness.
321 // Process the function in depth first order so that we process at least one
322 // of the predecessors for every reachable block in the function.
323 SmallPtrSet<MachineBasicBlock*, 8> Processed;
324 MachineBasicBlock *Entry = MF.begin();
326 bool Changed = false;
327 for (MachineBasicBlock *BB : depth_first_ext(Entry, Processed))
328 Changed |= processBasicBlock(MF, *BB);
330 // Process any unreachable blocks in arbitrary order now.
331 if (MF.size() != Processed.size())
332 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
333 if (Processed.insert(BB))
334 Changed |= processBasicBlock(MF, *BB);
341 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and
342 /// live-out sets for the FP registers. Consistent means that the set of
343 /// registers live-out from a block is identical to the live-in set of all
344 /// successors. This is not enforced by the normal live-in lists since
345 /// registers may be implicitly defined, or not used by all successors.
346 void FPS::bundleCFG(MachineFunction &MF) {
347 assert(LiveBundles.empty() && "Stale data in LiveBundles");
348 LiveBundles.resize(Bundles->getNumBundles());
350 // Gather the actual live-in masks for all MBBs.
351 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
352 MachineBasicBlock *MBB = I;
353 const unsigned Mask = calcLiveInMask(MBB);
356 // Update MBB ingoing bundle mask.
357 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)].Mask |= Mask;
361 /// processBasicBlock - Loop over all of the instructions in the basic block,
362 /// transforming FP instructions into their stack form.
364 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
365 bool Changed = false;
371 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
372 MachineInstr *MI = I;
373 uint64_t Flags = MI->getDesc().TSFlags;
375 unsigned FPInstClass = Flags & X86II::FPTypeMask;
376 if (MI->isInlineAsm())
377 FPInstClass = X86II::SpecialFP;
379 if (MI->isCopy() && isFPCopy(MI))
380 FPInstClass = X86II::SpecialFP;
382 if (MI->isImplicitDef() &&
383 X86::RFP80RegClass.contains(MI->getOperand(0).getReg()))
384 FPInstClass = X86II::SpecialFP;
387 FPInstClass = X86II::SpecialFP;
389 if (FPInstClass == X86II::NotFP)
390 continue; // Efficiently ignore non-fp insts!
392 MachineInstr *PrevMI = nullptr;
394 PrevMI = std::prev(I);
396 ++NumFP; // Keep track of # of pseudo instrs
397 DEBUG(dbgs() << "\nFPInst:\t" << *MI);
399 // Get dead variables list now because the MI pointer may be deleted as part
401 SmallVector<unsigned, 8> DeadRegs;
402 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
403 const MachineOperand &MO = MI->getOperand(i);
404 if (MO.isReg() && MO.isDead())
405 DeadRegs.push_back(MO.getReg());
408 switch (FPInstClass) {
409 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
410 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
411 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
412 case X86II::TwoArgFP: handleTwoArgFP(I); break;
413 case X86II::CompareFP: handleCompareFP(I); break;
414 case X86II::CondMovFP: handleCondMovFP(I); break;
415 case X86II::SpecialFP: handleSpecialFP(I); break;
416 default: llvm_unreachable("Unknown FP Type!");
419 // Check to see if any of the values defined by this instruction are dead
420 // after definition. If so, pop them.
421 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
422 unsigned Reg = DeadRegs[i];
423 // Check if Reg is live on the stack. An inline-asm register operand that
424 // is in the clobber list and marked dead might not be live on the stack.
425 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
426 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
427 freeStackSlotAfter(I, Reg-X86::FP0);
431 // Print out all of the instructions expanded to if -debug
433 MachineBasicBlock::iterator PrevI(PrevMI);
435 dbgs() << "Just deleted pseudo instruction\n";
437 MachineBasicBlock::iterator Start = I;
438 // Rewind to first instruction newly inserted.
439 while (Start != BB.begin() && std::prev(Start) != PrevI) --Start;
440 dbgs() << "Inserted instructions:\n\t";
441 Start->print(dbgs(), &MF.getTarget());
442 while (++Start != std::next(I)) {}
456 /// setupBlockStack - Use the live bundles to set up our model of the stack
457 /// to match predecessors' live out stack.
458 void FPS::setupBlockStack() {
459 DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
460 << " derived from " << MBB->getName() << ".\n");
462 // Get the live-in bundle for MBB.
463 const LiveBundle &Bundle =
464 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)];
467 DEBUG(dbgs() << "Block has no FP live-ins.\n");
471 // Depth-first iteration should ensure that we always have an assigned stack.
472 assert(Bundle.isFixed() && "Reached block before any predecessors");
474 // Push the fixed live-in registers.
475 for (unsigned i = Bundle.FixCount; i > 0; --i) {
476 MBB->addLiveIn(X86::ST0+i-1);
477 DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
478 << unsigned(Bundle.FixStack[i-1]) << '\n');
479 pushReg(Bundle.FixStack[i-1]);
482 // Kill off unwanted live-ins. This can happen with a critical edge.
483 // FIXME: We could keep these live registers around as zombies. They may need
484 // to be revived at the end of a short block. It might save a few instrs.
485 adjustLiveRegs(calcLiveInMask(MBB), MBB->begin());
489 /// finishBlockStack - Revive live-outs that are implicitly defined out of
490 /// MBB. Shuffle live registers to match the expected fixed stack of any
491 /// predecessors, and ensure that all predecessors are expecting the same
493 void FPS::finishBlockStack() {
494 // The RET handling below takes care of return blocks for us.
495 if (MBB->succ_empty())
498 DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
499 << " derived from " << MBB->getName() << ".\n");
501 // Get MBB's live-out bundle.
502 unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true);
503 LiveBundle &Bundle = LiveBundles[BundleIdx];
505 // We may need to kill and define some registers to match successors.
506 // FIXME: This can probably be combined with the shuffle below.
507 MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
508 adjustLiveRegs(Bundle.Mask, Term);
511 DEBUG(dbgs() << "No live-outs.\n");
515 // Has the stack order been fixed yet?
516 DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
517 if (Bundle.isFixed()) {
518 DEBUG(dbgs() << "Shuffling stack to match.\n");
519 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
521 // Not fixed yet, we get to choose.
522 DEBUG(dbgs() << "Fixing stack order now.\n");
523 Bundle.FixCount = StackTop;
524 for (unsigned i = 0; i < StackTop; ++i)
525 Bundle.FixStack[i] = getStackEntry(i);
530 //===----------------------------------------------------------------------===//
531 // Efficient Lookup Table Support
532 //===----------------------------------------------------------------------===//
538 bool operator<(const TableEntry &TE) const { return from < TE.from; }
539 friend bool operator<(const TableEntry &TE, unsigned V) {
542 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V,
543 const TableEntry &TE) {
550 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
551 for (unsigned i = 0; i != NumEntries-1; ++i)
552 if (!(Table[i] < Table[i+1])) return false;
557 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
558 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
559 if (I != Table+N && I->from == Opcode)
565 #define ASSERT_SORTED(TABLE)
567 #define ASSERT_SORTED(TABLE) \
568 { static bool TABLE##Checked = false; \
569 if (!TABLE##Checked) { \
570 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
571 "All lookup tables must be sorted for efficient access!"); \
572 TABLE##Checked = true; \
577 //===----------------------------------------------------------------------===//
578 // Register File -> Register Stack Mapping Methods
579 //===----------------------------------------------------------------------===//
581 // OpcodeTable - Sorted map of register instructions to their stack version.
582 // The first element is an register file pseudo instruction, the second is the
583 // concrete X86 instruction which uses the register stack.
585 static const TableEntry OpcodeTable[] = {
586 { X86::ABS_Fp32 , X86::ABS_F },
587 { X86::ABS_Fp64 , X86::ABS_F },
588 { X86::ABS_Fp80 , X86::ABS_F },
589 { X86::ADD_Fp32m , X86::ADD_F32m },
590 { X86::ADD_Fp64m , X86::ADD_F64m },
591 { X86::ADD_Fp64m32 , X86::ADD_F32m },
592 { X86::ADD_Fp80m32 , X86::ADD_F32m },
593 { X86::ADD_Fp80m64 , X86::ADD_F64m },
594 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
595 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
596 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
597 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
598 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
599 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
600 { X86::CHS_Fp32 , X86::CHS_F },
601 { X86::CHS_Fp64 , X86::CHS_F },
602 { X86::CHS_Fp80 , X86::CHS_F },
603 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
604 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
605 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
606 { X86::CMOVB_Fp32 , X86::CMOVB_F },
607 { X86::CMOVB_Fp64 , X86::CMOVB_F },
608 { X86::CMOVB_Fp80 , X86::CMOVB_F },
609 { X86::CMOVE_Fp32 , X86::CMOVE_F },
610 { X86::CMOVE_Fp64 , X86::CMOVE_F },
611 { X86::CMOVE_Fp80 , X86::CMOVE_F },
612 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
613 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
614 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
615 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
616 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
617 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
618 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
619 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
620 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
621 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
622 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
623 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
624 { X86::CMOVP_Fp32 , X86::CMOVP_F },
625 { X86::CMOVP_Fp64 , X86::CMOVP_F },
626 { X86::CMOVP_Fp80 , X86::CMOVP_F },
627 { X86::COS_Fp32 , X86::COS_F },
628 { X86::COS_Fp64 , X86::COS_F },
629 { X86::COS_Fp80 , X86::COS_F },
630 { X86::DIVR_Fp32m , X86::DIVR_F32m },
631 { X86::DIVR_Fp64m , X86::DIVR_F64m },
632 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
633 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
634 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
635 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
636 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
637 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
638 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
639 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
640 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
641 { X86::DIV_Fp32m , X86::DIV_F32m },
642 { X86::DIV_Fp64m , X86::DIV_F64m },
643 { X86::DIV_Fp64m32 , X86::DIV_F32m },
644 { X86::DIV_Fp80m32 , X86::DIV_F32m },
645 { X86::DIV_Fp80m64 , X86::DIV_F64m },
646 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
647 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
648 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
649 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
650 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
651 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
652 { X86::ILD_Fp16m32 , X86::ILD_F16m },
653 { X86::ILD_Fp16m64 , X86::ILD_F16m },
654 { X86::ILD_Fp16m80 , X86::ILD_F16m },
655 { X86::ILD_Fp32m32 , X86::ILD_F32m },
656 { X86::ILD_Fp32m64 , X86::ILD_F32m },
657 { X86::ILD_Fp32m80 , X86::ILD_F32m },
658 { X86::ILD_Fp64m32 , X86::ILD_F64m },
659 { X86::ILD_Fp64m64 , X86::ILD_F64m },
660 { X86::ILD_Fp64m80 , X86::ILD_F64m },
661 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
662 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
663 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
664 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
665 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
666 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
667 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
668 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
669 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
670 { X86::IST_Fp16m32 , X86::IST_F16m },
671 { X86::IST_Fp16m64 , X86::IST_F16m },
672 { X86::IST_Fp16m80 , X86::IST_F16m },
673 { X86::IST_Fp32m32 , X86::IST_F32m },
674 { X86::IST_Fp32m64 , X86::IST_F32m },
675 { X86::IST_Fp32m80 , X86::IST_F32m },
676 { X86::IST_Fp64m32 , X86::IST_FP64m },
677 { X86::IST_Fp64m64 , X86::IST_FP64m },
678 { X86::IST_Fp64m80 , X86::IST_FP64m },
679 { X86::LD_Fp032 , X86::LD_F0 },
680 { X86::LD_Fp064 , X86::LD_F0 },
681 { X86::LD_Fp080 , X86::LD_F0 },
682 { X86::LD_Fp132 , X86::LD_F1 },
683 { X86::LD_Fp164 , X86::LD_F1 },
684 { X86::LD_Fp180 , X86::LD_F1 },
685 { X86::LD_Fp32m , X86::LD_F32m },
686 { X86::LD_Fp32m64 , X86::LD_F32m },
687 { X86::LD_Fp32m80 , X86::LD_F32m },
688 { X86::LD_Fp64m , X86::LD_F64m },
689 { X86::LD_Fp64m80 , X86::LD_F64m },
690 { X86::LD_Fp80m , X86::LD_F80m },
691 { X86::MUL_Fp32m , X86::MUL_F32m },
692 { X86::MUL_Fp64m , X86::MUL_F64m },
693 { X86::MUL_Fp64m32 , X86::MUL_F32m },
694 { X86::MUL_Fp80m32 , X86::MUL_F32m },
695 { X86::MUL_Fp80m64 , X86::MUL_F64m },
696 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
697 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
698 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
699 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
700 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
701 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
702 { X86::SIN_Fp32 , X86::SIN_F },
703 { X86::SIN_Fp64 , X86::SIN_F },
704 { X86::SIN_Fp80 , X86::SIN_F },
705 { X86::SQRT_Fp32 , X86::SQRT_F },
706 { X86::SQRT_Fp64 , X86::SQRT_F },
707 { X86::SQRT_Fp80 , X86::SQRT_F },
708 { X86::ST_Fp32m , X86::ST_F32m },
709 { X86::ST_Fp64m , X86::ST_F64m },
710 { X86::ST_Fp64m32 , X86::ST_F32m },
711 { X86::ST_Fp80m32 , X86::ST_F32m },
712 { X86::ST_Fp80m64 , X86::ST_F64m },
713 { X86::ST_FpP80m , X86::ST_FP80m },
714 { X86::SUBR_Fp32m , X86::SUBR_F32m },
715 { X86::SUBR_Fp64m , X86::SUBR_F64m },
716 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
717 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
718 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
719 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
720 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
721 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
722 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
723 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
724 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
725 { X86::SUB_Fp32m , X86::SUB_F32m },
726 { X86::SUB_Fp64m , X86::SUB_F64m },
727 { X86::SUB_Fp64m32 , X86::SUB_F32m },
728 { X86::SUB_Fp80m32 , X86::SUB_F32m },
729 { X86::SUB_Fp80m64 , X86::SUB_F64m },
730 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
731 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
732 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
733 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
734 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
735 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
736 { X86::TST_Fp32 , X86::TST_F },
737 { X86::TST_Fp64 , X86::TST_F },
738 { X86::TST_Fp80 , X86::TST_F },
739 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
740 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
741 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
742 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
743 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
744 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
747 static unsigned getConcreteOpcode(unsigned Opcode) {
748 ASSERT_SORTED(OpcodeTable);
749 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
750 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
754 //===----------------------------------------------------------------------===//
756 //===----------------------------------------------------------------------===//
758 // PopTable - Sorted map of instructions to their popping version. The first
759 // element is an instruction, the second is the version which pops.
761 static const TableEntry PopTable[] = {
762 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
764 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
765 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
767 { X86::IST_F16m , X86::IST_FP16m },
768 { X86::IST_F32m , X86::IST_FP32m },
770 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
772 { X86::ST_F32m , X86::ST_FP32m },
773 { X86::ST_F64m , X86::ST_FP64m },
774 { X86::ST_Frr , X86::ST_FPrr },
776 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
777 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
779 { X86::UCOM_FIr , X86::UCOM_FIPr },
781 { X86::UCOM_FPr , X86::UCOM_FPPr },
782 { X86::UCOM_Fr , X86::UCOM_FPr },
785 /// popStackAfter - Pop the current value off of the top of the FP stack after
786 /// the specified instruction. This attempts to be sneaky and combine the pop
787 /// into the instruction itself if possible. The iterator is left pointing to
788 /// the last instruction, be it a new pop instruction inserted, or the old
789 /// instruction if it was modified in place.
791 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
792 MachineInstr* MI = I;
793 DebugLoc dl = MI->getDebugLoc();
794 ASSERT_SORTED(PopTable);
796 report_fatal_error("Cannot pop empty stack!");
797 RegMap[Stack[--StackTop]] = ~0; // Update state
799 // Check to see if there is a popping version of this instruction...
800 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
802 I->setDesc(TII->get(Opcode));
803 if (Opcode == X86::UCOM_FPPr)
805 } else { // Insert an explicit pop
806 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
810 /// freeStackSlotAfter - Free the specified register from the register stack, so
811 /// that it is no longer in a register. If the register is currently at the top
812 /// of the stack, we just pop the current instruction, otherwise we store the
813 /// current top-of-stack into the specified slot, then pop the top of stack.
814 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
815 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
820 // Otherwise, store the top of stack into the dead slot, killing the operand
821 // without having to add in an explicit xchg then pop.
823 I = freeStackSlotBefore(++I, FPRegNo);
826 /// freeStackSlotBefore - Free the specified register without trying any
828 MachineBasicBlock::iterator
829 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
830 unsigned STReg = getSTReg(FPRegNo);
831 unsigned OldSlot = getSlot(FPRegNo);
832 unsigned TopReg = Stack[StackTop-1];
833 Stack[OldSlot] = TopReg;
834 RegMap[TopReg] = OldSlot;
835 RegMap[FPRegNo] = ~0;
836 Stack[--StackTop] = ~0;
837 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)).addReg(STReg);
840 /// adjustLiveRegs - Kill and revive registers such that exactly the FP
841 /// registers with a bit in Mask are live.
842 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
843 unsigned Defs = Mask;
845 for (unsigned i = 0; i < StackTop; ++i) {
846 unsigned RegNo = Stack[i];
847 if (!(Defs & (1 << RegNo)))
848 // This register is live, but we don't want it.
849 Kills |= (1 << RegNo);
851 // We don't need to imp-def this live register.
852 Defs &= ~(1 << RegNo);
854 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
856 // Produce implicit-defs for free by using killed registers.
857 while (Kills && Defs) {
858 unsigned KReg = countTrailingZeros(Kills);
859 unsigned DReg = countTrailingZeros(Defs);
860 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
861 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
862 std::swap(RegMap[KReg], RegMap[DReg]);
863 Kills &= ~(1 << KReg);
864 Defs &= ~(1 << DReg);
867 // Kill registers by popping.
868 if (Kills && I != MBB->begin()) {
869 MachineBasicBlock::iterator I2 = std::prev(I);
871 unsigned KReg = getStackEntry(0);
872 if (!(Kills & (1 << KReg)))
874 DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
876 Kills &= ~(1 << KReg);
880 // Manually kill the rest.
882 unsigned KReg = countTrailingZeros(Kills);
883 DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
884 freeStackSlotBefore(I, KReg);
885 Kills &= ~(1 << KReg);
888 // Load zeros for all the imp-defs.
890 unsigned DReg = countTrailingZeros(Defs);
891 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
892 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
894 Defs &= ~(1 << DReg);
897 // Now we should have the correct registers live.
899 assert(StackTop == CountPopulation_32(Mask) && "Live count mismatch");
902 /// shuffleStackTop - emit fxch instructions before I to shuffle the top
903 /// FixCount entries into the order given by FixStack.
904 /// FIXME: Is there a better algorithm than insertion sort?
905 void FPS::shuffleStackTop(const unsigned char *FixStack,
907 MachineBasicBlock::iterator I) {
908 // Move items into place, starting from the desired stack bottom.
910 // Old register at position FixCount.
911 unsigned OldReg = getStackEntry(FixCount);
912 // Desired register at position FixCount.
913 unsigned Reg = FixStack[FixCount];
916 // (Reg st0) (OldReg st0) = (Reg OldReg st0)
919 moveToTop(OldReg, I);
925 //===----------------------------------------------------------------------===//
926 // Instruction transformation implementation
927 //===----------------------------------------------------------------------===//
929 void FPS::handleCall(MachineBasicBlock::iterator &I) {
930 unsigned STReturns = 0;
932 for (const auto &MO : I->operands()) {
936 unsigned R = MO.getReg() - X86::FP0;
939 assert(MO.isDef() && MO.isImplicit());
944 unsigned N = CountTrailingOnes_32(STReturns);
946 // FP registers used for function return must be consecutive starting at
948 assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2));
950 for (unsigned I = 0; I < N; ++I)
954 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
956 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
957 MachineInstr *MI = I;
958 unsigned DestReg = getFPReg(MI->getOperand(0));
960 // Change from the pseudo instruction to the concrete instruction.
961 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
962 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
964 // Result gets pushed on the stack.
968 /// handleOneArgFP - fst <mem>, ST(0)
970 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
971 MachineInstr *MI = I;
972 unsigned NumOps = MI->getDesc().getNumOperands();
973 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
974 "Can only handle fst* & ftst instructions!");
976 // Is this the last use of the source register?
977 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
978 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
980 // FISTP64m is strange because there isn't a non-popping versions.
981 // If we have one _and_ we don't want to pop the operand, duplicate the value
982 // on the stack instead of moving it. This ensure that popping the value is
984 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
987 (MI->getOpcode() == X86::IST_Fp64m32 ||
988 MI->getOpcode() == X86::ISTT_Fp16m32 ||
989 MI->getOpcode() == X86::ISTT_Fp32m32 ||
990 MI->getOpcode() == X86::ISTT_Fp64m32 ||
991 MI->getOpcode() == X86::IST_Fp64m64 ||
992 MI->getOpcode() == X86::ISTT_Fp16m64 ||
993 MI->getOpcode() == X86::ISTT_Fp32m64 ||
994 MI->getOpcode() == X86::ISTT_Fp64m64 ||
995 MI->getOpcode() == X86::IST_Fp64m80 ||
996 MI->getOpcode() == X86::ISTT_Fp16m80 ||
997 MI->getOpcode() == X86::ISTT_Fp32m80 ||
998 MI->getOpcode() == X86::ISTT_Fp64m80 ||
999 MI->getOpcode() == X86::ST_FpP80m)) {
1000 duplicateToTop(Reg, ScratchFPReg, I);
1002 moveToTop(Reg, I); // Move to the top of the stack...
1005 // Convert from the pseudo instruction to the concrete instruction.
1006 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
1007 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1009 if (MI->getOpcode() == X86::IST_FP64m ||
1010 MI->getOpcode() == X86::ISTT_FP16m ||
1011 MI->getOpcode() == X86::ISTT_FP32m ||
1012 MI->getOpcode() == X86::ISTT_FP64m ||
1013 MI->getOpcode() == X86::ST_FP80m) {
1015 report_fatal_error("Stack empty??");
1017 } else if (KillsSrc) { // Last use of operand?
1023 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
1024 /// replace the value with a newly computed value. These instructions may have
1025 /// non-fp operands after their FP operands.
1029 /// R1 = fadd R2, [mem]
1031 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
1032 MachineInstr *MI = I;
1034 unsigned NumOps = MI->getDesc().getNumOperands();
1035 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1038 // Is this the last use of the source register?
1039 unsigned Reg = getFPReg(MI->getOperand(1));
1040 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
1043 // If this is the last use of the source register, just make sure it's on
1044 // the top of the stack.
1047 report_fatal_error("Stack cannot be empty!");
1049 pushReg(getFPReg(MI->getOperand(0)));
1051 // If this is not the last use of the source register, _copy_ it to the top
1053 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
1056 // Change from the pseudo instruction to the concrete instruction.
1057 MI->RemoveOperand(1); // Drop the source operand.
1058 MI->RemoveOperand(0); // Drop the destination operand.
1059 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1063 //===----------------------------------------------------------------------===//
1064 // Define tables of various ways to map pseudo instructions
1067 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
1068 static const TableEntry ForwardST0Table[] = {
1069 { X86::ADD_Fp32 , X86::ADD_FST0r },
1070 { X86::ADD_Fp64 , X86::ADD_FST0r },
1071 { X86::ADD_Fp80 , X86::ADD_FST0r },
1072 { X86::DIV_Fp32 , X86::DIV_FST0r },
1073 { X86::DIV_Fp64 , X86::DIV_FST0r },
1074 { X86::DIV_Fp80 , X86::DIV_FST0r },
1075 { X86::MUL_Fp32 , X86::MUL_FST0r },
1076 { X86::MUL_Fp64 , X86::MUL_FST0r },
1077 { X86::MUL_Fp80 , X86::MUL_FST0r },
1078 { X86::SUB_Fp32 , X86::SUB_FST0r },
1079 { X86::SUB_Fp64 , X86::SUB_FST0r },
1080 { X86::SUB_Fp80 , X86::SUB_FST0r },
1083 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
1084 static const TableEntry ReverseST0Table[] = {
1085 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1086 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1087 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1088 { X86::DIV_Fp32 , X86::DIVR_FST0r },
1089 { X86::DIV_Fp64 , X86::DIVR_FST0r },
1090 { X86::DIV_Fp80 , X86::DIVR_FST0r },
1091 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1092 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1093 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1094 { X86::SUB_Fp32 , X86::SUBR_FST0r },
1095 { X86::SUB_Fp64 , X86::SUBR_FST0r },
1096 { X86::SUB_Fp80 , X86::SUBR_FST0r },
1099 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
1100 static const TableEntry ForwardSTiTable[] = {
1101 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1102 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1103 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1104 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1105 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1106 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1107 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1108 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1109 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1110 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1111 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1112 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1115 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
1116 static const TableEntry ReverseSTiTable[] = {
1117 { X86::ADD_Fp32 , X86::ADD_FrST0 },
1118 { X86::ADD_Fp64 , X86::ADD_FrST0 },
1119 { X86::ADD_Fp80 , X86::ADD_FrST0 },
1120 { X86::DIV_Fp32 , X86::DIV_FrST0 },
1121 { X86::DIV_Fp64 , X86::DIV_FrST0 },
1122 { X86::DIV_Fp80 , X86::DIV_FrST0 },
1123 { X86::MUL_Fp32 , X86::MUL_FrST0 },
1124 { X86::MUL_Fp64 , X86::MUL_FrST0 },
1125 { X86::MUL_Fp80 , X86::MUL_FrST0 },
1126 { X86::SUB_Fp32 , X86::SUB_FrST0 },
1127 { X86::SUB_Fp64 , X86::SUB_FrST0 },
1128 { X86::SUB_Fp80 , X86::SUB_FrST0 },
1132 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
1133 /// instructions which need to be simplified and possibly transformed.
1135 /// Result: ST(0) = fsub ST(0), ST(i)
1136 /// ST(i) = fsub ST(0), ST(i)
1137 /// ST(0) = fsubr ST(0), ST(i)
1138 /// ST(i) = fsubr ST(0), ST(i)
1140 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
1141 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1142 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1143 MachineInstr *MI = I;
1145 unsigned NumOperands = MI->getDesc().getNumOperands();
1146 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
1147 unsigned Dest = getFPReg(MI->getOperand(0));
1148 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1149 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1150 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1151 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1152 DebugLoc dl = MI->getDebugLoc();
1154 unsigned TOS = getStackEntry(0);
1156 // One of our operands must be on the top of the stack. If neither is yet, we
1157 // need to move one.
1158 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
1159 // We can choose to move either operand to the top of the stack. If one of
1160 // the operands is killed by this instruction, we want that one so that we
1161 // can update right on top of the old version.
1163 moveToTop(Op0, I); // Move dead operand to TOS.
1165 } else if (KillsOp1) {
1169 // All of the operands are live after this instruction executes, so we
1170 // cannot update on top of any operand. Because of this, we must
1171 // duplicate one of the stack elements to the top. It doesn't matter
1172 // which one we pick.
1174 duplicateToTop(Op0, Dest, I);
1178 } else if (!KillsOp0 && !KillsOp1) {
1179 // If we DO have one of our operands at the top of the stack, but we don't
1180 // have a dead operand, we must duplicate one of the operands to a new slot
1182 duplicateToTop(Op0, Dest, I);
1187 // Now we know that one of our operands is on the top of the stack, and at
1188 // least one of our operands is killed by this instruction.
1189 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
1190 "Stack conditions not set up right!");
1192 // We decide which form to use based on what is on the top of the stack, and
1193 // which operand is killed by this instruction.
1194 const TableEntry *InstTable;
1195 bool isForward = TOS == Op0;
1196 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
1199 InstTable = ForwardST0Table;
1201 InstTable = ReverseST0Table;
1204 InstTable = ForwardSTiTable;
1206 InstTable = ReverseSTiTable;
1209 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
1211 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
1213 // NotTOS - The register which is not on the top of stack...
1214 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
1216 // Replace the old instruction with a new instruction
1218 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1220 // If both operands are killed, pop one off of the stack in addition to
1221 // overwriting the other one.
1222 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
1223 assert(!updateST0 && "Should have updated other operand!");
1224 popStackAfter(I); // Pop the top of stack
1227 // Update stack information so that we know the destination register is now on
1229 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
1230 assert(UpdatedSlot < StackTop && Dest < 7);
1231 Stack[UpdatedSlot] = Dest;
1232 RegMap[Dest] = UpdatedSlot;
1233 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
1236 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
1237 /// register arguments and no explicit destinations.
1239 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
1240 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1241 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1242 MachineInstr *MI = I;
1244 unsigned NumOperands = MI->getDesc().getNumOperands();
1245 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
1246 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1247 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1248 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1249 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1251 // Make sure the first operand is on the top of stack, the other one can be
1255 // Change from the pseudo instruction to the concrete instruction.
1256 MI->getOperand(0).setReg(getSTReg(Op1));
1257 MI->RemoveOperand(1);
1258 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1260 // If any of the operands are killed by this instruction, free them.
1261 if (KillsOp0) freeStackSlotAfter(I, Op0);
1262 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
1265 /// handleCondMovFP - Handle two address conditional move instructions. These
1266 /// instructions move a st(i) register to st(0) iff a condition is true. These
1267 /// instructions require that the first operand is at the top of the stack, but
1268 /// otherwise don't modify the stack at all.
1269 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
1270 MachineInstr *MI = I;
1272 unsigned Op0 = getFPReg(MI->getOperand(0));
1273 unsigned Op1 = getFPReg(MI->getOperand(2));
1274 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1276 // The first operand *must* be on the top of the stack.
1279 // Change the second operand to the stack register that the operand is in.
1280 // Change from the pseudo instruction to the concrete instruction.
1281 MI->RemoveOperand(0);
1282 MI->RemoveOperand(1);
1283 MI->getOperand(0).setReg(getSTReg(Op1));
1284 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1286 // If we kill the second operand, make sure to pop it from the stack.
1287 if (Op0 != Op1 && KillsOp1) {
1288 // Get this value off of the register stack.
1289 freeStackSlotAfter(I, Op1);
1294 /// handleSpecialFP - Handle special instructions which behave unlike other
1295 /// floating point instructions. This is primarily intended for use by pseudo
1298 void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
1299 MachineInstr *MI = Inst;
1306 switch (MI->getOpcode()) {
1307 default: llvm_unreachable("Unknown SpecialFP instruction!");
1308 case TargetOpcode::COPY: {
1309 // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.
1310 const MachineOperand &MO1 = MI->getOperand(1);
1311 const MachineOperand &MO0 = MI->getOperand(0);
1312 bool KillsSrc = MI->killsRegister(MO1.getReg());
1315 unsigned DstFP = getFPReg(MO0);
1316 unsigned SrcFP = getFPReg(MO1);
1317 assert(isLive(SrcFP) && "Cannot copy dead register");
1319 // If the input operand is killed, we can just change the owner of the
1320 // incoming stack slot into the result.
1321 unsigned Slot = getSlot(SrcFP);
1322 Stack[Slot] = DstFP;
1323 RegMap[DstFP] = Slot;
1325 // For COPY we just duplicate the specified value to a new stack slot.
1326 // This could be made better, but would require substantial changes.
1327 duplicateToTop(SrcFP, DstFP, Inst);
1332 case TargetOpcode::IMPLICIT_DEF: {
1333 // All FP registers must be explicitly defined, so load a 0 instead.
1334 unsigned Reg = MI->getOperand(0).getReg() - X86::FP0;
1335 DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
1336 BuildMI(*MBB, Inst, MI->getDebugLoc(), TII->get(X86::LD_F0));
1341 case TargetOpcode::INLINEASM: {
1342 // The inline asm MachineInstr currently only *uses* FP registers for the
1343 // 'f' constraint. These should be turned into the current ST(x) register
1344 // in the machine instr.
1346 // There are special rules for x87 inline assembly. The compiler must know
1347 // exactly how many registers are popped and pushed implicitly by the asm.
1348 // Otherwise it is not possible to restore the stack state after the inline
1351 // There are 3 kinds of input operands:
1353 // 1. Popped inputs. These must appear at the stack top in ST0-STn. A
1354 // popped input operand must be in a fixed stack slot, and it is either
1355 // tied to an output operand, or in the clobber list. The MI has ST use
1356 // and def operands for these inputs.
1358 // 2. Fixed inputs. These inputs appear in fixed stack slots, but are
1359 // preserved by the inline asm. The fixed stack slots must be STn-STm
1360 // following the popped inputs. A fixed input operand cannot be tied to
1361 // an output or appear in the clobber list. The MI has ST use operands
1362 // and no defs for these inputs.
1364 // 3. Preserved inputs. These inputs use the "f" constraint which is
1365 // represented as an FP register. The inline asm won't change these
1368 // Outputs must be in ST registers, FP outputs are not allowed. Clobbered
1369 // registers do not count as output operands. The inline asm changes the
1370 // stack as if it popped all the popped inputs and then pushed all the
1373 // Scan the assembly for ST registers used, defined and clobbered. We can
1374 // only tell clobbers from defs by looking at the asm descriptor.
1375 unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
1376 unsigned NumOps = 0;
1377 SmallSet<unsigned, 1> FRegIdx;
1380 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
1381 i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) {
1382 unsigned Flags = MI->getOperand(i).getImm();
1384 NumOps = InlineAsm::getNumOperandRegisters(Flags);
1387 const MachineOperand &MO = MI->getOperand(i + 1);
1390 unsigned STReg = MO.getReg() - X86::FP0;
1394 // If the flag has a register class constraint, this must be an operand
1395 // with constraint "f". Record its index and continue.
1396 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
1397 FRegIdx.insert(i + 1);
1401 switch (InlineAsm::getKind(Flags)) {
1402 case InlineAsm::Kind_RegUse:
1403 STUses |= (1u << STReg);
1405 case InlineAsm::Kind_RegDef:
1406 case InlineAsm::Kind_RegDefEarlyClobber:
1407 STDefs |= (1u << STReg);
1409 STDeadDefs |= (1u << STReg);
1411 case InlineAsm::Kind_Clobber:
1412 STClobbers |= (1u << STReg);
1419 if (STUses && !isMask_32(STUses))
1420 MI->emitError("fixed input regs must be last on the x87 stack");
1421 unsigned NumSTUses = CountTrailingOnes_32(STUses);
1423 // Defs must be contiguous from the stack top. ST0-STn.
1424 if (STDefs && !isMask_32(STDefs)) {
1425 MI->emitError("output regs must be last on the x87 stack");
1426 STDefs = NextPowerOf2(STDefs) - 1;
1428 unsigned NumSTDefs = CountTrailingOnes_32(STDefs);
1430 // So must the clobbered stack slots. ST0-STm, m >= n.
1431 if (STClobbers && !isMask_32(STDefs | STClobbers))
1432 MI->emitError("clobbers must be last on the x87 stack");
1434 // Popped inputs are the ones that are also clobbered or defined.
1435 unsigned STPopped = STUses & (STDefs | STClobbers);
1436 if (STPopped && !isMask_32(STPopped))
1437 MI->emitError("implicitly popped regs must be last on the x87 stack");
1438 unsigned NumSTPopped = CountTrailingOnes_32(STPopped);
1440 DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
1441 << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");
1444 // If any input operand uses constraint "f", all output register
1445 // constraints must be early-clobber defs.
1446 for (unsigned I = 0, E = MI->getNumOperands(); I < E; ++I)
1447 if (FRegIdx.count(I)) {
1448 assert((1 << getFPReg(MI->getOperand(I)) & STDefs) == 0 &&
1449 "Operands with constraint \"f\" cannot overlap with defs");
1453 // Collect all FP registers (register operands with constraints "t", "u",
1454 // and "f") to kill afer the instruction.
1455 unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
1456 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1457 MachineOperand &Op = MI->getOperand(i);
1458 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1460 unsigned FPReg = getFPReg(Op);
1462 // If we kill this operand, make sure to pop it from the stack after the
1463 // asm. We just remember it for now, and pop them all off at the end in
1465 if (Op.isUse() && Op.isKill())
1466 FPKills |= 1U << FPReg;
1469 // Do not include registers that are implicitly popped by defs/clobbers.
1470 FPKills &= ~(STDefs | STClobbers);
1472 // Now we can rearrange the live registers to match what was requested.
1473 unsigned char STUsesArray[8];
1475 for (unsigned I = 0; I < NumSTUses; ++I)
1478 shuffleStackTop(STUsesArray, NumSTUses, Inst);
1479 DEBUG({dbgs() << "Before asm: "; dumpStack();});
1481 // With the stack layout fixed, rewrite the FP registers.
1482 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1483 MachineOperand &Op = MI->getOperand(i);
1484 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1487 unsigned FPReg = getFPReg(Op);
1489 if (FRegIdx.count(i))
1490 // Operand with constraint "f".
1491 Op.setReg(getSTReg(FPReg));
1493 // Operand with a single register class constraint ("t" or "u").
1494 Op.setReg(X86::ST0 + FPReg);
1497 // Simulate the inline asm popping its inputs and pushing its outputs.
1498 StackTop -= NumSTPopped;
1500 for (unsigned i = 0; i < NumSTDefs; ++i)
1501 pushReg(NumSTDefs - i - 1);
1503 // If this asm kills any FP registers (is the last use of them) we must
1504 // explicitly emit pop instructions for them. Do this now after the asm has
1505 // executed so that the ST(x) numbers are not off (which would happen if we
1506 // did this inline with operand rewriting).
1508 // Note: this might be a non-optimal pop sequence. We might be able to do
1509 // better by trying to pop in stack order or something.
1511 unsigned FPReg = countTrailingZeros(FPKills);
1513 freeStackSlotAfter(Inst, FPReg);
1514 FPKills &= ~(1U << FPReg);
1517 // Don't delete the inline asm!
1521 case X86::WIN_FTOL_32:
1522 case X86::WIN_FTOL_64: {
1523 // Push the operand into ST0.
1524 MachineOperand &Op = MI->getOperand(0);
1525 assert(Op.isUse() && Op.isReg() &&
1526 Op.getReg() >= X86::FP0 && Op.getReg() <= X86::FP6);
1527 unsigned FPReg = getFPReg(Op);
1529 moveToTop(FPReg, Inst);
1531 duplicateToTop(FPReg, FPReg, Inst);
1533 // Emit the call. This will pop the operand.
1534 BuildMI(*MBB, Inst, MI->getDebugLoc(), TII->get(X86::CALLpcrel32))
1535 .addExternalSymbol("_ftol2")
1536 .addReg(X86::ST0, RegState::ImplicitKill)
1537 .addReg(X86::ECX, RegState::ImplicitDefine)
1538 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
1539 .addReg(X86::EDX, RegState::Define | RegState::Implicit)
1540 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1550 // If RET has an FP register use operand, pass the first one in ST(0) and
1551 // the second one in ST(1).
1553 // Find the register operands.
1554 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1555 unsigned LiveMask = 0;
1557 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1558 MachineOperand &Op = MI->getOperand(i);
1559 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1561 // FP Register uses must be kills unless there are two uses of the same
1562 // register, in which case only one will be a kill.
1563 assert(Op.isUse() &&
1564 (Op.isKill() || // Marked kill.
1565 getFPReg(Op) == FirstFPRegOp || // Second instance.
1566 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1567 "Ret only defs operands, and values aren't live beyond it");
1569 if (FirstFPRegOp == ~0U)
1570 FirstFPRegOp = getFPReg(Op);
1572 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1573 SecondFPRegOp = getFPReg(Op);
1575 LiveMask |= (1 << getFPReg(Op));
1577 // Remove the operand so that later passes don't see it.
1578 MI->RemoveOperand(i);
1582 // We may have been carrying spurious live-ins, so make sure only the returned
1583 // registers are left live.
1584 adjustLiveRegs(LiveMask, MI);
1585 if (!LiveMask) return; // Quick check to see if any are possible.
1587 // There are only four possibilities here:
1588 // 1) we are returning a single FP value. In this case, it has to be in
1589 // ST(0) already, so just declare success by removing the value from the
1591 if (SecondFPRegOp == ~0U) {
1592 // Assert that the top of stack contains the right FP register.
1593 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1594 "Top of stack not the right register for RET!");
1596 // Ok, everything is good, mark the value as not being on the stack
1597 // anymore so that our assertion about the stack being empty at end of
1598 // block doesn't fire.
1603 // Otherwise, we are returning two values:
1604 // 2) If returning the same value for both, we only have one thing in the FP
1605 // stack. Consider: RET FP1, FP1
1606 if (StackTop == 1) {
1607 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1608 "Stack misconfiguration for RET!");
1610 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1611 // register to hold it.
1612 unsigned NewReg = ScratchFPReg;
1613 duplicateToTop(FirstFPRegOp, NewReg, MI);
1614 FirstFPRegOp = NewReg;
1617 /// Okay we know we have two different FPx operands now:
1618 assert(StackTop == 2 && "Must have two values live!");
1620 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1621 /// in ST(1). In this case, emit an fxch.
1622 if (getStackEntry(0) == SecondFPRegOp) {
1623 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1624 moveToTop(FirstFPRegOp, MI);
1627 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1628 /// ST(1). Just remove both from our understanding of the stack and return.
1629 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1630 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1635 Inst = MBB->erase(Inst); // Remove the pseudo instruction
1637 // We want to leave I pointing to the previous instruction, but what if we
1638 // just erased the first instruction?
1639 if (Inst == MBB->begin()) {
1640 DEBUG(dbgs() << "Inserting dummy KILL\n");
1641 Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
1646 void FPS::setKillFlags(MachineBasicBlock &MBB) const {
1647 const TargetRegisterInfo *TRI =
1648 MBB.getParent()->getSubtarget().getRegisterInfo();
1649 LivePhysRegs LPR(TRI);
1651 LPR.addLiveOuts(&MBB);
1653 for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
1655 if (I->isDebugValue())
1659 SmallVector<MachineOperand *, 2> Uses;
1660 MachineInstr &MI = *I;
1662 for (auto &MO : I->operands()) {
1666 unsigned Reg = MO.getReg() - X86::FP0;
1673 if (!LPR.contains(MO.getReg()))
1676 Uses.push_back(&MO);
1679 for (auto *MO : Uses)
1680 if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg()))
1683 LPR.stepBackward(MI);