1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the pass which converts floating point instructions from
11 // pseudo registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
15 // The x87 hardware tracks liveness of the stack registers, so it is necessary
16 // to implement exact liveness tracking between basic blocks. The CFG edges are
17 // partitioned into bundles where the same FP registers must be live in
18 // identical stack positions. Instructions are inserted at the end of each basic
19 // block to rearrange the live registers to match the outgoing bundle.
21 // This approach avoids splitting critical edges at the potential cost of more
22 // live register shuffling instructions when critical edges are present.
24 //===----------------------------------------------------------------------===//
27 #include "X86InstrInfo.h"
28 #include "llvm/ADT/DepthFirstIterator.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/CodeGen/EdgeBundles.h"
35 #include "llvm/CodeGen/LivePhysRegs.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetSubtargetInfo.h"
51 #define DEBUG_TYPE "x86-codegen"
53 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
54 STATISTIC(NumFP , "Number of floating point instructions");
57 const unsigned ScratchFPReg = 7;
59 struct FPS : public MachineFunctionPass {
61 FPS() : MachineFunctionPass(ID) {
62 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry());
63 // This is really only to keep valgrind quiet.
64 // The logic in isLive() is too much for it.
65 memset(Stack, 0, sizeof(Stack));
66 memset(RegMap, 0, sizeof(RegMap));
69 void getAnalysisUsage(AnalysisUsage &AU) const override {
71 AU.addRequired<EdgeBundles>();
72 AU.addPreservedID(MachineLoopInfoID);
73 AU.addPreservedID(MachineDominatorsID);
74 MachineFunctionPass::getAnalysisUsage(AU);
77 bool runOnMachineFunction(MachineFunction &MF) override;
79 const char *getPassName() const override { return "X86 FP Stackifier"; }
82 const TargetInstrInfo *TII; // Machine instruction info.
84 // Two CFG edges are related if they leave the same block, or enter the same
85 // block. The transitive closure of an edge under this relation is a
86 // LiveBundle. It represents a set of CFG edges where the live FP stack
87 // registers must be allocated identically in the x87 stack.
89 // A LiveBundle is usually all the edges leaving a block, or all the edges
90 // entering a block, but it can contain more edges if critical edges are
93 // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
94 // but the exact mapping of FP registers to stack slots is fixed later.
96 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
99 // Number of pre-assigned live registers in FixStack. This is 0 when the
100 // stack order has not yet been fixed.
103 // Assigned stack order for live-in registers.
104 // FixStack[i] == getStackEntry(i) for all i < FixCount.
105 unsigned char FixStack[8];
107 LiveBundle() : Mask(0), FixCount(0) {}
109 // Have the live registers been assigned a stack order yet?
110 bool isFixed() const { return !Mask || FixCount; }
113 // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
114 // with no live FP registers.
115 SmallVector<LiveBundle, 8> LiveBundles;
117 // The edge bundle analysis provides indices into the LiveBundles vector.
118 EdgeBundles *Bundles;
120 // Return a bitmask of FP registers in block's live-in list.
121 static unsigned calcLiveInMask(MachineBasicBlock *MBB) {
123 for (const auto &LI : MBB->liveins()) {
124 if (LI.PhysReg < X86::FP0 || LI.PhysReg > X86::FP6)
126 Mask |= 1 << (LI.PhysReg - X86::FP0);
131 // Partition all the CFG edges into LiveBundles.
132 void bundleCFG(MachineFunction &MF);
134 MachineBasicBlock *MBB; // Current basic block
136 // The hardware keeps track of how many FP registers are live, so we have
137 // to model that exactly. Usually, each live register corresponds to an
138 // FP<n> register, but when dealing with calls, returns, and inline
139 // assembly, it is sometimes necessary to have live scratch registers.
140 unsigned Stack[8]; // FP<n> Registers in each stack slot...
141 unsigned StackTop; // The current top of the FP stack.
144 NumFPRegs = 8 // Including scratch pseudo-registers.
147 // For each live FP<n> register, point to its Stack[] entry.
148 // The first entries correspond to FP0-FP6, the rest are scratch registers
149 // used when we need slightly different live registers than what the
150 // register allocator thinks.
151 unsigned RegMap[NumFPRegs];
153 // Set up our stack model to match the incoming registers to MBB.
154 void setupBlockStack();
156 // Shuffle live registers to match the expectations of successor blocks.
157 void finishBlockStack();
159 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
160 void dumpStack() const {
161 dbgs() << "Stack contents:";
162 for (unsigned i = 0; i != StackTop; ++i) {
163 dbgs() << " FP" << Stack[i];
164 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
169 /// getSlot - Return the stack slot number a particular register number is
171 unsigned getSlot(unsigned RegNo) const {
172 assert(RegNo < NumFPRegs && "Regno out of range!");
173 return RegMap[RegNo];
176 /// isLive - Is RegNo currently live in the stack?
177 bool isLive(unsigned RegNo) const {
178 unsigned Slot = getSlot(RegNo);
179 return Slot < StackTop && Stack[Slot] == RegNo;
182 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
183 unsigned getStackEntry(unsigned STi) const {
185 report_fatal_error("Access past stack top!");
186 return Stack[StackTop-1-STi];
189 /// getSTReg - Return the X86::ST(i) register which contains the specified
190 /// FP<RegNo> register.
191 unsigned getSTReg(unsigned RegNo) const {
192 return StackTop - 1 - getSlot(RegNo) + X86::ST0;
195 // pushReg - Push the specified FP<n> register onto the stack.
196 void pushReg(unsigned Reg) {
197 assert(Reg < NumFPRegs && "Register number out of range!");
199 report_fatal_error("Stack overflow!");
200 Stack[StackTop] = Reg;
201 RegMap[Reg] = StackTop++;
204 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
205 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
206 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
207 if (isAtTop(RegNo)) return;
209 unsigned STReg = getSTReg(RegNo);
210 unsigned RegOnTop = getStackEntry(0);
212 // Swap the slots the regs are in.
213 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
215 // Swap stack slot contents.
216 if (RegMap[RegOnTop] >= StackTop)
217 report_fatal_error("Access past stack top!");
218 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
220 // Emit an fxch to update the runtime processors version of the state.
221 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
225 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
226 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
227 unsigned STReg = getSTReg(RegNo);
228 pushReg(AsReg); // New register on top of stack
230 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
233 /// popStackAfter - Pop the current value off of the top of the FP stack
234 /// after the specified instruction.
235 void popStackAfter(MachineBasicBlock::iterator &I);
237 /// freeStackSlotAfter - Free the specified register from the register
238 /// stack, so that it is no longer in a register. If the register is
239 /// currently at the top of the stack, we just pop the current instruction,
240 /// otherwise we store the current top-of-stack into the specified slot,
241 /// then pop the top of stack.
242 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
244 /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
246 MachineBasicBlock::iterator
247 freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
249 /// Adjust the live registers to be the set in Mask.
250 void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
252 /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
253 /// st(0), FP reg FixStack[1] is st(1) etc.
254 void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
255 MachineBasicBlock::iterator I);
257 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
259 void handleCall(MachineBasicBlock::iterator &I);
260 void handleZeroArgFP(MachineBasicBlock::iterator &I);
261 void handleOneArgFP(MachineBasicBlock::iterator &I);
262 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
263 void handleTwoArgFP(MachineBasicBlock::iterator &I);
264 void handleCompareFP(MachineBasicBlock::iterator &I);
265 void handleCondMovFP(MachineBasicBlock::iterator &I);
266 void handleSpecialFP(MachineBasicBlock::iterator &I);
268 // Check if a COPY instruction is using FP registers.
269 static bool isFPCopy(MachineInstr *MI) {
270 unsigned DstReg = MI->getOperand(0).getReg();
271 unsigned SrcReg = MI->getOperand(1).getReg();
273 return X86::RFP80RegClass.contains(DstReg) ||
274 X86::RFP80RegClass.contains(SrcReg);
277 void setKillFlags(MachineBasicBlock &MBB) const;
282 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
284 /// getFPReg - Return the X86::FPx register number for the specified operand.
285 /// For example, this returns 3 for X86::FP3.
286 static unsigned getFPReg(const MachineOperand &MO) {
287 assert(MO.isReg() && "Expected an FP register!");
288 unsigned Reg = MO.getReg();
289 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
290 return Reg - X86::FP0;
293 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
294 /// register references into FP stack references.
296 bool FPS::runOnMachineFunction(MachineFunction &MF) {
297 // We only need to run this pass if there are any FP registers used in this
298 // function. If it is all integer, there is nothing for us to do!
299 bool FPIsUsed = false;
301 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
302 const MachineRegisterInfo &MRI = MF.getRegInfo();
303 for (unsigned i = 0; i <= 6; ++i)
304 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
310 if (!FPIsUsed) return false;
312 Bundles = &getAnalysis<EdgeBundles>();
313 TII = MF.getSubtarget().getInstrInfo();
315 // Prepare cross-MBB liveness.
320 // Process the function in depth first order so that we process at least one
321 // of the predecessors for every reachable block in the function.
322 SmallPtrSet<MachineBasicBlock*, 8> Processed;
323 MachineBasicBlock *Entry = MF.begin();
325 bool Changed = false;
326 for (MachineBasicBlock *BB : depth_first_ext(Entry, Processed))
327 Changed |= processBasicBlock(MF, *BB);
329 // Process any unreachable blocks in arbitrary order now.
330 if (MF.size() != Processed.size())
331 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
332 if (Processed.insert(BB).second)
333 Changed |= processBasicBlock(MF, *BB);
340 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and
341 /// live-out sets for the FP registers. Consistent means that the set of
342 /// registers live-out from a block is identical to the live-in set of all
343 /// successors. This is not enforced by the normal live-in lists since
344 /// registers may be implicitly defined, or not used by all successors.
345 void FPS::bundleCFG(MachineFunction &MF) {
346 assert(LiveBundles.empty() && "Stale data in LiveBundles");
347 LiveBundles.resize(Bundles->getNumBundles());
349 // Gather the actual live-in masks for all MBBs.
350 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
351 MachineBasicBlock *MBB = I;
352 const unsigned Mask = calcLiveInMask(MBB);
355 // Update MBB ingoing bundle mask.
356 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)].Mask |= Mask;
360 /// processBasicBlock - Loop over all of the instructions in the basic block,
361 /// transforming FP instructions into their stack form.
363 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
364 bool Changed = false;
370 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
371 MachineInstr *MI = I;
372 uint64_t Flags = MI->getDesc().TSFlags;
374 unsigned FPInstClass = Flags & X86II::FPTypeMask;
375 if (MI->isInlineAsm())
376 FPInstClass = X86II::SpecialFP;
378 if (MI->isCopy() && isFPCopy(MI))
379 FPInstClass = X86II::SpecialFP;
381 if (MI->isImplicitDef() &&
382 X86::RFP80RegClass.contains(MI->getOperand(0).getReg()))
383 FPInstClass = X86II::SpecialFP;
386 FPInstClass = X86II::SpecialFP;
388 if (FPInstClass == X86II::NotFP)
389 continue; // Efficiently ignore non-fp insts!
391 MachineInstr *PrevMI = nullptr;
393 PrevMI = std::prev(I);
395 ++NumFP; // Keep track of # of pseudo instrs
396 DEBUG(dbgs() << "\nFPInst:\t" << *MI);
398 // Get dead variables list now because the MI pointer may be deleted as part
400 SmallVector<unsigned, 8> DeadRegs;
401 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
402 const MachineOperand &MO = MI->getOperand(i);
403 if (MO.isReg() && MO.isDead())
404 DeadRegs.push_back(MO.getReg());
407 switch (FPInstClass) {
408 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
409 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
410 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
411 case X86II::TwoArgFP: handleTwoArgFP(I); break;
412 case X86II::CompareFP: handleCompareFP(I); break;
413 case X86II::CondMovFP: handleCondMovFP(I); break;
414 case X86II::SpecialFP: handleSpecialFP(I); break;
415 default: llvm_unreachable("Unknown FP Type!");
418 // Check to see if any of the values defined by this instruction are dead
419 // after definition. If so, pop them.
420 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
421 unsigned Reg = DeadRegs[i];
422 // Check if Reg is live on the stack. An inline-asm register operand that
423 // is in the clobber list and marked dead might not be live on the stack.
424 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
425 DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
426 freeStackSlotAfter(I, Reg-X86::FP0);
430 // Print out all of the instructions expanded to if -debug
432 MachineBasicBlock::iterator PrevI(PrevMI);
434 dbgs() << "Just deleted pseudo instruction\n";
436 MachineBasicBlock::iterator Start = I;
437 // Rewind to first instruction newly inserted.
438 while (Start != BB.begin() && std::prev(Start) != PrevI) --Start;
439 dbgs() << "Inserted instructions:\n\t";
440 Start->print(dbgs());
441 while (++Start != std::next(I)) {}
455 /// setupBlockStack - Use the live bundles to set up our model of the stack
456 /// to match predecessors' live out stack.
457 void FPS::setupBlockStack() {
458 DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber()
459 << " derived from " << MBB->getName() << ".\n");
461 // Get the live-in bundle for MBB.
462 const LiveBundle &Bundle =
463 LiveBundles[Bundles->getBundle(MBB->getNumber(), false)];
466 DEBUG(dbgs() << "Block has no FP live-ins.\n");
470 // Depth-first iteration should ensure that we always have an assigned stack.
471 assert(Bundle.isFixed() && "Reached block before any predecessors");
473 // Push the fixed live-in registers.
474 for (unsigned i = Bundle.FixCount; i > 0; --i) {
475 MBB->addLiveIn(X86::ST0+i-1);
476 DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP"
477 << unsigned(Bundle.FixStack[i-1]) << '\n');
478 pushReg(Bundle.FixStack[i-1]);
481 // Kill off unwanted live-ins. This can happen with a critical edge.
482 // FIXME: We could keep these live registers around as zombies. They may need
483 // to be revived at the end of a short block. It might save a few instrs.
484 adjustLiveRegs(calcLiveInMask(MBB), MBB->begin());
488 /// finishBlockStack - Revive live-outs that are implicitly defined out of
489 /// MBB. Shuffle live registers to match the expected fixed stack of any
490 /// predecessors, and ensure that all predecessors are expecting the same
492 void FPS::finishBlockStack() {
493 // The RET handling below takes care of return blocks for us.
494 if (MBB->succ_empty())
497 DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber()
498 << " derived from " << MBB->getName() << ".\n");
500 // Get MBB's live-out bundle.
501 unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true);
502 LiveBundle &Bundle = LiveBundles[BundleIdx];
504 // We may need to kill and define some registers to match successors.
505 // FIXME: This can probably be combined with the shuffle below.
506 MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
507 adjustLiveRegs(Bundle.Mask, Term);
510 DEBUG(dbgs() << "No live-outs.\n");
514 // Has the stack order been fixed yet?
515 DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
516 if (Bundle.isFixed()) {
517 DEBUG(dbgs() << "Shuffling stack to match.\n");
518 shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
520 // Not fixed yet, we get to choose.
521 DEBUG(dbgs() << "Fixing stack order now.\n");
522 Bundle.FixCount = StackTop;
523 for (unsigned i = 0; i < StackTop; ++i)
524 Bundle.FixStack[i] = getStackEntry(i);
529 //===----------------------------------------------------------------------===//
530 // Efficient Lookup Table Support
531 //===----------------------------------------------------------------------===//
537 bool operator<(const TableEntry &TE) const { return from < TE.from; }
538 friend bool operator<(const TableEntry &TE, unsigned V) {
541 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V,
542 const TableEntry &TE) {
548 static int Lookup(ArrayRef<TableEntry> Table, unsigned Opcode) {
549 const TableEntry *I = std::lower_bound(Table.begin(), Table.end(), Opcode);
550 if (I != Table.end() && I->from == Opcode)
556 #define ASSERT_SORTED(TABLE)
558 #define ASSERT_SORTED(TABLE) \
559 { static bool TABLE##Checked = false; \
560 if (!TABLE##Checked) { \
561 assert(std::is_sorted(std::begin(TABLE), std::end(TABLE)) && \
562 "All lookup tables must be sorted for efficient access!"); \
563 TABLE##Checked = true; \
568 //===----------------------------------------------------------------------===//
569 // Register File -> Register Stack Mapping Methods
570 //===----------------------------------------------------------------------===//
572 // OpcodeTable - Sorted map of register instructions to their stack version.
573 // The first element is an register file pseudo instruction, the second is the
574 // concrete X86 instruction which uses the register stack.
576 static const TableEntry OpcodeTable[] = {
577 { X86::ABS_Fp32 , X86::ABS_F },
578 { X86::ABS_Fp64 , X86::ABS_F },
579 { X86::ABS_Fp80 , X86::ABS_F },
580 { X86::ADD_Fp32m , X86::ADD_F32m },
581 { X86::ADD_Fp64m , X86::ADD_F64m },
582 { X86::ADD_Fp64m32 , X86::ADD_F32m },
583 { X86::ADD_Fp80m32 , X86::ADD_F32m },
584 { X86::ADD_Fp80m64 , X86::ADD_F64m },
585 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
586 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
587 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
588 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
589 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
590 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
591 { X86::CHS_Fp32 , X86::CHS_F },
592 { X86::CHS_Fp64 , X86::CHS_F },
593 { X86::CHS_Fp80 , X86::CHS_F },
594 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
595 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
596 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
597 { X86::CMOVB_Fp32 , X86::CMOVB_F },
598 { X86::CMOVB_Fp64 , X86::CMOVB_F },
599 { X86::CMOVB_Fp80 , X86::CMOVB_F },
600 { X86::CMOVE_Fp32 , X86::CMOVE_F },
601 { X86::CMOVE_Fp64 , X86::CMOVE_F },
602 { X86::CMOVE_Fp80 , X86::CMOVE_F },
603 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
604 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
605 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
606 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
607 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
608 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
609 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
610 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
611 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
612 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
613 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
614 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
615 { X86::CMOVP_Fp32 , X86::CMOVP_F },
616 { X86::CMOVP_Fp64 , X86::CMOVP_F },
617 { X86::CMOVP_Fp80 , X86::CMOVP_F },
618 { X86::COS_Fp32 , X86::COS_F },
619 { X86::COS_Fp64 , X86::COS_F },
620 { X86::COS_Fp80 , X86::COS_F },
621 { X86::DIVR_Fp32m , X86::DIVR_F32m },
622 { X86::DIVR_Fp64m , X86::DIVR_F64m },
623 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
624 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
625 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
626 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
627 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
628 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
629 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
630 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
631 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
632 { X86::DIV_Fp32m , X86::DIV_F32m },
633 { X86::DIV_Fp64m , X86::DIV_F64m },
634 { X86::DIV_Fp64m32 , X86::DIV_F32m },
635 { X86::DIV_Fp80m32 , X86::DIV_F32m },
636 { X86::DIV_Fp80m64 , X86::DIV_F64m },
637 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
638 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
639 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
640 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
641 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
642 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
643 { X86::ILD_Fp16m32 , X86::ILD_F16m },
644 { X86::ILD_Fp16m64 , X86::ILD_F16m },
645 { X86::ILD_Fp16m80 , X86::ILD_F16m },
646 { X86::ILD_Fp32m32 , X86::ILD_F32m },
647 { X86::ILD_Fp32m64 , X86::ILD_F32m },
648 { X86::ILD_Fp32m80 , X86::ILD_F32m },
649 { X86::ILD_Fp64m32 , X86::ILD_F64m },
650 { X86::ILD_Fp64m64 , X86::ILD_F64m },
651 { X86::ILD_Fp64m80 , X86::ILD_F64m },
652 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
653 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
654 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
655 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
656 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
657 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
658 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
659 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
660 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
661 { X86::IST_Fp16m32 , X86::IST_F16m },
662 { X86::IST_Fp16m64 , X86::IST_F16m },
663 { X86::IST_Fp16m80 , X86::IST_F16m },
664 { X86::IST_Fp32m32 , X86::IST_F32m },
665 { X86::IST_Fp32m64 , X86::IST_F32m },
666 { X86::IST_Fp32m80 , X86::IST_F32m },
667 { X86::IST_Fp64m32 , X86::IST_FP64m },
668 { X86::IST_Fp64m64 , X86::IST_FP64m },
669 { X86::IST_Fp64m80 , X86::IST_FP64m },
670 { X86::LD_Fp032 , X86::LD_F0 },
671 { X86::LD_Fp064 , X86::LD_F0 },
672 { X86::LD_Fp080 , X86::LD_F0 },
673 { X86::LD_Fp132 , X86::LD_F1 },
674 { X86::LD_Fp164 , X86::LD_F1 },
675 { X86::LD_Fp180 , X86::LD_F1 },
676 { X86::LD_Fp32m , X86::LD_F32m },
677 { X86::LD_Fp32m64 , X86::LD_F32m },
678 { X86::LD_Fp32m80 , X86::LD_F32m },
679 { X86::LD_Fp64m , X86::LD_F64m },
680 { X86::LD_Fp64m80 , X86::LD_F64m },
681 { X86::LD_Fp80m , X86::LD_F80m },
682 { X86::MUL_Fp32m , X86::MUL_F32m },
683 { X86::MUL_Fp64m , X86::MUL_F64m },
684 { X86::MUL_Fp64m32 , X86::MUL_F32m },
685 { X86::MUL_Fp80m32 , X86::MUL_F32m },
686 { X86::MUL_Fp80m64 , X86::MUL_F64m },
687 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
688 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
689 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
690 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
691 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
692 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
693 { X86::SIN_Fp32 , X86::SIN_F },
694 { X86::SIN_Fp64 , X86::SIN_F },
695 { X86::SIN_Fp80 , X86::SIN_F },
696 { X86::SQRT_Fp32 , X86::SQRT_F },
697 { X86::SQRT_Fp64 , X86::SQRT_F },
698 { X86::SQRT_Fp80 , X86::SQRT_F },
699 { X86::ST_Fp32m , X86::ST_F32m },
700 { X86::ST_Fp64m , X86::ST_F64m },
701 { X86::ST_Fp64m32 , X86::ST_F32m },
702 { X86::ST_Fp80m32 , X86::ST_F32m },
703 { X86::ST_Fp80m64 , X86::ST_F64m },
704 { X86::ST_FpP80m , X86::ST_FP80m },
705 { X86::SUBR_Fp32m , X86::SUBR_F32m },
706 { X86::SUBR_Fp64m , X86::SUBR_F64m },
707 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
708 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
709 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
710 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
711 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
712 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
713 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
714 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
715 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
716 { X86::SUB_Fp32m , X86::SUB_F32m },
717 { X86::SUB_Fp64m , X86::SUB_F64m },
718 { X86::SUB_Fp64m32 , X86::SUB_F32m },
719 { X86::SUB_Fp80m32 , X86::SUB_F32m },
720 { X86::SUB_Fp80m64 , X86::SUB_F64m },
721 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
722 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
723 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
724 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
725 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
726 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
727 { X86::TST_Fp32 , X86::TST_F },
728 { X86::TST_Fp64 , X86::TST_F },
729 { X86::TST_Fp80 , X86::TST_F },
730 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
731 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
732 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
733 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
734 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
735 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
738 static unsigned getConcreteOpcode(unsigned Opcode) {
739 ASSERT_SORTED(OpcodeTable);
740 int Opc = Lookup(OpcodeTable, Opcode);
741 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
745 //===----------------------------------------------------------------------===//
747 //===----------------------------------------------------------------------===//
749 // PopTable - Sorted map of instructions to their popping version. The first
750 // element is an instruction, the second is the version which pops.
752 static const TableEntry PopTable[] = {
753 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
755 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
756 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
758 { X86::IST_F16m , X86::IST_FP16m },
759 { X86::IST_F32m , X86::IST_FP32m },
761 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
763 { X86::ST_F32m , X86::ST_FP32m },
764 { X86::ST_F64m , X86::ST_FP64m },
765 { X86::ST_Frr , X86::ST_FPrr },
767 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
768 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
770 { X86::UCOM_FIr , X86::UCOM_FIPr },
772 { X86::UCOM_FPr , X86::UCOM_FPPr },
773 { X86::UCOM_Fr , X86::UCOM_FPr },
776 /// popStackAfter - Pop the current value off of the top of the FP stack after
777 /// the specified instruction. This attempts to be sneaky and combine the pop
778 /// into the instruction itself if possible. The iterator is left pointing to
779 /// the last instruction, be it a new pop instruction inserted, or the old
780 /// instruction if it was modified in place.
782 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
783 MachineInstr* MI = I;
784 DebugLoc dl = MI->getDebugLoc();
785 ASSERT_SORTED(PopTable);
787 report_fatal_error("Cannot pop empty stack!");
788 RegMap[Stack[--StackTop]] = ~0; // Update state
790 // Check to see if there is a popping version of this instruction...
791 int Opcode = Lookup(PopTable, I->getOpcode());
793 I->setDesc(TII->get(Opcode));
794 if (Opcode == X86::UCOM_FPPr)
796 } else { // Insert an explicit pop
797 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
801 /// freeStackSlotAfter - Free the specified register from the register stack, so
802 /// that it is no longer in a register. If the register is currently at the top
803 /// of the stack, we just pop the current instruction, otherwise we store the
804 /// current top-of-stack into the specified slot, then pop the top of stack.
805 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
806 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
811 // Otherwise, store the top of stack into the dead slot, killing the operand
812 // without having to add in an explicit xchg then pop.
814 I = freeStackSlotBefore(++I, FPRegNo);
817 /// freeStackSlotBefore - Free the specified register without trying any
819 MachineBasicBlock::iterator
820 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
821 unsigned STReg = getSTReg(FPRegNo);
822 unsigned OldSlot = getSlot(FPRegNo);
823 unsigned TopReg = Stack[StackTop-1];
824 Stack[OldSlot] = TopReg;
825 RegMap[TopReg] = OldSlot;
826 RegMap[FPRegNo] = ~0;
827 Stack[--StackTop] = ~0;
828 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
833 /// adjustLiveRegs - Kill and revive registers such that exactly the FP
834 /// registers with a bit in Mask are live.
835 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
836 unsigned Defs = Mask;
838 for (unsigned i = 0; i < StackTop; ++i) {
839 unsigned RegNo = Stack[i];
840 if (!(Defs & (1 << RegNo)))
841 // This register is live, but we don't want it.
842 Kills |= (1 << RegNo);
844 // We don't need to imp-def this live register.
845 Defs &= ~(1 << RegNo);
847 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
849 // Produce implicit-defs for free by using killed registers.
850 while (Kills && Defs) {
851 unsigned KReg = countTrailingZeros(Kills);
852 unsigned DReg = countTrailingZeros(Defs);
853 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n");
854 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
855 std::swap(RegMap[KReg], RegMap[DReg]);
856 Kills &= ~(1 << KReg);
857 Defs &= ~(1 << DReg);
860 // Kill registers by popping.
861 if (Kills && I != MBB->begin()) {
862 MachineBasicBlock::iterator I2 = std::prev(I);
864 unsigned KReg = getStackEntry(0);
865 if (!(Kills & (1 << KReg)))
867 DEBUG(dbgs() << "Popping %FP" << KReg << "\n");
869 Kills &= ~(1 << KReg);
873 // Manually kill the rest.
875 unsigned KReg = countTrailingZeros(Kills);
876 DEBUG(dbgs() << "Killing %FP" << KReg << "\n");
877 freeStackSlotBefore(I, KReg);
878 Kills &= ~(1 << KReg);
881 // Load zeros for all the imp-defs.
883 unsigned DReg = countTrailingZeros(Defs);
884 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n");
885 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
887 Defs &= ~(1 << DReg);
890 // Now we should have the correct registers live.
892 assert(StackTop == countPopulation(Mask) && "Live count mismatch");
895 /// shuffleStackTop - emit fxch instructions before I to shuffle the top
896 /// FixCount entries into the order given by FixStack.
897 /// FIXME: Is there a better algorithm than insertion sort?
898 void FPS::shuffleStackTop(const unsigned char *FixStack,
900 MachineBasicBlock::iterator I) {
901 // Move items into place, starting from the desired stack bottom.
903 // Old register at position FixCount.
904 unsigned OldReg = getStackEntry(FixCount);
905 // Desired register at position FixCount.
906 unsigned Reg = FixStack[FixCount];
909 // (Reg st0) (OldReg st0) = (Reg OldReg st0)
912 moveToTop(OldReg, I);
918 //===----------------------------------------------------------------------===//
919 // Instruction transformation implementation
920 //===----------------------------------------------------------------------===//
922 void FPS::handleCall(MachineBasicBlock::iterator &I) {
923 unsigned STReturns = 0;
925 for (const auto &MO : I->operands()) {
929 unsigned R = MO.getReg() - X86::FP0;
932 assert(MO.isDef() && MO.isImplicit());
937 unsigned N = countTrailingOnes(STReturns);
939 // FP registers used for function return must be consecutive starting at
941 assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2));
943 for (unsigned I = 0; I < N; ++I)
947 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
949 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
950 MachineInstr *MI = I;
951 unsigned DestReg = getFPReg(MI->getOperand(0));
953 // Change from the pseudo instruction to the concrete instruction.
954 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
955 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
957 // Result gets pushed on the stack.
961 /// handleOneArgFP - fst <mem>, ST(0)
963 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
964 MachineInstr *MI = I;
965 unsigned NumOps = MI->getDesc().getNumOperands();
966 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
967 "Can only handle fst* & ftst instructions!");
969 // Is this the last use of the source register?
970 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
971 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
973 // FISTP64m is strange because there isn't a non-popping versions.
974 // If we have one _and_ we don't want to pop the operand, duplicate the value
975 // on the stack instead of moving it. This ensure that popping the value is
977 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
980 (MI->getOpcode() == X86::IST_Fp64m32 ||
981 MI->getOpcode() == X86::ISTT_Fp16m32 ||
982 MI->getOpcode() == X86::ISTT_Fp32m32 ||
983 MI->getOpcode() == X86::ISTT_Fp64m32 ||
984 MI->getOpcode() == X86::IST_Fp64m64 ||
985 MI->getOpcode() == X86::ISTT_Fp16m64 ||
986 MI->getOpcode() == X86::ISTT_Fp32m64 ||
987 MI->getOpcode() == X86::ISTT_Fp64m64 ||
988 MI->getOpcode() == X86::IST_Fp64m80 ||
989 MI->getOpcode() == X86::ISTT_Fp16m80 ||
990 MI->getOpcode() == X86::ISTT_Fp32m80 ||
991 MI->getOpcode() == X86::ISTT_Fp64m80 ||
992 MI->getOpcode() == X86::ST_FpP80m)) {
993 duplicateToTop(Reg, ScratchFPReg, I);
995 moveToTop(Reg, I); // Move to the top of the stack...
998 // Convert from the pseudo instruction to the concrete instruction.
999 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
1000 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1002 if (MI->getOpcode() == X86::IST_FP64m ||
1003 MI->getOpcode() == X86::ISTT_FP16m ||
1004 MI->getOpcode() == X86::ISTT_FP32m ||
1005 MI->getOpcode() == X86::ISTT_FP64m ||
1006 MI->getOpcode() == X86::ST_FP80m) {
1008 report_fatal_error("Stack empty??");
1010 } else if (KillsSrc) { // Last use of operand?
1016 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
1017 /// replace the value with a newly computed value. These instructions may have
1018 /// non-fp operands after their FP operands.
1022 /// R1 = fadd R2, [mem]
1024 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
1025 MachineInstr *MI = I;
1027 unsigned NumOps = MI->getDesc().getNumOperands();
1028 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1031 // Is this the last use of the source register?
1032 unsigned Reg = getFPReg(MI->getOperand(1));
1033 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
1036 // If this is the last use of the source register, just make sure it's on
1037 // the top of the stack.
1040 report_fatal_error("Stack cannot be empty!");
1042 pushReg(getFPReg(MI->getOperand(0)));
1044 // If this is not the last use of the source register, _copy_ it to the top
1046 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
1049 // Change from the pseudo instruction to the concrete instruction.
1050 MI->RemoveOperand(1); // Drop the source operand.
1051 MI->RemoveOperand(0); // Drop the destination operand.
1052 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1056 //===----------------------------------------------------------------------===//
1057 // Define tables of various ways to map pseudo instructions
1060 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
1061 static const TableEntry ForwardST0Table[] = {
1062 { X86::ADD_Fp32 , X86::ADD_FST0r },
1063 { X86::ADD_Fp64 , X86::ADD_FST0r },
1064 { X86::ADD_Fp80 , X86::ADD_FST0r },
1065 { X86::DIV_Fp32 , X86::DIV_FST0r },
1066 { X86::DIV_Fp64 , X86::DIV_FST0r },
1067 { X86::DIV_Fp80 , X86::DIV_FST0r },
1068 { X86::MUL_Fp32 , X86::MUL_FST0r },
1069 { X86::MUL_Fp64 , X86::MUL_FST0r },
1070 { X86::MUL_Fp80 , X86::MUL_FST0r },
1071 { X86::SUB_Fp32 , X86::SUB_FST0r },
1072 { X86::SUB_Fp64 , X86::SUB_FST0r },
1073 { X86::SUB_Fp80 , X86::SUB_FST0r },
1076 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
1077 static const TableEntry ReverseST0Table[] = {
1078 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1079 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1080 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1081 { X86::DIV_Fp32 , X86::DIVR_FST0r },
1082 { X86::DIV_Fp64 , X86::DIVR_FST0r },
1083 { X86::DIV_Fp80 , X86::DIVR_FST0r },
1084 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1085 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1086 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1087 { X86::SUB_Fp32 , X86::SUBR_FST0r },
1088 { X86::SUB_Fp64 , X86::SUBR_FST0r },
1089 { X86::SUB_Fp80 , X86::SUBR_FST0r },
1092 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
1093 static const TableEntry ForwardSTiTable[] = {
1094 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1095 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1096 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1097 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1098 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1099 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1100 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1101 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1102 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1103 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1104 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1105 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1108 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
1109 static const TableEntry ReverseSTiTable[] = {
1110 { X86::ADD_Fp32 , X86::ADD_FrST0 },
1111 { X86::ADD_Fp64 , X86::ADD_FrST0 },
1112 { X86::ADD_Fp80 , X86::ADD_FrST0 },
1113 { X86::DIV_Fp32 , X86::DIV_FrST0 },
1114 { X86::DIV_Fp64 , X86::DIV_FrST0 },
1115 { X86::DIV_Fp80 , X86::DIV_FrST0 },
1116 { X86::MUL_Fp32 , X86::MUL_FrST0 },
1117 { X86::MUL_Fp64 , X86::MUL_FrST0 },
1118 { X86::MUL_Fp80 , X86::MUL_FrST0 },
1119 { X86::SUB_Fp32 , X86::SUB_FrST0 },
1120 { X86::SUB_Fp64 , X86::SUB_FrST0 },
1121 { X86::SUB_Fp80 , X86::SUB_FrST0 },
1125 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
1126 /// instructions which need to be simplified and possibly transformed.
1128 /// Result: ST(0) = fsub ST(0), ST(i)
1129 /// ST(i) = fsub ST(0), ST(i)
1130 /// ST(0) = fsubr ST(0), ST(i)
1131 /// ST(i) = fsubr ST(0), ST(i)
1133 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
1134 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1135 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1136 MachineInstr *MI = I;
1138 unsigned NumOperands = MI->getDesc().getNumOperands();
1139 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
1140 unsigned Dest = getFPReg(MI->getOperand(0));
1141 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1142 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1143 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1144 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1145 DebugLoc dl = MI->getDebugLoc();
1147 unsigned TOS = getStackEntry(0);
1149 // One of our operands must be on the top of the stack. If neither is yet, we
1150 // need to move one.
1151 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
1152 // We can choose to move either operand to the top of the stack. If one of
1153 // the operands is killed by this instruction, we want that one so that we
1154 // can update right on top of the old version.
1156 moveToTop(Op0, I); // Move dead operand to TOS.
1158 } else if (KillsOp1) {
1162 // All of the operands are live after this instruction executes, so we
1163 // cannot update on top of any operand. Because of this, we must
1164 // duplicate one of the stack elements to the top. It doesn't matter
1165 // which one we pick.
1167 duplicateToTop(Op0, Dest, I);
1171 } else if (!KillsOp0 && !KillsOp1) {
1172 // If we DO have one of our operands at the top of the stack, but we don't
1173 // have a dead operand, we must duplicate one of the operands to a new slot
1175 duplicateToTop(Op0, Dest, I);
1180 // Now we know that one of our operands is on the top of the stack, and at
1181 // least one of our operands is killed by this instruction.
1182 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
1183 "Stack conditions not set up right!");
1185 // We decide which form to use based on what is on the top of the stack, and
1186 // which operand is killed by this instruction.
1187 ArrayRef<TableEntry> InstTable;
1188 bool isForward = TOS == Op0;
1189 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
1192 InstTable = ForwardST0Table;
1194 InstTable = ReverseST0Table;
1197 InstTable = ForwardSTiTable;
1199 InstTable = ReverseSTiTable;
1202 int Opcode = Lookup(InstTable, MI->getOpcode());
1203 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
1205 // NotTOS - The register which is not on the top of stack...
1206 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
1208 // Replace the old instruction with a new instruction
1210 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1212 // If both operands are killed, pop one off of the stack in addition to
1213 // overwriting the other one.
1214 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
1215 assert(!updateST0 && "Should have updated other operand!");
1216 popStackAfter(I); // Pop the top of stack
1219 // Update stack information so that we know the destination register is now on
1221 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
1222 assert(UpdatedSlot < StackTop && Dest < 7);
1223 Stack[UpdatedSlot] = Dest;
1224 RegMap[Dest] = UpdatedSlot;
1225 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
1228 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
1229 /// register arguments and no explicit destinations.
1231 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
1232 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
1233 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
1234 MachineInstr *MI = I;
1236 unsigned NumOperands = MI->getDesc().getNumOperands();
1237 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
1238 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
1239 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
1240 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
1241 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1243 // Make sure the first operand is on the top of stack, the other one can be
1247 // Change from the pseudo instruction to the concrete instruction.
1248 MI->getOperand(0).setReg(getSTReg(Op1));
1249 MI->RemoveOperand(1);
1250 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1252 // If any of the operands are killed by this instruction, free them.
1253 if (KillsOp0) freeStackSlotAfter(I, Op0);
1254 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
1257 /// handleCondMovFP - Handle two address conditional move instructions. These
1258 /// instructions move a st(i) register to st(0) iff a condition is true. These
1259 /// instructions require that the first operand is at the top of the stack, but
1260 /// otherwise don't modify the stack at all.
1261 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
1262 MachineInstr *MI = I;
1264 unsigned Op0 = getFPReg(MI->getOperand(0));
1265 unsigned Op1 = getFPReg(MI->getOperand(2));
1266 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
1268 // The first operand *must* be on the top of the stack.
1271 // Change the second operand to the stack register that the operand is in.
1272 // Change from the pseudo instruction to the concrete instruction.
1273 MI->RemoveOperand(0);
1274 MI->RemoveOperand(1);
1275 MI->getOperand(0).setReg(getSTReg(Op1));
1276 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
1278 // If we kill the second operand, make sure to pop it from the stack.
1279 if (Op0 != Op1 && KillsOp1) {
1280 // Get this value off of the register stack.
1281 freeStackSlotAfter(I, Op1);
1286 /// handleSpecialFP - Handle special instructions which behave unlike other
1287 /// floating point instructions. This is primarily intended for use by pseudo
1290 void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
1291 MachineInstr *MI = Inst;
1298 switch (MI->getOpcode()) {
1299 default: llvm_unreachable("Unknown SpecialFP instruction!");
1300 case TargetOpcode::COPY: {
1301 // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.
1302 const MachineOperand &MO1 = MI->getOperand(1);
1303 const MachineOperand &MO0 = MI->getOperand(0);
1304 bool KillsSrc = MI->killsRegister(MO1.getReg());
1307 unsigned DstFP = getFPReg(MO0);
1308 unsigned SrcFP = getFPReg(MO1);
1309 assert(isLive(SrcFP) && "Cannot copy dead register");
1311 // If the input operand is killed, we can just change the owner of the
1312 // incoming stack slot into the result.
1313 unsigned Slot = getSlot(SrcFP);
1314 Stack[Slot] = DstFP;
1315 RegMap[DstFP] = Slot;
1317 // For COPY we just duplicate the specified value to a new stack slot.
1318 // This could be made better, but would require substantial changes.
1319 duplicateToTop(SrcFP, DstFP, Inst);
1324 case TargetOpcode::IMPLICIT_DEF: {
1325 // All FP registers must be explicitly defined, so load a 0 instead.
1326 unsigned Reg = MI->getOperand(0).getReg() - X86::FP0;
1327 DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
1328 BuildMI(*MBB, Inst, MI->getDebugLoc(), TII->get(X86::LD_F0));
1333 case TargetOpcode::INLINEASM: {
1334 // The inline asm MachineInstr currently only *uses* FP registers for the
1335 // 'f' constraint. These should be turned into the current ST(x) register
1336 // in the machine instr.
1338 // There are special rules for x87 inline assembly. The compiler must know
1339 // exactly how many registers are popped and pushed implicitly by the asm.
1340 // Otherwise it is not possible to restore the stack state after the inline
1343 // There are 3 kinds of input operands:
1345 // 1. Popped inputs. These must appear at the stack top in ST0-STn. A
1346 // popped input operand must be in a fixed stack slot, and it is either
1347 // tied to an output operand, or in the clobber list. The MI has ST use
1348 // and def operands for these inputs.
1350 // 2. Fixed inputs. These inputs appear in fixed stack slots, but are
1351 // preserved by the inline asm. The fixed stack slots must be STn-STm
1352 // following the popped inputs. A fixed input operand cannot be tied to
1353 // an output or appear in the clobber list. The MI has ST use operands
1354 // and no defs for these inputs.
1356 // 3. Preserved inputs. These inputs use the "f" constraint which is
1357 // represented as an FP register. The inline asm won't change these
1360 // Outputs must be in ST registers, FP outputs are not allowed. Clobbered
1361 // registers do not count as output operands. The inline asm changes the
1362 // stack as if it popped all the popped inputs and then pushed all the
1365 // Scan the assembly for ST registers used, defined and clobbered. We can
1366 // only tell clobbers from defs by looking at the asm descriptor.
1367 unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
1368 unsigned NumOps = 0;
1369 SmallSet<unsigned, 1> FRegIdx;
1372 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
1373 i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) {
1374 unsigned Flags = MI->getOperand(i).getImm();
1376 NumOps = InlineAsm::getNumOperandRegisters(Flags);
1379 const MachineOperand &MO = MI->getOperand(i + 1);
1382 unsigned STReg = MO.getReg() - X86::FP0;
1386 // If the flag has a register class constraint, this must be an operand
1387 // with constraint "f". Record its index and continue.
1388 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
1389 FRegIdx.insert(i + 1);
1393 switch (InlineAsm::getKind(Flags)) {
1394 case InlineAsm::Kind_RegUse:
1395 STUses |= (1u << STReg);
1397 case InlineAsm::Kind_RegDef:
1398 case InlineAsm::Kind_RegDefEarlyClobber:
1399 STDefs |= (1u << STReg);
1401 STDeadDefs |= (1u << STReg);
1403 case InlineAsm::Kind_Clobber:
1404 STClobbers |= (1u << STReg);
1411 if (STUses && !isMask_32(STUses))
1412 MI->emitError("fixed input regs must be last on the x87 stack");
1413 unsigned NumSTUses = countTrailingOnes(STUses);
1415 // Defs must be contiguous from the stack top. ST0-STn.
1416 if (STDefs && !isMask_32(STDefs)) {
1417 MI->emitError("output regs must be last on the x87 stack");
1418 STDefs = NextPowerOf2(STDefs) - 1;
1420 unsigned NumSTDefs = countTrailingOnes(STDefs);
1422 // So must the clobbered stack slots. ST0-STm, m >= n.
1423 if (STClobbers && !isMask_32(STDefs | STClobbers))
1424 MI->emitError("clobbers must be last on the x87 stack");
1426 // Popped inputs are the ones that are also clobbered or defined.
1427 unsigned STPopped = STUses & (STDefs | STClobbers);
1428 if (STPopped && !isMask_32(STPopped))
1429 MI->emitError("implicitly popped regs must be last on the x87 stack");
1430 unsigned NumSTPopped = countTrailingOnes(STPopped);
1432 DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
1433 << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");
1436 // If any input operand uses constraint "f", all output register
1437 // constraints must be early-clobber defs.
1438 for (unsigned I = 0, E = MI->getNumOperands(); I < E; ++I)
1439 if (FRegIdx.count(I)) {
1440 assert((1 << getFPReg(MI->getOperand(I)) & STDefs) == 0 &&
1441 "Operands with constraint \"f\" cannot overlap with defs");
1445 // Collect all FP registers (register operands with constraints "t", "u",
1446 // and "f") to kill afer the instruction.
1447 unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
1448 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1449 MachineOperand &Op = MI->getOperand(i);
1450 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1452 unsigned FPReg = getFPReg(Op);
1454 // If we kill this operand, make sure to pop it from the stack after the
1455 // asm. We just remember it for now, and pop them all off at the end in
1457 if (Op.isUse() && Op.isKill())
1458 FPKills |= 1U << FPReg;
1461 // Do not include registers that are implicitly popped by defs/clobbers.
1462 FPKills &= ~(STDefs | STClobbers);
1464 // Now we can rearrange the live registers to match what was requested.
1465 unsigned char STUsesArray[8];
1467 for (unsigned I = 0; I < NumSTUses; ++I)
1470 shuffleStackTop(STUsesArray, NumSTUses, Inst);
1471 DEBUG({dbgs() << "Before asm: "; dumpStack();});
1473 // With the stack layout fixed, rewrite the FP registers.
1474 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1475 MachineOperand &Op = MI->getOperand(i);
1476 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1479 unsigned FPReg = getFPReg(Op);
1481 if (FRegIdx.count(i))
1482 // Operand with constraint "f".
1483 Op.setReg(getSTReg(FPReg));
1485 // Operand with a single register class constraint ("t" or "u").
1486 Op.setReg(X86::ST0 + FPReg);
1489 // Simulate the inline asm popping its inputs and pushing its outputs.
1490 StackTop -= NumSTPopped;
1492 for (unsigned i = 0; i < NumSTDefs; ++i)
1493 pushReg(NumSTDefs - i - 1);
1495 // If this asm kills any FP registers (is the last use of them) we must
1496 // explicitly emit pop instructions for them. Do this now after the asm has
1497 // executed so that the ST(x) numbers are not off (which would happen if we
1498 // did this inline with operand rewriting).
1500 // Note: this might be a non-optimal pop sequence. We might be able to do
1501 // better by trying to pop in stack order or something.
1503 unsigned FPReg = countTrailingZeros(FPKills);
1505 freeStackSlotAfter(Inst, FPReg);
1506 FPKills &= ~(1U << FPReg);
1509 // Don't delete the inline asm!
1517 // If RET has an FP register use operand, pass the first one in ST(0) and
1518 // the second one in ST(1).
1520 // Find the register operands.
1521 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1522 unsigned LiveMask = 0;
1524 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1525 MachineOperand &Op = MI->getOperand(i);
1526 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1528 // FP Register uses must be kills unless there are two uses of the same
1529 // register, in which case only one will be a kill.
1530 assert(Op.isUse() &&
1531 (Op.isKill() || // Marked kill.
1532 getFPReg(Op) == FirstFPRegOp || // Second instance.
1533 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1534 "Ret only defs operands, and values aren't live beyond it");
1536 if (FirstFPRegOp == ~0U)
1537 FirstFPRegOp = getFPReg(Op);
1539 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1540 SecondFPRegOp = getFPReg(Op);
1542 LiveMask |= (1 << getFPReg(Op));
1544 // Remove the operand so that later passes don't see it.
1545 MI->RemoveOperand(i);
1549 // We may have been carrying spurious live-ins, so make sure only the returned
1550 // registers are left live.
1551 adjustLiveRegs(LiveMask, MI);
1552 if (!LiveMask) return; // Quick check to see if any are possible.
1554 // There are only four possibilities here:
1555 // 1) we are returning a single FP value. In this case, it has to be in
1556 // ST(0) already, so just declare success by removing the value from the
1558 if (SecondFPRegOp == ~0U) {
1559 // Assert that the top of stack contains the right FP register.
1560 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1561 "Top of stack not the right register for RET!");
1563 // Ok, everything is good, mark the value as not being on the stack
1564 // anymore so that our assertion about the stack being empty at end of
1565 // block doesn't fire.
1570 // Otherwise, we are returning two values:
1571 // 2) If returning the same value for both, we only have one thing in the FP
1572 // stack. Consider: RET FP1, FP1
1573 if (StackTop == 1) {
1574 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1575 "Stack misconfiguration for RET!");
1577 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1578 // register to hold it.
1579 unsigned NewReg = ScratchFPReg;
1580 duplicateToTop(FirstFPRegOp, NewReg, MI);
1581 FirstFPRegOp = NewReg;
1584 /// Okay we know we have two different FPx operands now:
1585 assert(StackTop == 2 && "Must have two values live!");
1587 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1588 /// in ST(1). In this case, emit an fxch.
1589 if (getStackEntry(0) == SecondFPRegOp) {
1590 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1591 moveToTop(FirstFPRegOp, MI);
1594 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1595 /// ST(1). Just remove both from our understanding of the stack and return.
1596 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1597 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1602 Inst = MBB->erase(Inst); // Remove the pseudo instruction
1604 // We want to leave I pointing to the previous instruction, but what if we
1605 // just erased the first instruction?
1606 if (Inst == MBB->begin()) {
1607 DEBUG(dbgs() << "Inserting dummy KILL\n");
1608 Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
1613 void FPS::setKillFlags(MachineBasicBlock &MBB) const {
1614 const TargetRegisterInfo *TRI =
1615 MBB.getParent()->getSubtarget().getRegisterInfo();
1616 LivePhysRegs LPR(TRI);
1618 LPR.addLiveOuts(&MBB);
1620 for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
1622 if (I->isDebugValue())
1625 std::bitset<8> Defs;
1626 SmallVector<MachineOperand *, 2> Uses;
1627 MachineInstr &MI = *I;
1629 for (auto &MO : I->operands()) {
1633 unsigned Reg = MO.getReg() - X86::FP0;
1640 if (!LPR.contains(MO.getReg()))
1643 Uses.push_back(&MO);
1646 for (auto *MO : Uses)
1647 if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg()))
1650 LPR.stepBackward(MI);