1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/WinEHFuncInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
37 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
38 unsigned StackAlignOverride)
39 : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
40 STI.is64Bit() ? -8 : -4),
41 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
42 // Cache a bunch of frame-related predicates for this subtarget.
43 SlotSize = TRI->getSlotSize();
44 Is64Bit = STI.is64Bit();
45 IsLP64 = STI.isTarget64BitLP64();
46 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
47 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
48 StackPtr = TRI->getStackRegister();
51 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
52 return !MF.getFrameInfo()->hasVarSizedObjects() &&
53 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
56 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
57 /// call frame pseudos can be simplified. Having a FP, as in the default
58 /// implementation, is not sufficient here since we can't always use it.
59 /// Use a more nuanced condition.
61 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
62 return hasReservedCallFrame(MF) ||
63 (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
64 TRI->hasBasePointer(MF);
67 // needsFrameIndexResolution - Do we need to perform FI resolution for
68 // this function. Normally, this is required only when the function
69 // has any stack objects. However, FI resolution actually has another job,
70 // not apparent from the title - it resolves callframesetup/destroy
71 // that were not simplified earlier.
72 // So, this is required for x86 functions that have push sequences even
73 // when there are no stack objects.
75 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
76 return MF.getFrameInfo()->hasStackObjects() ||
77 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
80 /// hasFP - Return true if the specified function should have a dedicated frame
81 /// pointer register. This is true if the function has variable sized allocas
82 /// or if frame pointer elimination is disabled.
83 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
84 const MachineFrameInfo *MFI = MF.getFrameInfo();
85 const MachineModuleInfo &MMI = MF.getMMI();
87 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
88 TRI->needsStackRealignment(MF) ||
89 MFI->hasVarSizedObjects() ||
90 MFI->isFrameAddressTaken() || MFI->hasOpaqueSPAdjustment() ||
91 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
92 MMI.callsUnwindInit() || MMI.hasEHFunclets() || MMI.callsEHReturn() ||
93 MFI->hasStackMap() || MFI->hasPatchPoint());
96 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
100 return X86::SUB64ri32;
103 return X86::SUB32ri8;
108 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
111 return X86::ADD64ri8;
112 return X86::ADD64ri32;
115 return X86::ADD32ri8;
120 static unsigned getSUBrrOpcode(unsigned isLP64) {
121 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
124 static unsigned getADDrrOpcode(unsigned isLP64) {
125 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
128 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
131 return X86::AND64ri8;
132 return X86::AND64ri32;
135 return X86::AND32ri8;
139 static unsigned getLEArOpcode(unsigned IsLP64) {
140 return IsLP64 ? X86::LEA64r : X86::LEA32r;
143 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
144 /// when it reaches the "return" instruction. We can then pop a stack object
145 /// to this register without worry about clobbering it.
146 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator &MBBI,
148 const TargetRegisterInfo *TRI,
150 const MachineFunction *MF = MBB.getParent();
151 const Function *F = MF->getFunction();
152 if (!F || MF->getMMI().callsEHReturn())
155 static const uint16_t CallerSavedRegs32Bit[] = {
156 X86::EAX, X86::EDX, X86::ECX, 0
159 static const uint16_t CallerSavedRegs64Bit[] = {
160 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
161 X86::R8, X86::R9, X86::R10, X86::R11, 0
164 unsigned Opc = MBBI->getOpcode();
171 case X86::TCRETURNdi:
172 case X86::TCRETURNri:
173 case X86::TCRETURNmi:
174 case X86::TCRETURNdi64:
175 case X86::TCRETURNri64:
176 case X86::TCRETURNmi64:
178 case X86::EH_RETURN64: {
179 SmallSet<uint16_t, 8> Uses;
180 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
181 MachineOperand &MO = MBBI->getOperand(i);
182 if (!MO.isReg() || MO.isDef())
184 unsigned Reg = MO.getReg();
187 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
191 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
193 if (!Uses.count(*CS))
201 static bool isEAXLiveIn(MachineFunction &MF) {
202 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
203 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
204 unsigned Reg = II->first;
206 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
207 Reg == X86::AH || Reg == X86::AL)
214 /// Check whether or not the terminators of \p MBB needs to read EFLAGS.
215 static bool terminatorsNeedFlagsAsInput(const MachineBasicBlock &MBB) {
216 for (const MachineInstr &MI : MBB.terminators()) {
217 bool BreakNext = false;
218 for (const MachineOperand &MO : MI.operands()) {
221 unsigned Reg = MO.getReg();
222 if (Reg != X86::EFLAGS)
225 // This terminator needs an eflag that is not defined
226 // by a previous terminator.
237 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
238 /// stack pointer by a constant value.
239 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator &MBBI,
241 int64_t NumBytes, bool InEpilogue) const {
242 bool isSub = NumBytes < 0;
243 uint64_t Offset = isSub ? -NumBytes : NumBytes;
245 uint64_t Chunk = (1LL << 31) - 1;
246 DebugLoc DL = MBB.findDebugLoc(MBBI);
249 if (Offset > Chunk) {
250 // Rather than emit a long series of instructions for large offsets,
251 // load the offset into a register and do one sub/add
254 if (isSub && !isEAXLiveIn(*MBB.getParent()))
255 Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
257 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
260 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
261 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
264 ? getSUBrrOpcode(Is64Bit)
265 : getADDrrOpcode(Is64Bit);
266 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
269 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
275 uint64_t ThisVal = std::min(Offset, Chunk);
276 if (ThisVal == (Is64Bit ? 8 : 4)) {
277 // Use push / pop instead.
279 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
280 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
283 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
284 : (Is64Bit ? X86::POP64r : X86::POP32r);
285 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
286 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
288 MI->setFlag(MachineInstr::FrameSetup);
294 MachineInstrBuilder MI = BuildStackAdjustment(
295 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue);
297 MI.setMIFlag(MachineInstr::FrameSetup);
303 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
304 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
305 int64_t Offset, bool InEpilogue) const {
306 assert(Offset != 0 && "zero offset stack adjustment requested");
308 // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
312 UseLEA = STI.useLeaForSP();
314 // If we can use LEA for SP but we shouldn't, check that none
315 // of the terminators uses the eflags. Otherwise we will insert
316 // a ADD that will redefine the eflags and break the condition.
317 // Alternatively, we could move the ADD, but this may not be possible
318 // and is an optimization anyway.
319 UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
320 if (UseLEA && !STI.useLeaForSP())
321 UseLEA = terminatorsNeedFlagsAsInput(MBB);
322 // If that assert breaks, that means we do not do the right thing
323 // in canUseAsEpilogue.
324 assert((UseLEA || !terminatorsNeedFlagsAsInput(MBB)) &&
325 "We shouldn't have allowed this insertion point");
328 MachineInstrBuilder MI;
330 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
331 TII.get(getLEArOpcode(Uses64BitFramePtr)),
333 StackPtr, false, Offset);
335 bool IsSub = Offset < 0;
336 uint64_t AbsOffset = IsSub ? -Offset : Offset;
337 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
338 : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
339 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
342 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
347 int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
348 MachineBasicBlock::iterator &MBBI,
349 bool doMergeWithPrevious) const {
350 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
351 (!doMergeWithPrevious && MBBI == MBB.end()))
354 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
355 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
357 unsigned Opc = PI->getOpcode();
360 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
361 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
362 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
363 PI->getOperand(0).getReg() == StackPtr){
364 Offset += PI->getOperand(2).getImm();
366 if (!doMergeWithPrevious) MBBI = NI;
367 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
368 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
369 PI->getOperand(0).getReg() == StackPtr) {
370 Offset -= PI->getOperand(2).getImm();
372 if (!doMergeWithPrevious) MBBI = NI;
378 void X86FrameLowering::BuildCFI(MachineBasicBlock &MBB,
379 MachineBasicBlock::iterator MBBI, DebugLoc DL,
380 MCCFIInstruction CFIInst) const {
381 MachineFunction &MF = *MBB.getParent();
382 unsigned CFIIndex = MF.getMMI().addFrameInst(CFIInst);
383 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
384 .addCFIIndex(CFIIndex);
388 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
389 MachineBasicBlock::iterator MBBI,
391 MachineFunction &MF = *MBB.getParent();
392 MachineFrameInfo *MFI = MF.getFrameInfo();
393 MachineModuleInfo &MMI = MF.getMMI();
394 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
396 // Add callee saved registers to move list.
397 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
398 if (CSI.empty()) return;
400 // Calculate offsets.
401 for (std::vector<CalleeSavedInfo>::const_iterator
402 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
403 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
404 unsigned Reg = I->getReg();
406 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
407 BuildCFI(MBB, MBBI, DL,
408 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
412 /// usesTheStack - This function checks if any of the users of EFLAGS
413 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
414 /// to use the stack, and if we don't adjust the stack we clobber the first
416 /// See X86InstrInfo::copyPhysReg.
417 static bool usesTheStack(const MachineFunction &MF) {
418 const MachineRegisterInfo &MRI = MF.getRegInfo();
420 for (MachineRegisterInfo::reg_instr_iterator
421 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
429 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
430 MachineBasicBlock &MBB,
431 MachineBasicBlock::iterator MBBI,
433 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
437 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
439 CallOp = X86::CALLpcrel32;
443 if (STI.isTargetCygMing()) {
444 Symbol = "___chkstk_ms";
448 } else if (STI.isTargetCygMing())
453 MachineInstrBuilder CI;
455 // All current stack probes take AX and SP as input, clobber flags, and
456 // preserve all registers. x86_64 probes leave RSP unmodified.
457 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
458 // For the large code model, we have to call through a register. Use R11,
459 // as it is scratch in all supported calling conventions.
460 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
461 .addExternalSymbol(Symbol);
462 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
464 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
467 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
468 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
469 CI.addReg(AX, RegState::Implicit)
470 .addReg(SP, RegState::Implicit)
471 .addReg(AX, RegState::Define | RegState::Implicit)
472 .addReg(SP, RegState::Define | RegState::Implicit)
473 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
476 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
477 // themselves. It also does not clobber %rax so we can reuse it when
479 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
485 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
486 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
487 // and might require smaller successive adjustments.
488 const uint64_t Win64MaxSEHOffset = 128;
489 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
490 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
491 return SEHFrameOffset & -16;
494 // If we're forcing a stack realignment we can't rely on just the frame
495 // info, we need to know the ABI stack alignment as well in case we
496 // have a call out. Otherwise just make sure we have some alignment - we'll
497 // go with the minimum SlotSize.
498 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
499 const MachineFrameInfo *MFI = MF.getFrameInfo();
500 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
501 unsigned StackAlign = getStackAlignment();
502 if (ForceStackAlign) {
504 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
505 else if (MaxAlign < SlotSize)
511 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
512 MachineBasicBlock::iterator MBBI,
514 uint64_t MaxAlign) const {
515 uint64_t Val = -MaxAlign;
517 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
521 .setMIFlag(MachineInstr::FrameSetup);
523 // The EFLAGS implicit def is dead.
524 MI->getOperand(3).setIsDead();
527 /// emitPrologue - Push callee-saved registers onto the stack, which
528 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
529 /// space for local variables. Also emit labels used by the exception handler to
530 /// generate the exception handling frames.
533 Here's a gist of what gets emitted:
535 ; Establish frame pointer, if needed
538 .cfi_def_cfa_offset 16
539 .cfi_offset %rbp, -16
542 .cfi_def_cfa_register %rbp
544 ; Spill general-purpose registers
545 [for all callee-saved GPRs]
548 .cfi_def_cfa_offset (offset from RETADDR)
551 ; If the required stack alignment > default stack alignment
552 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
553 ; of unknown size in the stack frame.
554 [if stack needs re-alignment]
557 ; Allocate space for locals
558 [if target is Windows and allocated space > 4096 bytes]
559 ; Windows needs special care for allocations larger
562 call ___chkstk_ms/___chkstk
568 .seh_stackalloc (size of XMM spill slots)
569 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
574 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
575 ; they may get spilled on any platform, if the current function
576 ; calls @llvm.eh.unwind.init
578 [for all callee-saved XMM registers]
579 movaps %<xmm reg>, -MMM(%rbp)
580 [for all callee-saved XMM registers]
581 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
582 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
584 [for all callee-saved XMM registers]
585 movaps %<xmm reg>, KKK(%rsp)
586 [for all callee-saved XMM registers]
587 .seh_savexmm %<xmm reg>, KKK
591 [if needs base pointer]
593 [if needs to restore base pointer]
598 [for all callee-saved registers]
599 .cfi_offset %<reg>, (offset from %rbp)
601 .cfi_def_cfa_offset (offset from RETADDR)
602 [for all callee-saved registers]
603 .cfi_offset %<reg>, (offset from %rsp)
606 - .seh directives are emitted only for Windows 64 ABI
607 - .cfi directives are emitted for all other ABIs
608 - for 32-bit code, substitute %e?? registers for %r??
611 void X86FrameLowering::emitPrologue(MachineFunction &MF,
612 MachineBasicBlock &MBB) const {
613 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
614 "MF used frame lowering for wrong subtarget");
615 MachineBasicBlock::iterator MBBI = MBB.begin();
616 MachineFrameInfo *MFI = MF.getFrameInfo();
617 const Function *Fn = MF.getFunction();
618 MachineModuleInfo &MMI = MF.getMMI();
619 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
620 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
621 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
622 bool HasFP = hasFP(MF);
623 bool IsWin64CC = STI.isCallingConvWin64(Fn->getCallingConv());
624 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
625 bool NeedsWinCFI = IsWin64Prologue && Fn->needsUnwindTableEntry();
627 !IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
628 unsigned FramePtr = TRI->getFrameRegister(MF);
629 const unsigned MachineFramePtr =
630 STI.isTarget64BitILP32()
631 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
633 unsigned BasePtr = TRI->getBaseRegister();
636 // Add RETADDR move area to callee saved frame size.
637 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
638 if (TailCallReturnAddrDelta && IsWin64Prologue)
639 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
641 if (TailCallReturnAddrDelta < 0)
642 X86FI->setCalleeSavedFrameSize(
643 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
645 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
647 // The default stack probe size is 4096 if the function has no stackprobesize
649 unsigned StackProbeSize = 4096;
650 if (Fn->hasFnAttribute("stack-probe-size"))
651 Fn->getFnAttribute("stack-probe-size")
653 .getAsInteger(0, StackProbeSize);
655 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
656 // function, and use up to 128 bytes of stack space, don't have a frame
657 // pointer, calls, or dynamic alloca then we do not need to adjust the
658 // stack pointer (we fit in the Red Zone). We also check that we don't
659 // push and pop from the stack.
660 if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
661 !TRI->needsStackRealignment(MF) &&
662 !MFI->hasVarSizedObjects() && // No dynamic alloca.
663 !MFI->adjustsStack() && // No calls.
664 !IsWin64CC && // Win64 has no Red Zone
665 !usesTheStack(MF) && // Don't push and pop.
666 !MF.shouldSplitStack()) { // Regular stack
667 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
668 if (HasFP) MinSize += SlotSize;
669 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
670 MFI->setStackSize(StackSize);
673 // Insert stack pointer adjustment for later moving of return addr. Only
674 // applies to tail call optimized functions where the callee argument stack
675 // size is bigger than the callers.
676 if (TailCallReturnAddrDelta < 0) {
677 BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
678 /*InEpilogue=*/false)
679 .setMIFlag(MachineInstr::FrameSetup);
682 // Mapping for machine moves:
684 // DST: VirtualFP AND
685 // SRC: VirtualFP => DW_CFA_def_cfa_offset
686 // ELSE => DW_CFA_def_cfa
688 // SRC: VirtualFP AND
689 // DST: Register => DW_CFA_def_cfa_register
692 // OFFSET < 0 => DW_CFA_offset_extended_sf
693 // REG < 64 => DW_CFA_offset + Reg
694 // ELSE => DW_CFA_offset_extended
696 uint64_t NumBytes = 0;
697 int stackGrowth = -SlotSize;
699 if (MBB.isEHFuncletEntry()) {
700 assert(STI.isOSWindows() && "funclets only supported on Windows");
702 // Set up the FramePtr and BasePtr physical registers using the address
703 // passed as EBP or RDX by the MSVC EH runtime.
705 MBBI = restoreWin32EHFrameAndBasePtr(MBB, MBBI, DL);
707 // FIXME: Add SEH directives.
709 // Immediately spill RDX into the home slot. The runtime cares about this.
710 unsigned RDX = Uses64BitFramePtr ? X86::RDX : X86::EDX;
711 // MOV64mr %rdx, 16(%rsp)
712 unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
713 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)),
716 .setMIFlag(MachineInstr::FrameSetup);
718 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
719 .addReg(MachineFramePtr, RegState::Kill)
720 .setMIFlag(MachineInstr::FrameSetup);
721 // MOV64rr %rdx, %rbp
722 unsigned MOVrr = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
723 BuildMI(MBB, MBBI, DL, TII.get(MOVrr), FramePtr)
725 .setMIFlag(MachineInstr::FrameSetup);
726 assert(!TRI->hasBasePointer(MF) &&
727 "x64 funclets with base ptrs not yet implemented");
730 // For EH funclets, only allocate enough space for outgoing calls.
731 NumBytes = MFI->getMaxCallFrameSize();
733 // Calculate required stack adjustment.
734 uint64_t FrameSize = StackSize - SlotSize;
735 // If required, include space for extra hidden slot for stashing base pointer.
736 if (X86FI->getRestoreBasePointer())
737 FrameSize += SlotSize;
739 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
741 // Callee-saved registers are pushed on stack before the stack is realigned.
742 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
743 NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
745 // Get the offset of the stack slot for the EBP register, which is
746 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
747 // Update the frame offset adjustment.
748 MFI->setOffsetAdjustment(-NumBytes);
750 // Save EBP/RBP into the appropriate stack slot.
751 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
752 .addReg(MachineFramePtr, RegState::Kill)
753 .setMIFlag(MachineInstr::FrameSetup);
756 // Mark the place where EBP/RBP was saved.
757 // Define the current CFA rule to use the provided offset.
759 BuildCFI(MBB, MBBI, DL,
760 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
762 // Change the rule for the FramePtr to be an "offset" rule.
763 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
764 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
765 nullptr, DwarfFramePtr, 2 * stackGrowth));
769 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
771 .setMIFlag(MachineInstr::FrameSetup);
774 if (!IsWin64Prologue) {
775 // Update EBP with the new base value.
776 BuildMI(MBB, MBBI, DL,
777 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
780 .setMIFlag(MachineInstr::FrameSetup);
784 // Mark effective beginning of when frame pointer becomes valid.
785 // Define the current CFA to use the EBP/RBP register.
786 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
787 BuildCFI(MBB, MBBI, DL,
788 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
791 // Mark the FramePtr as live-in in every block.
792 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
793 I->addLiveIn(MachineFramePtr);
795 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
798 // Skip the callee-saved push instructions.
799 bool PushedRegs = false;
800 int StackOffset = 2 * stackGrowth;
802 while (MBBI != MBB.end() &&
803 MBBI->getFlag(MachineInstr::FrameSetup) &&
804 (MBBI->getOpcode() == X86::PUSH32r ||
805 MBBI->getOpcode() == X86::PUSH64r)) {
807 unsigned Reg = MBBI->getOperand(0).getReg();
810 if (!HasFP && NeedsDwarfCFI) {
811 // Mark callee-saved push instruction.
812 // Define the current CFA rule to use the provided offset.
814 BuildCFI(MBB, MBBI, DL,
815 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
816 StackOffset += stackGrowth;
820 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
821 MachineInstr::FrameSetup);
825 // Realign stack after we pushed callee-saved registers (so that we'll be
826 // able to calculate their offsets from the frame pointer).
827 // Don't do this for Win64, it needs to realign the stack after the prologue.
828 if (!IsWin64Prologue && TRI->needsStackRealignment(MF)) {
829 assert(HasFP && "There should be a frame pointer if stack is realigned.");
830 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
833 // If there is an SUB32ri of ESP immediately before this instruction, merge
834 // the two. This can be the case when tail call elimination is enabled and
835 // the callee has more arguments then the caller.
836 NumBytes -= mergeSPUpdates(MBB, MBBI, true);
838 // Adjust stack pointer: ESP -= numbytes.
840 // Windows and cygwin/mingw require a prologue helper routine when allocating
841 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
842 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
843 // stack and adjust the stack pointer in one go. The 64-bit version of
844 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
845 // responsible for adjusting the stack pointer. Touching the stack at 4K
846 // increments is necessary to ensure that the guard pages used by the OS
847 // virtual memory manager are allocated in correct sequence.
848 uint64_t AlignedNumBytes = NumBytes;
849 if (IsWin64Prologue && TRI->needsStackRealignment(MF))
850 AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
851 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
852 // Check whether EAX is livein for this function.
853 bool isEAXAlive = isEAXLiveIn(MF);
856 // Sanity check that EAX is not livein for this function.
857 // It should not be, so throw an assert.
858 assert(!Is64Bit && "EAX is livein in x64 case!");
861 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
862 .addReg(X86::EAX, RegState::Kill)
863 .setMIFlag(MachineInstr::FrameSetup);
867 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
868 // Function prologue is responsible for adjusting the stack pointer.
869 if (isUInt<32>(NumBytes)) {
870 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
872 .setMIFlag(MachineInstr::FrameSetup);
873 } else if (isInt<32>(NumBytes)) {
874 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
876 .setMIFlag(MachineInstr::FrameSetup);
878 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
880 .setMIFlag(MachineInstr::FrameSetup);
883 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
884 // We'll also use 4 already allocated bytes for EAX.
885 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
886 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
887 .setMIFlag(MachineInstr::FrameSetup);
890 // Save a pointer to the MI where we set AX.
891 MachineBasicBlock::iterator SetRAX = MBBI;
894 // Call __chkstk, __chkstk_ms, or __alloca.
895 emitStackProbeCall(MF, MBB, MBBI, DL);
897 // Apply the frame setup flag to all inserted instrs.
898 for (; SetRAX != MBBI; ++SetRAX)
899 SetRAX->setFlag(MachineInstr::FrameSetup);
903 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
905 StackPtr, false, NumBytes - 4);
906 MI->setFlag(MachineInstr::FrameSetup);
907 MBB.insert(MBBI, MI);
909 } else if (NumBytes) {
910 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false);
913 if (NeedsWinCFI && NumBytes)
914 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
916 .setMIFlag(MachineInstr::FrameSetup);
918 int SEHFrameOffset = 0;
919 if (IsWin64Prologue && HasFP) {
920 SEHFrameOffset = calculateSetFPREG(NumBytes);
922 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
923 StackPtr, false, SEHFrameOffset);
925 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr).addReg(StackPtr);
928 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
930 .addImm(SEHFrameOffset)
931 .setMIFlag(MachineInstr::FrameSetup);
934 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
935 const MachineInstr *FrameInstr = &*MBBI;
940 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
941 if (X86::FR64RegClass.contains(Reg)) {
942 unsigned IgnoredFrameReg;
943 int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
944 Offset += SEHFrameOffset;
946 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
949 .setMIFlag(MachineInstr::FrameSetup);
956 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
957 .setMIFlag(MachineInstr::FrameSetup);
959 // Realign stack after we spilled callee-saved registers (so that we'll be
960 // able to calculate their offsets from the frame pointer).
961 // Win64 requires aligning the stack after the prologue.
962 if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
963 assert(HasFP && "There should be a frame pointer if stack is realigned.");
964 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
967 // If we need a base pointer, set it up here. It's whatever the value
968 // of the stack pointer is at this point. Any variable size objects
969 // will be allocated after this, so we can still use the base pointer
970 // to reference locals.
971 if (TRI->hasBasePointer(MF)) {
972 // Update the base pointer with the current stack pointer.
973 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
974 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
976 .setMIFlag(MachineInstr::FrameSetup);
977 if (X86FI->getRestoreBasePointer()) {
978 // Stash value of base pointer. Saving RSP instead of EBP shortens
979 // dependence chain. Used by SjLj EH.
980 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
981 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
982 FramePtr, true, X86FI->getRestoreBasePointerOffset())
984 .setMIFlag(MachineInstr::FrameSetup);
987 if (X86FI->getHasSEHFramePtrSave()) {
988 // Stash the value of the frame pointer relative to the base pointer for
989 // Win32 EH. This supports Win32 EH, which does the inverse of the above:
990 // it recovers the frame pointer from the base pointer rather than the
992 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
995 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
996 assert(UsedReg == BasePtr);
997 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
999 .setMIFlag(MachineInstr::FrameSetup);
1003 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1004 // Mark end of stack pointer adjustment.
1005 if (!HasFP && NumBytes) {
1006 // Define the current CFA rule to use the provided offset.
1008 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
1009 nullptr, -StackSize + stackGrowth));
1012 // Emit DWARF info specifying the offsets of the callee-saved registers.
1014 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1018 bool X86FrameLowering::canUseLEAForSPInEpilogue(
1019 const MachineFunction &MF) const {
1020 // We can't use LEA instructions for adjusting the stack pointer if this is a
1021 // leaf function in the Win64 ABI. Only ADD instructions may be used to
1022 // deallocate the stack.
1023 // This means that we can use LEA for SP in two situations:
1024 // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1025 // 2. We *have* a frame pointer which means we are permitted to use LEA.
1026 return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1029 static bool isFuncletReturnInstr(MachineInstr *MI) {
1030 switch (MI->getOpcode()) {
1032 case X86::CATCHRET64:
1033 case X86::CLEANUPRET:
1034 case X86::CLEANUPRET64:
1039 llvm_unreachable("impossible");
1042 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
1043 MachineBasicBlock &MBB) const {
1044 const MachineFrameInfo *MFI = MF.getFrameInfo();
1045 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1046 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
1048 if (MBBI != MBB.end())
1049 DL = MBBI->getDebugLoc();
1050 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1051 const bool Is64BitILP32 = STI.isTarget64BitILP32();
1052 unsigned FramePtr = TRI->getFrameRegister(MF);
1053 unsigned MachineFramePtr =
1054 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
1057 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1059 IsWin64Prologue && MF.getFunction()->needsUnwindTableEntry();
1061 // Get the number of bytes to allocate from the FrameInfo.
1062 uint64_t StackSize = MFI->getStackSize();
1063 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1064 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1065 uint64_t NumBytes = 0;
1067 if (isFuncletReturnInstr(MBBI)) {
1068 NumBytes = MFI->getMaxCallFrameSize();
1071 assert(hasFP(MF) && "win64 EH funclets without FP not yet implemented");
1073 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1076 } else if (hasFP(MF)) {
1077 // Calculate required stack adjustment.
1078 uint64_t FrameSize = StackSize - SlotSize;
1079 NumBytes = FrameSize - CSSize;
1081 // Callee-saved registers were pushed on stack before the stack was
1083 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1084 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1087 BuildMI(MBB, MBBI, DL,
1088 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
1090 NumBytes = StackSize - CSSize;
1092 uint64_t SEHStackAllocAmt = NumBytes;
1094 // Skip the callee-saved pop instructions.
1095 while (MBBI != MBB.begin()) {
1096 MachineBasicBlock::iterator PI = std::prev(MBBI);
1097 unsigned Opc = PI->getOpcode();
1099 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1100 !PI->isTerminator())
1105 MachineBasicBlock::iterator FirstCSPop = MBBI;
1107 if (MBBI != MBB.end())
1108 DL = MBBI->getDebugLoc();
1110 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1111 // instruction, merge the two instructions.
1112 if (NumBytes || MFI->hasVarSizedObjects())
1113 NumBytes += mergeSPUpdates(MBB, MBBI, true);
1115 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1116 // slot before popping them off! Same applies for the case, when stack was
1118 if (TRI->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1119 if (TRI->needsStackRealignment(MF))
1121 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1122 uint64_t LEAAmount =
1123 IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1125 // There are only two legal forms of epilogue:
1126 // - add SEHAllocationSize, %rsp
1127 // - lea SEHAllocationSize(%FramePtr), %rsp
1129 // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1130 // However, we may use this sequence if we have a frame pointer because the
1131 // effects of the prologue can safely be undone.
1132 if (LEAAmount != 0) {
1133 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1134 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1135 FramePtr, false, LEAAmount);
1138 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1139 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1143 } else if (NumBytes) {
1144 // Adjust stack pointer back: ESP += numbytes.
1145 emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
1149 // Windows unwinder will not invoke function's exception handler if IP is
1150 // either in prologue or in epilogue. This behavior causes a problem when a
1151 // call immediately precedes an epilogue, because the return address points
1152 // into the epilogue. To cope with that, we insert an epilogue marker here,
1153 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1154 // final emitted code.
1156 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1158 // Add the return addr area delta back since we are not tail calling.
1159 int Offset = -1 * X86FI->getTCReturnAddrDelta();
1160 assert(Offset >= 0 && "TCDelta should never be positive");
1162 MBBI = MBB.getFirstTerminator();
1164 // Check for possible merge with preceding ADD instruction.
1165 Offset += mergeSPUpdates(MBB, MBBI, true);
1166 emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
1170 // NOTE: this only has a subset of the full frame index logic. In
1171 // particular, the FI < 0 and AfterFPPop logic is handled in
1172 // X86RegisterInfo::eliminateFrameIndex, but not here. Possibly
1173 // (probably?) it should be moved into here.
1174 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1175 unsigned &FrameReg) const {
1176 const MachineFrameInfo *MFI = MF.getFrameInfo();
1178 // We can't calculate offset from frame pointer if the stack is realigned,
1179 // so enforce usage of stack/base pointer. The base pointer is used when we
1180 // have dynamic allocas in addition to dynamic realignment.
1181 if (TRI->hasBasePointer(MF))
1182 FrameReg = TRI->getBaseRegister();
1183 else if (TRI->needsStackRealignment(MF))
1184 FrameReg = TRI->getStackRegister();
1186 FrameReg = TRI->getFrameRegister(MF);
1188 // Offset will hold the offset from the stack pointer at function entry to the
1190 // We need to factor in additional offsets applied during the prologue to the
1191 // frame, base, and stack pointer depending on which is used.
1192 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1193 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1194 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1195 uint64_t StackSize = MFI->getStackSize();
1196 bool HasFP = hasFP(MF);
1197 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1198 int64_t FPDelta = 0;
1200 if (IsWin64Prologue) {
1201 assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1203 // Calculate required stack adjustment.
1204 uint64_t FrameSize = StackSize - SlotSize;
1205 // If required, include space for extra hidden slot for stashing base pointer.
1206 if (X86FI->getRestoreBasePointer())
1207 FrameSize += SlotSize;
1208 uint64_t NumBytes = FrameSize - CSSize;
1210 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1211 if (FI && FI == X86FI->getFAIndex())
1212 return -SEHFrameOffset;
1214 // FPDelta is the offset from the "traditional" FP location of the old base
1215 // pointer followed by return address and the location required by the
1216 // restricted Win64 prologue.
1217 // Add FPDelta to all offsets below that go through the frame pointer.
1218 FPDelta = FrameSize - SEHFrameOffset;
1219 assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1220 "FPDelta isn't aligned per the Win64 ABI!");
1224 if (TRI->hasBasePointer(MF)) {
1225 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1227 // Skip the saved EBP.
1228 return Offset + SlotSize + FPDelta;
1230 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1231 return Offset + StackSize;
1233 } else if (TRI->needsStackRealignment(MF)) {
1235 // Skip the saved EBP.
1236 return Offset + SlotSize + FPDelta;
1238 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1239 return Offset + StackSize;
1241 // FIXME: Support tail calls
1244 return Offset + StackSize;
1246 // Skip the saved EBP.
1249 // Skip the RETADDR move area
1250 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1251 if (TailCallReturnAddrDelta < 0)
1252 Offset -= TailCallReturnAddrDelta;
1255 return Offset + FPDelta;
1258 // Simplified from getFrameIndexReference keeping only StackPointer cases
1259 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1261 unsigned &FrameReg) const {
1262 const MachineFrameInfo *MFI = MF.getFrameInfo();
1263 // Does not include any dynamic realign.
1264 const uint64_t StackSize = MFI->getStackSize();
1267 // Note: LLVM arranges the stack as:
1268 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1269 // > "Stack Slots" (<--SP)
1270 // We can always address StackSlots from RSP. We can usually (unless
1271 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1272 // address them from RBP. FixedObjects can be placed anywhere in the stack
1273 // frame depending on their specific requirements (i.e. we can actually
1274 // refer to arguments to the function which are stored in the *callers*
1275 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1276 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1278 assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1280 // We don't handle tail calls, and shouldn't be seeing them
1282 int TailCallReturnAddrDelta =
1283 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1284 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1288 // Fill in FrameReg output argument.
1289 FrameReg = TRI->getStackRegister();
1291 // This is how the math works out:
1293 // %rsp grows (i.e. gets lower) left to right. Each box below is
1294 // one word (eight bytes). Obj0 is the stack slot we're trying to
1297 // ----------------------------------
1298 // | BP | Obj0 | Obj1 | ... | ObjN |
1299 // ----------------------------------
1303 // A is the incoming stack pointer.
1304 // (B - A) is the local area offset (-8 for x86-64) [1]
1305 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1307 // |(E - B)| is the StackSize (absolute value, positive). For a
1308 // stack that grown down, this works out to be (B - E). [3]
1310 // E is also the value of %rsp after stack has been set up, and we
1311 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1312 // (C - E) == (C - A) - (B - A) + (B - E)
1313 // { Using [1], [2] and [3] above }
1314 // == getObjectOffset - LocalAreaOffset + StackSize
1317 // Get the Offset from the StackPointer
1318 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1320 return Offset + StackSize;
1323 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1324 MachineFunction &MF, const TargetRegisterInfo *TRI,
1325 std::vector<CalleeSavedInfo> &CSI) const {
1326 MachineFrameInfo *MFI = MF.getFrameInfo();
1327 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1329 unsigned CalleeSavedFrameSize = 0;
1330 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1333 // emitPrologue always spills frame register the first thing.
1334 SpillSlotOffset -= SlotSize;
1335 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1337 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1338 // the frame register, we can delete it from CSI list and not have to worry
1339 // about avoiding it later.
1340 unsigned FPReg = TRI->getFrameRegister(MF);
1341 for (unsigned i = 0; i < CSI.size(); ++i) {
1342 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1343 CSI.erase(CSI.begin() + i);
1349 // Assign slots for GPRs. It increases frame size.
1350 for (unsigned i = CSI.size(); i != 0; --i) {
1351 unsigned Reg = CSI[i - 1].getReg();
1353 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1356 SpillSlotOffset -= SlotSize;
1357 CalleeSavedFrameSize += SlotSize;
1359 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1360 CSI[i - 1].setFrameIdx(SlotIndex);
1363 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1365 // Assign slots for XMMs.
1366 for (unsigned i = CSI.size(); i != 0; --i) {
1367 unsigned Reg = CSI[i - 1].getReg();
1368 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1371 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1373 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1375 SpillSlotOffset -= RC->getSize();
1377 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1378 CSI[i - 1].setFrameIdx(SlotIndex);
1379 MFI->ensureMaxAlignment(RC->getAlignment());
1385 bool X86FrameLowering::spillCalleeSavedRegisters(
1386 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1387 const std::vector<CalleeSavedInfo> &CSI,
1388 const TargetRegisterInfo *TRI) const {
1389 DebugLoc DL = MBB.findDebugLoc(MI);
1391 // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
1392 // for us, and there are no XMM CSRs on Win32.
1393 if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
1396 // Push GPRs. It increases frame size.
1397 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1398 for (unsigned i = CSI.size(); i != 0; --i) {
1399 unsigned Reg = CSI[i - 1].getReg();
1401 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1403 // Add the callee-saved register as live-in. It's killed at the spill.
1406 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1407 .setMIFlag(MachineInstr::FrameSetup);
1410 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1411 // It can be done by spilling XMMs to stack frame.
1412 for (unsigned i = CSI.size(); i != 0; --i) {
1413 unsigned Reg = CSI[i-1].getReg();
1414 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1416 // Add the callee-saved register as live-in. It's killed at the spill.
1418 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1420 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1423 MI->setFlag(MachineInstr::FrameSetup);
1430 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1431 MachineBasicBlock::iterator MI,
1432 const std::vector<CalleeSavedInfo> &CSI,
1433 const TargetRegisterInfo *TRI) const {
1437 // Don't restore CSRs in 32-bit EH funclets. Matches
1438 // spillCalleeSavedRegisters.
1439 if (isFuncletReturnInstr(MI) && STI.is32Bit() && STI.isOSWindows())
1442 DebugLoc DL = MBB.findDebugLoc(MI);
1444 // Reload XMMs from stack frame.
1445 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1446 unsigned Reg = CSI[i].getReg();
1447 if (X86::GR64RegClass.contains(Reg) ||
1448 X86::GR32RegClass.contains(Reg))
1451 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1452 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1456 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1457 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1458 unsigned Reg = CSI[i].getReg();
1459 if (!X86::GR64RegClass.contains(Reg) &&
1460 !X86::GR32RegClass.contains(Reg))
1463 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1468 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
1469 BitVector &SavedRegs,
1470 RegScavenger *RS) const {
1471 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1473 MachineFrameInfo *MFI = MF.getFrameInfo();
1475 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1476 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1478 if (TailCallReturnAddrDelta < 0) {
1479 // create RETURNADDR area
1488 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1489 TailCallReturnAddrDelta - SlotSize, true);
1492 // Spill the BasePtr if it's used.
1493 if (TRI->hasBasePointer(MF)) {
1494 SavedRegs.set(TRI->getBaseRegister());
1496 // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
1497 if (MF.getMMI().hasEHFunclets()) {
1498 int FI = MFI->CreateSpillStackObject(SlotSize, SlotSize);
1499 X86FI->setHasSEHFramePtrSave(true);
1500 X86FI->setSEHFramePtrSaveIndex(FI);
1506 HasNestArgument(const MachineFunction *MF) {
1507 const Function *F = MF->getFunction();
1508 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1510 if (I->hasNestAttr())
1516 /// GetScratchRegister - Get a temp register for performing work in the
1517 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1518 /// and the properties of the function either one or two registers will be
1519 /// needed. Set primary to true for the first register, false for the second.
1521 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1522 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1525 if (CallingConvention == CallingConv::HiPE) {
1527 return Primary ? X86::R14 : X86::R13;
1529 return Primary ? X86::EBX : X86::EDI;
1534 return Primary ? X86::R11 : X86::R12;
1536 return Primary ? X86::R11D : X86::R12D;
1539 bool IsNested = HasNestArgument(&MF);
1541 if (CallingConvention == CallingConv::X86_FastCall ||
1542 CallingConvention == CallingConv::Fast) {
1544 report_fatal_error("Segmented stacks does not support fastcall with "
1545 "nested function.");
1546 return Primary ? X86::EAX : X86::ECX;
1549 return Primary ? X86::EDX : X86::EAX;
1550 return Primary ? X86::ECX : X86::EAX;
1553 // The stack limit in the TCB is set to this many bytes above the actual stack
1555 static const uint64_t kSplitStackAvailable = 256;
1557 void X86FrameLowering::adjustForSegmentedStacks(
1558 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1559 MachineFrameInfo *MFI = MF.getFrameInfo();
1561 unsigned TlsReg, TlsOffset;
1564 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1565 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1566 "Scratch register is live-in");
1568 if (MF.getFunction()->isVarArg())
1569 report_fatal_error("Segmented stacks do not support vararg functions.");
1570 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1571 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1572 !STI.isTargetDragonFly())
1573 report_fatal_error("Segmented stacks not supported on this platform.");
1575 // Eventually StackSize will be calculated by a link-time pass; which will
1576 // also decide whether checking code needs to be injected into this particular
1578 StackSize = MFI->getStackSize();
1580 // Do not generate a prologue for functions with a stack of size zero
1584 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1585 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1586 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1587 bool IsNested = false;
1589 // We need to know if the function has a nest argument only in 64 bit mode.
1591 IsNested = HasNestArgument(&MF);
1593 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1594 // allocMBB needs to be last (terminating) instruction.
1596 for (const auto &LI : PrologueMBB.liveins()) {
1597 allocMBB->addLiveIn(LI);
1598 checkMBB->addLiveIn(LI);
1602 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1604 MF.push_front(allocMBB);
1605 MF.push_front(checkMBB);
1607 // When the frame size is less than 256 we just compare the stack
1608 // boundary directly to the value of the stack pointer, per gcc.
1609 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1611 // Read the limit off the current stacklet off the stack_guard location.
1613 if (STI.isTargetLinux()) {
1615 TlsOffset = IsLP64 ? 0x70 : 0x40;
1616 } else if (STI.isTargetDarwin()) {
1618 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1619 } else if (STI.isTargetWin64()) {
1621 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1622 } else if (STI.isTargetFreeBSD()) {
1625 } else if (STI.isTargetDragonFly()) {
1627 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1629 report_fatal_error("Segmented stacks not supported on this platform.");
1632 if (CompareStackPointer)
1633 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1635 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1636 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1638 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1639 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1641 if (STI.isTargetLinux()) {
1644 } else if (STI.isTargetDarwin()) {
1646 TlsOffset = 0x48 + 90*4;
1647 } else if (STI.isTargetWin32()) {
1649 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1650 } else if (STI.isTargetDragonFly()) {
1652 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1653 } else if (STI.isTargetFreeBSD()) {
1654 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1656 report_fatal_error("Segmented stacks not supported on this platform.");
1659 if (CompareStackPointer)
1660 ScratchReg = X86::ESP;
1662 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1663 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1665 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1666 STI.isTargetDragonFly()) {
1667 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1668 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1669 } else if (STI.isTargetDarwin()) {
1671 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1672 unsigned ScratchReg2;
1674 if (CompareStackPointer) {
1675 // The primary scratch register is available for holding the TLS offset.
1676 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1677 SaveScratch2 = false;
1679 // Need to use a second register to hold the TLS offset
1680 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1682 // Unfortunately, with fastcc the second scratch register may hold an
1684 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1687 // If Scratch2 is live-in then it needs to be saved.
1688 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1689 "Scratch register is live-in and not saved");
1692 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1693 .addReg(ScratchReg2, RegState::Kill);
1695 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1697 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1699 .addReg(ScratchReg2).addImm(1).addReg(0)
1704 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1708 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1709 // It jumps to normal execution of the function body.
1710 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
1712 // On 32 bit we first push the arguments size and then the frame size. On 64
1713 // bit, we pass the stack frame size in r10 and the argument size in r11.
1715 // Functions with nested arguments use R10, so it needs to be saved across
1716 // the call to _morestack
1718 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1719 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1720 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1721 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1722 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1725 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1727 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1729 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1730 .addImm(X86FI->getArgumentStackSize());
1732 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1733 .addImm(X86FI->getArgumentStackSize());
1734 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1738 // __morestack is in libgcc
1739 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1740 // Under the large code model, we cannot assume that __morestack lives
1741 // within 2^31 bytes of the call site, so we cannot use pc-relative
1742 // addressing. We cannot perform the call via a temporary register,
1743 // as the rax register may be used to store the static chain, and all
1744 // other suitable registers may be either callee-save or used for
1745 // parameter passing. We cannot use the stack at this point either
1746 // because __morestack manipulates the stack directly.
1748 // To avoid these issues, perform an indirect call via a read-only memory
1749 // location containing the address.
1751 // This solution is not perfect, as it assumes that the .rodata section
1752 // is laid out within 2^31 bytes of each function body, but this seems
1753 // to be sufficient for JIT.
1754 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1758 .addExternalSymbol("__morestack_addr")
1760 MF.getMMI().setUsesMorestackAddr(true);
1763 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1764 .addExternalSymbol("__morestack");
1766 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1767 .addExternalSymbol("__morestack");
1771 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1773 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1775 allocMBB->addSuccessor(&PrologueMBB);
1777 checkMBB->addSuccessor(allocMBB);
1778 checkMBB->addSuccessor(&PrologueMBB);
1785 /// Erlang programs may need a special prologue to handle the stack size they
1786 /// might need at runtime. That is because Erlang/OTP does not implement a C
1787 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1788 /// (for more information see Eric Stenman's Ph.D. thesis:
1789 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1792 /// temp0 = sp - MaxStack
1793 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1797 /// call inc_stack # doubles the stack space
1798 /// temp0 = sp - MaxStack
1799 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1800 void X86FrameLowering::adjustForHiPEPrologue(
1801 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1802 MachineFrameInfo *MFI = MF.getFrameInfo();
1804 // HiPE-specific values
1805 const unsigned HipeLeafWords = 24;
1806 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1807 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1808 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1809 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1810 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1812 assert(STI.isTargetLinux() &&
1813 "HiPE prologue is only supported on Linux operating systems.");
1815 // Compute the largest caller's frame that is needed to fit the callees'
1816 // frames. This 'MaxStack' is computed from:
1818 // a) the fixed frame size, which is the space needed for all spilled temps,
1819 // b) outgoing on-stack parameter areas, and
1820 // c) the minimum stack space this function needs to make available for the
1821 // functions it calls (a tunable ABI property).
1822 if (MFI->hasCalls()) {
1823 unsigned MoreStackForCalls = 0;
1825 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1826 MBBI != MBBE; ++MBBI)
1827 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1832 // Get callee operand.
1833 const MachineOperand &MO = MI->getOperand(0);
1835 // Only take account of global function calls (no closures etc.).
1839 const Function *F = dyn_cast<Function>(MO.getGlobal());
1843 // Do not update 'MaxStack' for primitive and built-in functions
1844 // (encoded with names either starting with "erlang."/"bif_" or not
1845 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1846 // "_", such as the BIF "suspend_0") as they are executed on another
1848 if (F->getName().find("erlang.") != StringRef::npos ||
1849 F->getName().find("bif_") != StringRef::npos ||
1850 F->getName().find_first_of("._") == StringRef::npos)
1853 unsigned CalleeStkArity =
1854 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1855 if (HipeLeafWords - 1 > CalleeStkArity)
1856 MoreStackForCalls = std::max(MoreStackForCalls,
1857 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1859 MaxStack += MoreStackForCalls;
1862 // If the stack frame needed is larger than the guaranteed then runtime checks
1863 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1864 if (MaxStack > Guaranteed) {
1865 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1866 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1868 for (const auto &LI : PrologueMBB.liveins()) {
1869 stackCheckMBB->addLiveIn(LI);
1870 incStackMBB->addLiveIn(LI);
1873 MF.push_front(incStackMBB);
1874 MF.push_front(stackCheckMBB);
1876 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1877 unsigned LEAop, CMPop, CALLop;
1881 LEAop = X86::LEA64r;
1882 CMPop = X86::CMP64rm;
1883 CALLop = X86::CALL64pcrel32;
1884 SPLimitOffset = 0x90;
1888 LEAop = X86::LEA32r;
1889 CMPop = X86::CMP32rm;
1890 CALLop = X86::CALLpcrel32;
1891 SPLimitOffset = 0x4c;
1894 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1895 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1896 "HiPE prologue scratch register is live-in");
1898 // Create new MBB for StackCheck:
1899 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1900 SPReg, false, -MaxStack);
1901 // SPLimitOffset is in a fixed heap location (pointed by BP).
1902 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1903 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1904 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
1906 // Create new MBB for IncStack:
1907 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1908 addExternalSymbol("inc_stack_0");
1909 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1910 SPReg, false, -MaxStack);
1911 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1912 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1913 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1915 stackCheckMBB->addSuccessor(&PrologueMBB, 99);
1916 stackCheckMBB->addSuccessor(incStackMBB, 1);
1917 incStackMBB->addSuccessor(&PrologueMBB, 99);
1918 incStackMBB->addSuccessor(incStackMBB, 1);
1925 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
1926 MachineBasicBlock::iterator MBBI, DebugLoc DL, int Offset) const {
1928 if (Offset % SlotSize)
1931 int NumPops = Offset / SlotSize;
1932 // This is only worth it if we have at most 2 pops.
1933 if (NumPops != 1 && NumPops != 2)
1936 // Handle only the trivial case where the adjustment directly follows
1937 // a call. This is the most common one, anyway.
1938 if (MBBI == MBB.begin())
1940 MachineBasicBlock::iterator Prev = std::prev(MBBI);
1941 if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
1945 unsigned FoundRegs = 0;
1947 auto RegMask = Prev->getOperand(1);
1949 // Try to find up to NumPops free registers.
1950 for (auto Candidate : X86::GR32_NOREX_NOSPRegClass) {
1952 // Poor man's liveness:
1953 // Since we're immediately after a call, any register that is clobbered
1954 // by the call and not defined by it can be considered dead.
1955 if (!RegMask.clobbersPhysReg(Candidate))
1959 for (const MachineOperand &MO : Prev->implicit_operands()) {
1960 if (MO.isReg() && MO.isDef() && MO.getReg() == Candidate) {
1969 Regs[FoundRegs++] = Candidate;
1970 if (FoundRegs == (unsigned)NumPops)
1977 // If we found only one free register, but need two, reuse the same one twice.
1978 while (FoundRegs < (unsigned)NumPops)
1979 Regs[FoundRegs++] = Regs[0];
1981 for (int i = 0; i < NumPops; ++i)
1982 BuildMI(MBB, MBBI, DL,
1983 TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
1988 void X86FrameLowering::
1989 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1990 MachineBasicBlock::iterator I) const {
1991 bool reserveCallFrame = hasReservedCallFrame(MF);
1992 unsigned Opcode = I->getOpcode();
1993 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1994 DebugLoc DL = I->getDebugLoc();
1995 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
1996 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
1999 if (!reserveCallFrame) {
2000 // If the stack pointer can be changed after prologue, turn the
2001 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2002 // adjcallstackdown instruction into 'add ESP, <amt>'
2006 // We need to keep the stack aligned properly. To do this, we round the
2007 // amount of space needed for the outgoing arguments up to the next
2008 // alignment boundary.
2009 unsigned StackAlign = getStackAlignment();
2010 Amount = RoundUpToAlignment(Amount, StackAlign);
2012 // Factor out the amount that gets handled inside the sequence
2013 // (Pushes of argument for frame setup, callee pops for frame destroy)
2014 Amount -= InternalAmt;
2017 // Add Amount to SP to destroy a frame, and subtract to setup.
2018 int Offset = isDestroy ? Amount : -Amount;
2020 if (!(MF.getFunction()->optForMinSize() &&
2021 adjustStackWithPops(MBB, I, DL, Offset)))
2022 BuildStackAdjustment(MBB, I, DL, Offset, /*InEpilogue=*/false);
2028 if (isDestroy && InternalAmt) {
2029 // If we are performing frame pointer elimination and if the callee pops
2030 // something off the stack pointer, add it back. We do this until we have
2031 // more advanced stack pointer tracking ability.
2032 // We are not tracking the stack pointer adjustment by the callee, so make
2033 // sure we restore the stack pointer immediately after the call, there may
2034 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2035 MachineBasicBlock::iterator B = MBB.begin();
2036 while (I != B && !std::prev(I)->isCall())
2038 BuildStackAdjustment(MBB, I, DL, -InternalAmt, /*InEpilogue=*/false);
2042 bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
2043 assert(MBB.getParent() && "Block is not attached to a function!");
2045 if (canUseLEAForSPInEpilogue(*MBB.getParent()))
2048 // If we cannot use LEA to adjust SP, we may need to use ADD, which
2049 // clobbers the EFLAGS. Check that none of the terminators reads the
2050 // EFLAGS, and if one uses it, conservatively assume this is not
2051 // safe to insert the epilogue here.
2052 return !terminatorsNeedFlagsAsInput(MBB);
2055 MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHFrameAndBasePtr(
2056 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
2057 DebugLoc DL) const {
2058 assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
2059 assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
2060 assert(STI.is32Bit() && !Uses64BitFramePtr &&
2061 "restoring EBP/ESI on non-32-bit target");
2063 MachineFunction &MF = *MBB.getParent();
2064 unsigned FramePtr = TRI->getFrameRegister(MF);
2065 unsigned BasePtr = TRI->getBaseRegister();
2066 MachineModuleInfo &MMI = MF.getMMI();
2067 const Function *Fn = MF.getFunction();
2068 WinEHFuncInfo &FuncInfo = MMI.getWinEHFuncInfo(Fn);
2069 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2070 MachineFrameInfo *MFI = MF.getFrameInfo();
2072 // FIXME: Don't set FrameSetup flag in catchret case.
2074 int FI = FuncInfo.EHRegNodeFrameIndex;
2076 int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg);
2077 int EHRegSize = MFI->getObjectSize(FI);
2078 int EndOffset = -EHRegOffset - EHRegSize;
2079 assert(EndOffset >= 0 &&
2080 "end of registration object above normal EBP position!");
2081 if (UsedReg == FramePtr) {
2082 // ADD $offset, %ebp
2083 assert(UsedReg == FramePtr);
2084 unsigned ADDri = getADDriOpcode(false, EndOffset);
2085 BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2088 .setMIFlag(MachineInstr::FrameSetup)
2092 assert(UsedReg == BasePtr);
2093 // LEA offset(%ebp), %esi
2094 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2095 FramePtr, false, EndOffset)
2096 .setMIFlag(MachineInstr::FrameSetup);
2097 // MOV32mr SavedEBPOffset(%esi), %ebp
2098 assert(X86FI->getHasSEHFramePtrSave());
2100 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
2101 assert(UsedReg == BasePtr);
2102 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), UsedReg, true,
2105 .setMIFlag(MachineInstr::FrameSetup);