1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
35 // FIXME: completely move here.
36 extern cl::opt<bool> ForceStackAlign;
38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
39 return !MF.getFrameInfo()->hasVarSizedObjects();
42 /// hasFP - Return true if the specified function should have a dedicated frame
43 /// pointer register. This is true if the function has variable sized allocas
44 /// or if frame pointer elimination is disabled.
45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 const MachineModuleInfo &MMI = MF.getMMI();
48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
50 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
51 RegInfo->needsStackRealignment(MF) ||
52 MFI->hasVarSizedObjects() ||
53 MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
55 MMI.callsUnwindInit() || MMI.callsEHReturn());
58 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
62 return X86::SUB64ri32;
70 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
74 return X86::ADD64ri32;
82 static unsigned getLEArOpcode(unsigned IsLP64) {
83 return IsLP64 ? X86::LEA64r : X86::LEA32r;
86 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
87 /// when it reaches the "return" instruction. We can then pop a stack object
88 /// to this register without worry about clobbering it.
89 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator &MBBI,
91 const TargetRegisterInfo &TRI,
93 const MachineFunction *MF = MBB.getParent();
94 const Function *F = MF->getFunction();
95 if (!F || MF->getMMI().callsEHReturn())
98 static const uint16_t CallerSavedRegs32Bit[] = {
99 X86::EAX, X86::EDX, X86::ECX, 0
102 static const uint16_t CallerSavedRegs64Bit[] = {
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
107 unsigned Opc = MBBI->getOpcode();
114 case X86::TCRETURNdi:
115 case X86::TCRETURNri:
116 case X86::TCRETURNmi:
117 case X86::TCRETURNdi64:
118 case X86::TCRETURNri64:
119 case X86::TCRETURNmi64:
121 case X86::EH_RETURN64: {
122 SmallSet<uint16_t, 8> Uses;
123 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
124 MachineOperand &MO = MBBI->getOperand(i);
125 if (!MO.isReg() || MO.isDef())
127 unsigned Reg = MO.getReg();
130 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
134 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
136 if (!Uses.count(*CS))
145 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
146 /// stack pointer by a constant value.
148 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
149 unsigned StackPtr, int64_t NumBytes,
150 bool Is64Bit, bool IsLP64, bool UseLEA,
151 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
152 bool isSub = NumBytes < 0;
153 uint64_t Offset = isSub ? -NumBytes : NumBytes;
156 Opc = getLEArOpcode(IsLP64);
159 ? getSUBriOpcode(IsLP64, Offset)
160 : getADDriOpcode(IsLP64, Offset);
162 uint64_t Chunk = (1LL << 31) - 1;
163 DebugLoc DL = MBB.findDebugLoc(MBBI);
166 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
167 if (ThisVal == (Is64Bit ? 8 : 4)) {
168 // Use push / pop instead.
170 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
171 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
174 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
175 : (Is64Bit ? X86::POP64r : X86::POP32r);
176 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
177 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
179 MI->setFlag(MachineInstr::FrameSetup);
185 MachineInstr *MI = NULL;
188 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 StackPtr, false, isSub ? -ThisVal : ThisVal);
191 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
194 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
198 MI->setFlag(MachineInstr::FrameSetup);
204 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
206 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
207 unsigned StackPtr, uint64_t *NumBytes = NULL) {
208 if (MBBI == MBB.begin()) return;
210 MachineBasicBlock::iterator PI = std::prev(MBBI);
211 unsigned Opc = PI->getOpcode();
212 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
213 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
214 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
215 PI->getOperand(0).getReg() == StackPtr) {
217 *NumBytes += PI->getOperand(2).getImm();
219 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
220 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
221 PI->getOperand(0).getReg() == StackPtr) {
223 *NumBytes -= PI->getOperand(2).getImm();
228 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
230 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
231 MachineBasicBlock::iterator &MBBI,
232 unsigned StackPtr, uint64_t *NumBytes = NULL) {
233 // FIXME: THIS ISN'T RUN!!!
236 if (MBBI == MBB.end()) return;
238 MachineBasicBlock::iterator NI = std::next(MBBI);
239 if (NI == MBB.end()) return;
241 unsigned Opc = NI->getOpcode();
242 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
243 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
244 NI->getOperand(0).getReg() == StackPtr) {
246 *NumBytes -= NI->getOperand(2).getImm();
249 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
250 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
251 NI->getOperand(0).getReg() == StackPtr) {
253 *NumBytes += NI->getOperand(2).getImm();
259 /// mergeSPUpdates - Checks the instruction before/after the passed
260 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the
261 /// stack adjustment is returned as a positive value for ADD/LEA and a negative for
263 static int mergeSPUpdates(MachineBasicBlock &MBB,
264 MachineBasicBlock::iterator &MBBI,
266 bool doMergeWithPrevious) {
267 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
268 (!doMergeWithPrevious && MBBI == MBB.end()))
271 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
272 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : std::next(MBBI);
273 unsigned Opc = PI->getOpcode();
276 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
277 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
278 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
279 PI->getOperand(0).getReg() == StackPtr){
280 Offset += PI->getOperand(2).getImm();
282 if (!doMergeWithPrevious) MBBI = NI;
283 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
284 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
285 PI->getOperand(0).getReg() == StackPtr) {
286 Offset -= PI->getOperand(2).getImm();
288 if (!doMergeWithPrevious) MBBI = NI;
294 static bool isEAXLiveIn(MachineFunction &MF) {
295 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
296 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
297 unsigned Reg = II->first;
299 if (Reg == X86::EAX || Reg == X86::AX ||
300 Reg == X86::AH || Reg == X86::AL)
307 void X86FrameLowering::emitCalleeSavedFrameMoves(
308 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
309 unsigned FramePtr) const {
310 MachineFunction &MF = *MBB.getParent();
311 MachineFrameInfo *MFI = MF.getFrameInfo();
312 MachineModuleInfo &MMI = MF.getMMI();
313 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
314 const X86InstrInfo &TII = *TM.getInstrInfo();
316 // Add callee saved registers to move list.
317 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
318 if (CSI.empty()) return;
320 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
321 bool HasFP = hasFP(MF);
323 // Calculate amount of bytes used for return address storing.
324 int stackGrowth = -RegInfo->getSlotSize();
326 // FIXME: This is dirty hack. The code itself is pretty mess right now.
327 // It should be rewritten from scratch and generalized sometimes.
329 // Determine maximum offset (minimum due to stack growth).
330 int64_t MaxOffset = 0;
331 for (std::vector<CalleeSavedInfo>::const_iterator
332 I = CSI.begin(), E = CSI.end(); I != E; ++I)
333 MaxOffset = std::min(MaxOffset,
334 MFI->getObjectOffset(I->getFrameIdx()));
336 // Calculate offsets.
337 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
338 for (std::vector<CalleeSavedInfo>::const_iterator
339 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
340 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
341 unsigned Reg = I->getReg();
342 Offset = MaxOffset - Offset + saveAreaOffset;
344 // Don't output a new machine move if we're re-saving the frame
345 // pointer. This happens when the PrologEpilogInserter has inserted an extra
346 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
347 // generates one when frame pointers are used. If we generate a "machine
348 // move" for this extra "PUSH", the linker will lose track of the fact that
349 // the frame pointer should have the value of the first "PUSH" when it's
352 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
353 // another bug. I.e., one where we generate a prolog like this:
361 // The immediate re-push of EBP is unnecessary. At the least, it's an
362 // optimization bug. EBP can be used as a scratch register in certain
363 // cases, but probably not when we have a frame pointer.
364 if (HasFP && FramePtr == Reg)
367 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
369 MMI.addFrameInst(MCCFIInstruction::createOffset(0, DwarfReg, Offset));
370 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
374 /// usesTheStack - This function checks if any of the users of EFLAGS
375 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
376 /// to use the stack, and if we don't adjust the stack we clobber the first
378 /// See X86InstrInfo::copyPhysReg.
379 static bool usesTheStack(const MachineFunction &MF) {
380 const MachineRegisterInfo &MRI = MF.getRegInfo();
382 for (MachineRegisterInfo::reg_instr_iterator
383 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
391 /// emitPrologue - Push callee-saved registers onto the stack, which
392 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
393 /// space for local variables. Also emit labels used by the exception handler to
394 /// generate the exception handling frames.
395 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
396 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
397 MachineBasicBlock::iterator MBBI = MBB.begin();
398 MachineFrameInfo *MFI = MF.getFrameInfo();
399 const Function *Fn = MF.getFunction();
400 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
401 const X86InstrInfo &TII = *TM.getInstrInfo();
402 MachineModuleInfo &MMI = MF.getMMI();
403 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
404 bool needsFrameMoves = MMI.hasDebugInfo() ||
405 Fn->needsUnwindTableEntry();
406 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
407 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
408 bool HasFP = hasFP(MF);
409 bool Is64Bit = STI.is64Bit();
410 bool IsLP64 = STI.isTarget64BitLP64();
411 bool IsWin64 = STI.isTargetWin64();
412 bool UseLEA = STI.useLeaForSP();
413 unsigned StackAlign = getStackAlignment();
414 unsigned SlotSize = RegInfo->getSlotSize();
415 unsigned FramePtr = RegInfo->getFrameRegister(MF);
416 unsigned StackPtr = RegInfo->getStackRegister();
417 unsigned BasePtr = RegInfo->getBaseRegister();
420 // If we're forcing a stack realignment we can't rely on just the frame
421 // info, we need to know the ABI stack alignment as well in case we
422 // have a call out. Otherwise just make sure we have some alignment - we'll
423 // go with the minimum SlotSize.
424 if (ForceStackAlign) {
426 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
427 else if (MaxAlign < SlotSize)
431 // Add RETADDR move area to callee saved frame size.
432 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
433 if (TailCallReturnAddrDelta < 0)
434 X86FI->setCalleeSavedFrameSize(
435 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
437 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
438 // function, and use up to 128 bytes of stack space, don't have a frame
439 // pointer, calls, or dynamic alloca then we do not need to adjust the
440 // stack pointer (we fit in the Red Zone). We also check that we don't
441 // push and pop from the stack.
442 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
443 Attribute::NoRedZone) &&
444 !RegInfo->needsStackRealignment(MF) &&
445 !MFI->hasVarSizedObjects() && // No dynamic alloca.
446 !MFI->adjustsStack() && // No calls.
447 !IsWin64 && // Win64 has no Red Zone
448 !usesTheStack(MF) && // Don't push and pop.
449 !MF.shouldSplitStack()) { // Regular stack
450 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
451 if (HasFP) MinSize += SlotSize;
452 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
453 MFI->setStackSize(StackSize);
456 // Insert stack pointer adjustment for later moving of return addr. Only
457 // applies to tail call optimized functions where the callee argument stack
458 // size is bigger than the callers.
459 if (TailCallReturnAddrDelta < 0) {
461 BuildMI(MBB, MBBI, DL,
462 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
465 .addImm(-TailCallReturnAddrDelta)
466 .setMIFlag(MachineInstr::FrameSetup);
467 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
470 // Mapping for machine moves:
472 // DST: VirtualFP AND
473 // SRC: VirtualFP => DW_CFA_def_cfa_offset
474 // ELSE => DW_CFA_def_cfa
476 // SRC: VirtualFP AND
477 // DST: Register => DW_CFA_def_cfa_register
480 // OFFSET < 0 => DW_CFA_offset_extended_sf
481 // REG < 64 => DW_CFA_offset + Reg
482 // ELSE => DW_CFA_offset_extended
484 uint64_t NumBytes = 0;
485 int stackGrowth = -SlotSize;
488 // Calculate required stack adjustment.
489 uint64_t FrameSize = StackSize - SlotSize;
490 if (RegInfo->needsStackRealignment(MF)) {
491 // Callee-saved registers are pushed on stack before the stack
493 FrameSize -= X86FI->getCalleeSavedFrameSize();
494 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
496 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
499 // Get the offset of the stack slot for the EBP register, which is
500 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
501 // Update the frame offset adjustment.
502 MFI->setOffsetAdjustment(-NumBytes);
504 // Save EBP/RBP into the appropriate stack slot.
505 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
506 .addReg(FramePtr, RegState::Kill)
507 .setMIFlag(MachineInstr::FrameSetup);
509 if (needsFrameMoves) {
510 // Mark the place where EBP/RBP was saved.
511 // Define the current CFA rule to use the provided offset.
513 unsigned CFIIndex = MMI.addFrameInst(
514 MCCFIInstruction::createDefCfaOffset(0, 2 * stackGrowth));
515 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
516 .addCFIIndex(CFIIndex);
518 // Change the rule for the FramePtr to be an "offset" rule.
519 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
520 CFIIndex = MMI.addFrameInst(
521 MCCFIInstruction::createOffset(0, DwarfFramePtr, 2 * stackGrowth));
522 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
523 .addCFIIndex(CFIIndex);
526 // Update EBP with the new base value.
527 BuildMI(MBB, MBBI, DL,
528 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
530 .setMIFlag(MachineInstr::FrameSetup);
532 if (needsFrameMoves) {
533 // Mark effective beginning of when frame pointer becomes valid.
534 // Define the current CFA to use the EBP/RBP register.
535 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
536 unsigned CFIIndex = MMI.addFrameInst(
537 MCCFIInstruction::createDefCfaRegister(0, DwarfFramePtr));
538 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
539 .addCFIIndex(CFIIndex);
542 // Mark the FramePtr as live-in in every block except the entry.
543 for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
545 I->addLiveIn(FramePtr);
547 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
550 // Skip the callee-saved push instructions.
551 bool PushedRegs = false;
552 int StackOffset = 2 * stackGrowth;
554 while (MBBI != MBB.end() &&
555 (MBBI->getOpcode() == X86::PUSH32r ||
556 MBBI->getOpcode() == X86::PUSH64r)) {
558 MBBI->setFlag(MachineInstr::FrameSetup);
561 if (!HasFP && needsFrameMoves) {
562 // Mark callee-saved push instruction.
563 // Define the current CFA rule to use the provided offset.
565 unsigned CFIIndex = MMI.addFrameInst(
566 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
567 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
568 .addCFIIndex(CFIIndex);
569 StackOffset += stackGrowth;
573 // Realign stack after we pushed callee-saved registers (so that we'll be
574 // able to calculate their offsets from the frame pointer).
576 // NOTE: We push the registers before realigning the stack, so
577 // vector callee-saved (xmm) registers may be saved w/o proper
578 // alignment in this way. However, currently these regs are saved in
579 // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so
580 // this shouldn't be a problem.
581 if (RegInfo->needsStackRealignment(MF)) {
582 assert(HasFP && "There should be a frame pointer if stack is realigned.");
584 BuildMI(MBB, MBBI, DL,
585 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
588 .setMIFlag(MachineInstr::FrameSetup);
590 // The EFLAGS implicit def is dead.
591 MI->getOperand(3).setIsDead();
594 // If there is an SUB32ri of ESP immediately before this instruction, merge
595 // the two. This can be the case when tail call elimination is enabled and
596 // the callee has more arguments then the caller.
597 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
599 // If there is an ADD32ri or SUB32ri of ESP immediately after this
600 // instruction, merge the two instructions.
601 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
603 // Adjust stack pointer: ESP -= numbytes.
605 // Windows and cygwin/mingw require a prologue helper routine when allocating
606 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
607 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
608 // stack and adjust the stack pointer in one go. The 64-bit version of
609 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
610 // responsible for adjusting the stack pointer. Touching the stack at 4K
611 // increments is necessary to ensure that the guard pages used by the OS
612 // virtual memory manager are allocated in correct sequence.
613 if (NumBytes >= 4096 && STI.isOSWindows() && !STI.isTargetMacho()) {
614 const char *StackProbeSymbol;
617 if (STI.isTargetCygMing()) {
618 StackProbeSymbol = "___chkstk_ms";
620 StackProbeSymbol = "__chkstk";
622 } else if (STI.isTargetCygMing())
623 StackProbeSymbol = "_alloca";
625 StackProbeSymbol = "_chkstk";
627 // Check whether EAX is livein for this function.
628 bool isEAXAlive = isEAXLiveIn(MF);
631 // Sanity check that EAX is not livein for this function.
632 // It should not be, so throw an assert.
633 assert(!Is64Bit && "EAX is livein in x64 case!");
636 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
637 .addReg(X86::EAX, RegState::Kill)
638 .setMIFlag(MachineInstr::FrameSetup);
642 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
643 // Function prologue is responsible for adjusting the stack pointer.
644 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
646 .setMIFlag(MachineInstr::FrameSetup);
648 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
649 // We'll also use 4 already allocated bytes for EAX.
650 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
651 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
652 .setMIFlag(MachineInstr::FrameSetup);
655 BuildMI(MBB, MBBI, DL,
656 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
657 .addExternalSymbol(StackProbeSymbol)
658 .addReg(StackPtr, RegState::Define | RegState::Implicit)
659 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
660 .setMIFlag(MachineInstr::FrameSetup);
663 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
664 // themself. It also does not clobber %rax so we can reuse it when
666 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), StackPtr)
669 .setMIFlag(MachineInstr::FrameSetup);
673 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
675 StackPtr, false, NumBytes - 4);
676 MI->setFlag(MachineInstr::FrameSetup);
677 MBB.insert(MBBI, MI);
680 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
681 UseLEA, TII, *RegInfo);
683 // If we need a base pointer, set it up here. It's whatever the value
684 // of the stack pointer is at this point. Any variable size objects
685 // will be allocated after this, so we can still use the base pointer
686 // to reference locals.
687 if (RegInfo->hasBasePointer(MF)) {
688 // Update the frame pointer with the current stack pointer.
689 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
690 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
692 .setMIFlag(MachineInstr::FrameSetup);
695 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
696 // Mark end of stack pointer adjustment.
697 if (!HasFP && NumBytes) {
698 // Define the current CFA rule to use the provided offset.
700 unsigned CFIIndex = MMI.addFrameInst(
701 MCCFIInstruction::createDefCfaOffset(0, -StackSize + stackGrowth));
703 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
704 .addCFIIndex(CFIIndex);
707 // Emit DWARF info specifying the offsets of the callee-saved registers.
709 emitCalleeSavedFrameMoves(MBB, MBBI, DL, HasFP ? FramePtr : StackPtr);
713 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
714 MachineBasicBlock &MBB) const {
715 const MachineFrameInfo *MFI = MF.getFrameInfo();
716 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
717 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
718 const X86InstrInfo &TII = *TM.getInstrInfo();
719 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
720 assert(MBBI != MBB.end() && "Returning block has no instructions");
721 unsigned RetOpcode = MBBI->getOpcode();
722 DebugLoc DL = MBBI->getDebugLoc();
723 bool Is64Bit = STI.is64Bit();
724 bool IsLP64 = STI.isTarget64BitLP64();
725 bool UseLEA = STI.useLeaForSP();
726 unsigned StackAlign = getStackAlignment();
727 unsigned SlotSize = RegInfo->getSlotSize();
728 unsigned FramePtr = RegInfo->getFrameRegister(MF);
729 unsigned StackPtr = RegInfo->getStackRegister();
733 llvm_unreachable("Can only insert epilog into returning blocks");
738 case X86::TCRETURNdi:
739 case X86::TCRETURNri:
740 case X86::TCRETURNmi:
741 case X86::TCRETURNdi64:
742 case X86::TCRETURNri64:
743 case X86::TCRETURNmi64:
745 case X86::EH_RETURN64:
746 break; // These are ok
749 // Get the number of bytes to allocate from the FrameInfo.
750 uint64_t StackSize = MFI->getStackSize();
751 uint64_t MaxAlign = MFI->getMaxAlignment();
752 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
753 uint64_t NumBytes = 0;
755 // If we're forcing a stack realignment we can't rely on just the frame
756 // info, we need to know the ABI stack alignment as well in case we
757 // have a call out. Otherwise just make sure we have some alignment - we'll
758 // go with the minimum.
759 if (ForceStackAlign) {
761 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
763 MaxAlign = MaxAlign ? MaxAlign : 4;
767 // Calculate required stack adjustment.
768 uint64_t FrameSize = StackSize - SlotSize;
769 if (RegInfo->needsStackRealignment(MF)) {
770 // Callee-saved registers were pushed on stack before the stack
773 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
775 NumBytes = FrameSize - CSSize;
779 BuildMI(MBB, MBBI, DL,
780 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
782 NumBytes = StackSize - CSSize;
785 // Skip the callee-saved pop instructions.
786 while (MBBI != MBB.begin()) {
787 MachineBasicBlock::iterator PI = std::prev(MBBI);
788 unsigned Opc = PI->getOpcode();
790 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
796 MachineBasicBlock::iterator FirstCSPop = MBBI;
798 DL = MBBI->getDebugLoc();
800 // If there is an ADD32ri or SUB32ri of ESP immediately before this
801 // instruction, merge the two instructions.
802 if (NumBytes || MFI->hasVarSizedObjects())
803 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
805 // If dynamic alloca is used, then reset esp to point to the last callee-saved
806 // slot before popping them off! Same applies for the case, when stack was
808 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
809 if (RegInfo->needsStackRealignment(MF))
812 unsigned Opc = getLEArOpcode(IsLP64);
813 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
814 FramePtr, false, -CSSize);
816 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
817 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
820 } else if (NumBytes) {
821 // Adjust stack pointer back: ESP += numbytes.
822 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
826 // We're returning from function via eh_return.
827 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
828 MBBI = MBB.getLastNonDebugInstr();
829 MachineOperand &DestAddr = MBBI->getOperand(0);
830 assert(DestAddr.isReg() && "Offset should be in register!");
831 BuildMI(MBB, MBBI, DL,
832 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
833 StackPtr).addReg(DestAddr.getReg());
834 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
835 RetOpcode == X86::TCRETURNmi ||
836 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
837 RetOpcode == X86::TCRETURNmi64) {
838 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
839 // Tail call return: adjust the stack pointer and jump to callee.
840 MBBI = MBB.getLastNonDebugInstr();
841 MachineOperand &JumpTarget = MBBI->getOperand(0);
842 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
843 assert(StackAdjust.isImm() && "Expecting immediate value.");
845 // Adjust stack pointer.
846 int StackAdj = StackAdjust.getImm();
847 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
849 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
851 // Incoporate the retaddr area.
852 Offset = StackAdj-MaxTCDelta;
853 assert(Offset >= 0 && "Offset should never be negative");
856 // Check for possible merge with preceding ADD instruction.
857 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
858 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
859 UseLEA, TII, *RegInfo);
862 // Jump to label or value in register.
863 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
864 MachineInstrBuilder MIB =
865 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
866 ? X86::TAILJMPd : X86::TAILJMPd64));
867 if (JumpTarget.isGlobal())
868 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
869 JumpTarget.getTargetFlags());
871 assert(JumpTarget.isSymbol());
872 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
873 JumpTarget.getTargetFlags());
875 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
876 MachineInstrBuilder MIB =
877 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
878 ? X86::TAILJMPm : X86::TAILJMPm64));
879 for (unsigned i = 0; i != 5; ++i)
880 MIB.addOperand(MBBI->getOperand(i));
881 } else if (RetOpcode == X86::TCRETURNri64) {
882 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
883 addReg(JumpTarget.getReg(), RegState::Kill);
885 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
886 addReg(JumpTarget.getReg(), RegState::Kill);
889 MachineInstr *NewMI = std::prev(MBBI);
890 NewMI->copyImplicitOps(MF, MBBI);
892 // Delete the pseudo instruction TCRETURN.
894 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
895 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
896 (X86FI->getTCReturnAddrDelta() < 0)) {
897 // Add the return addr area delta back since we are not tail calling.
898 int delta = -1*X86FI->getTCReturnAddrDelta();
899 MBBI = MBB.getLastNonDebugInstr();
901 // Check for possible merge with preceding ADD instruction.
902 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
903 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
908 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
909 const X86RegisterInfo *RegInfo =
910 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
911 const MachineFrameInfo *MFI = MF.getFrameInfo();
912 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
913 uint64_t StackSize = MFI->getStackSize();
915 if (RegInfo->hasBasePointer(MF)) {
916 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
918 // Skip the saved EBP.
919 return Offset + RegInfo->getSlotSize();
921 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
922 return Offset + StackSize;
924 } else if (RegInfo->needsStackRealignment(MF)) {
926 // Skip the saved EBP.
927 return Offset + RegInfo->getSlotSize();
929 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
930 return Offset + StackSize;
932 // FIXME: Support tail calls
935 return Offset + StackSize;
937 // Skip the saved EBP.
938 Offset += RegInfo->getSlotSize();
940 // Skip the RETADDR move area
941 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
942 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
943 if (TailCallReturnAddrDelta < 0)
944 Offset -= TailCallReturnAddrDelta;
950 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
951 unsigned &FrameReg) const {
952 const X86RegisterInfo *RegInfo =
953 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
954 // We can't calculate offset from frame pointer if the stack is realigned,
955 // so enforce usage of stack/base pointer. The base pointer is used when we
956 // have dynamic allocas in addition to dynamic realignment.
957 if (RegInfo->hasBasePointer(MF))
958 FrameReg = RegInfo->getBaseRegister();
959 else if (RegInfo->needsStackRealignment(MF))
960 FrameReg = RegInfo->getStackRegister();
962 FrameReg = RegInfo->getFrameRegister(MF);
963 return getFrameIndexOffset(MF, FI);
966 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
967 MachineBasicBlock::iterator MI,
968 const std::vector<CalleeSavedInfo> &CSI,
969 const TargetRegisterInfo *TRI) const {
973 DebugLoc DL = MBB.findDebugLoc(MI);
975 MachineFunction &MF = *MBB.getParent();
977 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
978 unsigned FPReg = TRI->getFrameRegister(MF);
979 unsigned CalleeFrameSize = 0;
981 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
982 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
984 // Push GPRs. It increases frame size.
985 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
986 for (unsigned i = CSI.size(); i != 0; --i) {
987 unsigned Reg = CSI[i-1].getReg();
988 if (!X86::GR64RegClass.contains(Reg) &&
989 !X86::GR32RegClass.contains(Reg))
991 // Add the callee-saved register as live-in. It's killed at the spill.
994 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
996 CalleeFrameSize += SlotSize;
997 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
998 .setMIFlag(MachineInstr::FrameSetup);
1001 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
1003 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1004 // It can be done by spilling XMMs to stack frame.
1005 // Note that only Win64 ABI might spill XMMs.
1006 for (unsigned i = CSI.size(); i != 0; --i) {
1007 unsigned Reg = CSI[i-1].getReg();
1008 if (X86::GR64RegClass.contains(Reg) ||
1009 X86::GR32RegClass.contains(Reg))
1011 // Add the callee-saved register as live-in. It's killed at the spill.
1013 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1014 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1021 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1022 MachineBasicBlock::iterator MI,
1023 const std::vector<CalleeSavedInfo> &CSI,
1024 const TargetRegisterInfo *TRI) const {
1028 DebugLoc DL = MBB.findDebugLoc(MI);
1030 MachineFunction &MF = *MBB.getParent();
1031 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1033 // Reload XMMs from stack frame.
1034 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1035 unsigned Reg = CSI[i].getReg();
1036 if (X86::GR64RegClass.contains(Reg) ||
1037 X86::GR32RegClass.contains(Reg))
1039 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1040 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1045 unsigned FPReg = TRI->getFrameRegister(MF);
1046 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1047 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1048 unsigned Reg = CSI[i].getReg();
1049 if (!X86::GR64RegClass.contains(Reg) &&
1050 !X86::GR32RegClass.contains(Reg))
1053 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
1055 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1061 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1062 RegScavenger *RS) const {
1063 MachineFrameInfo *MFI = MF.getFrameInfo();
1064 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
1065 unsigned SlotSize = RegInfo->getSlotSize();
1067 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1068 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1070 if (TailCallReturnAddrDelta < 0) {
1071 // create RETURNADDR area
1080 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1081 TailCallReturnAddrDelta - SlotSize, true);
1085 assert((TailCallReturnAddrDelta <= 0) &&
1086 "The Delta should always be zero or negative");
1087 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
1089 // Create a frame entry for the EBP register that must be saved.
1090 int FrameIdx = MFI->CreateFixedObject(SlotSize,
1092 TFI.getOffsetOfLocalArea() +
1093 TailCallReturnAddrDelta,
1095 assert(FrameIdx == MFI->getObjectIndexBegin() &&
1096 "Slot for EBP register must be last in order to be found!");
1100 // Spill the BasePtr if it's used.
1101 if (RegInfo->hasBasePointer(MF))
1102 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1106 HasNestArgument(const MachineFunction *MF) {
1107 const Function *F = MF->getFunction();
1108 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1110 if (I->hasNestAttr())
1116 /// GetScratchRegister - Get a temp register for performing work in the
1117 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1118 /// and the properties of the function either one or two registers will be
1119 /// needed. Set primary to true for the first register, false for the second.
1121 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1122 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1125 if (CallingConvention == CallingConv::HiPE) {
1127 return Primary ? X86::R14 : X86::R13;
1129 return Primary ? X86::EBX : X86::EDI;
1133 return Primary ? X86::R11 : X86::R12;
1135 bool IsNested = HasNestArgument(&MF);
1137 if (CallingConvention == CallingConv::X86_FastCall ||
1138 CallingConvention == CallingConv::Fast) {
1140 report_fatal_error("Segmented stacks does not support fastcall with "
1141 "nested function.");
1142 return Primary ? X86::EAX : X86::ECX;
1145 return Primary ? X86::EDX : X86::EAX;
1146 return Primary ? X86::ECX : X86::EAX;
1149 // The stack limit in the TCB is set to this many bytes above the actual stack
1151 static const uint64_t kSplitStackAvailable = 256;
1154 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1155 MachineBasicBlock &prologueMBB = MF.front();
1156 MachineFrameInfo *MFI = MF.getFrameInfo();
1157 const X86InstrInfo &TII = *TM.getInstrInfo();
1159 bool Is64Bit = STI.is64Bit();
1160 unsigned TlsReg, TlsOffset;
1163 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1164 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1165 "Scratch register is live-in");
1167 if (MF.getFunction()->isVarArg())
1168 report_fatal_error("Segmented stacks do not support vararg functions.");
1169 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1170 !STI.isTargetWin32() && !STI.isTargetWin64() && !STI.isTargetFreeBSD())
1171 report_fatal_error("Segmented stacks not supported on this platform.");
1173 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1174 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1175 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1176 bool IsNested = false;
1178 // We need to know if the function has a nest argument only in 64 bit mode.
1180 IsNested = HasNestArgument(&MF);
1182 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1183 // allocMBB needs to be last (terminating) instruction.
1185 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1186 e = prologueMBB.livein_end(); i != e; i++) {
1187 allocMBB->addLiveIn(*i);
1188 checkMBB->addLiveIn(*i);
1192 allocMBB->addLiveIn(X86::R10);
1194 MF.push_front(allocMBB);
1195 MF.push_front(checkMBB);
1197 // Eventually StackSize will be calculated by a link-time pass; which will
1198 // also decide whether checking code needs to be injected into this particular
1200 StackSize = MFI->getStackSize();
1202 // When the frame size is less than 256 we just compare the stack
1203 // boundary directly to the value of the stack pointer, per gcc.
1204 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1206 // Read the limit off the current stacklet off the stack_guard location.
1208 if (STI.isTargetLinux()) {
1211 } else if (STI.isTargetDarwin()) {
1213 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1214 } else if (STI.isTargetWin64()) {
1216 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1217 } else if (STI.isTargetFreeBSD()) {
1221 report_fatal_error("Segmented stacks not supported on this platform.");
1224 if (CompareStackPointer)
1225 ScratchReg = X86::RSP;
1227 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1228 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1230 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1231 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1233 if (STI.isTargetLinux()) {
1236 } else if (STI.isTargetDarwin()) {
1238 TlsOffset = 0x48 + 90*4;
1239 } else if (STI.isTargetWin32()) {
1241 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1242 } else if (STI.isTargetFreeBSD()) {
1243 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1245 report_fatal_error("Segmented stacks not supported on this platform.");
1248 if (CompareStackPointer)
1249 ScratchReg = X86::ESP;
1251 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1252 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1254 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64()) {
1255 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1256 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1257 } else if (STI.isTargetDarwin()) {
1259 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
1260 unsigned ScratchReg2;
1262 if (CompareStackPointer) {
1263 // The primary scratch register is available for holding the TLS offset
1264 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1265 SaveScratch2 = false;
1267 // Need to use a second register to hold the TLS offset
1268 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1270 // Unfortunately, with fastcc the second scratch register may hold an arg
1271 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1274 // If Scratch2 is live-in then it needs to be saved
1275 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1276 "Scratch register is live-in and not saved");
1279 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1280 .addReg(ScratchReg2, RegState::Kill);
1282 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1284 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1286 .addReg(ScratchReg2).addImm(1).addReg(0)
1291 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1295 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1296 // It jumps to normal execution of the function body.
1297 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1299 // On 32 bit we first push the arguments size and then the frame size. On 64
1300 // bit, we pass the stack frame size in r10 and the argument size in r11.
1302 // Functions with nested arguments use R10, so it needs to be saved across
1303 // the call to _morestack
1306 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1308 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1310 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1311 .addImm(X86FI->getArgumentStackSize());
1312 MF.getRegInfo().setPhysRegUsed(X86::R10);
1313 MF.getRegInfo().setPhysRegUsed(X86::R11);
1315 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1316 .addImm(X86FI->getArgumentStackSize());
1317 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1321 // __morestack is in libgcc
1323 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1324 .addExternalSymbol("__morestack");
1326 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1327 .addExternalSymbol("__morestack");
1330 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1332 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1334 allocMBB->addSuccessor(&prologueMBB);
1336 checkMBB->addSuccessor(allocMBB);
1337 checkMBB->addSuccessor(&prologueMBB);
1344 /// Erlang programs may need a special prologue to handle the stack size they
1345 /// might need at runtime. That is because Erlang/OTP does not implement a C
1346 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1347 /// (for more information see Eric Stenman's Ph.D. thesis:
1348 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1351 /// temp0 = sp - MaxStack
1352 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1356 /// call inc_stack # doubles the stack space
1357 /// temp0 = sp - MaxStack
1358 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1359 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1360 const X86InstrInfo &TII = *TM.getInstrInfo();
1361 MachineFrameInfo *MFI = MF.getFrameInfo();
1362 const unsigned SlotSize = TM.getRegisterInfo()->getSlotSize();
1363 const bool Is64Bit = STI.is64Bit();
1365 // HiPE-specific values
1366 const unsigned HipeLeafWords = 24;
1367 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1368 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1369 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1370 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1371 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1373 assert(STI.isTargetLinux() &&
1374 "HiPE prologue is only supported on Linux operating systems.");
1376 // Compute the largest caller's frame that is needed to fit the callees'
1377 // frames. This 'MaxStack' is computed from:
1379 // a) the fixed frame size, which is the space needed for all spilled temps,
1380 // b) outgoing on-stack parameter areas, and
1381 // c) the minimum stack space this function needs to make available for the
1382 // functions it calls (a tunable ABI property).
1383 if (MFI->hasCalls()) {
1384 unsigned MoreStackForCalls = 0;
1386 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1387 MBBI != MBBE; ++MBBI)
1388 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1393 // Get callee operand.
1394 const MachineOperand &MO = MI->getOperand(0);
1396 // Only take account of global function calls (no closures etc.).
1400 const Function *F = dyn_cast<Function>(MO.getGlobal());
1404 // Do not update 'MaxStack' for primitive and built-in functions
1405 // (encoded with names either starting with "erlang."/"bif_" or not
1406 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1407 // "_", such as the BIF "suspend_0") as they are executed on another
1409 if (F->getName().find("erlang.") != StringRef::npos ||
1410 F->getName().find("bif_") != StringRef::npos ||
1411 F->getName().find_first_of("._") == StringRef::npos)
1414 unsigned CalleeStkArity =
1415 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1416 if (HipeLeafWords - 1 > CalleeStkArity)
1417 MoreStackForCalls = std::max(MoreStackForCalls,
1418 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1420 MaxStack += MoreStackForCalls;
1423 // If the stack frame needed is larger than the guaranteed then runtime checks
1424 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1425 if (MaxStack > Guaranteed) {
1426 MachineBasicBlock &prologueMBB = MF.front();
1427 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1428 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1430 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1431 E = prologueMBB.livein_end(); I != E; I++) {
1432 stackCheckMBB->addLiveIn(*I);
1433 incStackMBB->addLiveIn(*I);
1436 MF.push_front(incStackMBB);
1437 MF.push_front(stackCheckMBB);
1439 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1440 unsigned LEAop, CMPop, CALLop;
1444 LEAop = X86::LEA64r;
1445 CMPop = X86::CMP64rm;
1446 CALLop = X86::CALL64pcrel32;
1447 SPLimitOffset = 0x90;
1451 LEAop = X86::LEA32r;
1452 CMPop = X86::CMP32rm;
1453 CALLop = X86::CALLpcrel32;
1454 SPLimitOffset = 0x4c;
1457 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1458 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1459 "HiPE prologue scratch register is live-in");
1461 // Create new MBB for StackCheck:
1462 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1463 SPReg, false, -MaxStack);
1464 // SPLimitOffset is in a fixed heap location (pointed by BP).
1465 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1466 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1467 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1469 // Create new MBB for IncStack:
1470 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1471 addExternalSymbol("inc_stack_0");
1472 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1473 SPReg, false, -MaxStack);
1474 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1475 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1476 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1478 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1479 stackCheckMBB->addSuccessor(incStackMBB, 1);
1480 incStackMBB->addSuccessor(&prologueMBB, 99);
1481 incStackMBB->addSuccessor(incStackMBB, 1);
1488 void X86FrameLowering::
1489 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1490 MachineBasicBlock::iterator I) const {
1491 const X86InstrInfo &TII = *TM.getInstrInfo();
1492 const X86RegisterInfo &RegInfo = *TM.getRegisterInfo();
1493 unsigned StackPtr = RegInfo.getStackRegister();
1494 bool reseveCallFrame = hasReservedCallFrame(MF);
1495 int Opcode = I->getOpcode();
1496 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1497 bool IsLP64 = STI.isTarget64BitLP64();
1498 DebugLoc DL = I->getDebugLoc();
1499 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
1500 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1503 if (!reseveCallFrame) {
1504 // If the stack pointer can be changed after prologue, turn the
1505 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1506 // adjcallstackdown instruction into 'add ESP, <amt>'
1507 // TODO: consider using push / pop instead of sub + store / add
1511 // We need to keep the stack aligned properly. To do this, we round the
1512 // amount of space needed for the outgoing arguments up to the next
1513 // alignment boundary.
1514 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1515 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1517 MachineInstr *New = 0;
1518 if (Opcode == TII.getCallFrameSetupOpcode()) {
1519 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1524 assert(Opcode == TII.getCallFrameDestroyOpcode());
1526 // Factor out the amount the callee already popped.
1527 Amount -= CalleeAmt;
1530 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1531 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1532 .addReg(StackPtr).addImm(Amount);
1537 // The EFLAGS implicit def is dead.
1538 New->getOperand(3).setIsDead();
1540 // Replace the pseudo instruction with a new instruction.
1547 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1548 // If we are performing frame pointer elimination and if the callee pops
1549 // something off the stack pointer, add it back. We do this until we have
1550 // more advanced stack pointer tracking ability.
1551 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1552 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1553 .addReg(StackPtr).addImm(CalleeAmt);
1555 // The EFLAGS implicit def is dead.
1556 New->getOperand(3).setIsDead();
1558 // We are not tracking the stack pointer adjustment by the callee, so make
1559 // sure we restore the stack pointer immediately after the call, there may
1560 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1561 MachineBasicBlock::iterator B = MBB.begin();
1562 while (I != B && !std::prev(I)->isCall())