1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/WinEHFuncInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
37 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
38 unsigned StackAlignOverride)
39 : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
40 STI.is64Bit() ? -8 : -4),
41 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
42 // Cache a bunch of frame-related predicates for this subtarget.
43 SlotSize = TRI->getSlotSize();
44 Is64Bit = STI.is64Bit();
45 IsLP64 = STI.isTarget64BitLP64();
46 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
47 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
48 StackPtr = TRI->getStackRegister();
51 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
52 return !MF.getFrameInfo()->hasVarSizedObjects() &&
53 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
56 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
57 /// call frame pseudos can be simplified. Having a FP, as in the default
58 /// implementation, is not sufficient here since we can't always use it.
59 /// Use a more nuanced condition.
61 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
62 return hasReservedCallFrame(MF) ||
63 (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
64 TRI->hasBasePointer(MF);
67 // needsFrameIndexResolution - Do we need to perform FI resolution for
68 // this function. Normally, this is required only when the function
69 // has any stack objects. However, FI resolution actually has another job,
70 // not apparent from the title - it resolves callframesetup/destroy
71 // that were not simplified earlier.
72 // So, this is required for x86 functions that have push sequences even
73 // when there are no stack objects.
75 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
76 return MF.getFrameInfo()->hasStackObjects() ||
77 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
80 /// hasFP - Return true if the specified function should have a dedicated frame
81 /// pointer register. This is true if the function has variable sized allocas
82 /// or if frame pointer elimination is disabled.
83 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
84 const MachineFrameInfo *MFI = MF.getFrameInfo();
85 const MachineModuleInfo &MMI = MF.getMMI();
87 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
88 TRI->needsStackRealignment(MF) ||
89 MFI->hasVarSizedObjects() ||
90 MFI->isFrameAddressTaken() || MFI->hasOpaqueSPAdjustment() ||
91 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
92 MMI.callsUnwindInit() || MMI.hasEHFunclets() || MMI.callsEHReturn() ||
93 MFI->hasStackMap() || MFI->hasPatchPoint());
96 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
100 return X86::SUB64ri32;
103 return X86::SUB32ri8;
108 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
111 return X86::ADD64ri8;
112 return X86::ADD64ri32;
115 return X86::ADD32ri8;
120 static unsigned getSUBrrOpcode(unsigned isLP64) {
121 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
124 static unsigned getADDrrOpcode(unsigned isLP64) {
125 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
128 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
131 return X86::AND64ri8;
132 return X86::AND64ri32;
135 return X86::AND32ri8;
139 static unsigned getLEArOpcode(unsigned IsLP64) {
140 return IsLP64 ? X86::LEA64r : X86::LEA32r;
143 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
144 /// when it reaches the "return" instruction. We can then pop a stack object
145 /// to this register without worry about clobbering it.
146 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator &MBBI,
148 const TargetRegisterInfo *TRI,
150 const MachineFunction *MF = MBB.getParent();
151 const Function *F = MF->getFunction();
152 if (!F || MF->getMMI().callsEHReturn())
155 static const uint16_t CallerSavedRegs32Bit[] = {
156 X86::EAX, X86::EDX, X86::ECX, 0
159 static const uint16_t CallerSavedRegs64Bit[] = {
160 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
161 X86::R8, X86::R9, X86::R10, X86::R11, 0
164 unsigned Opc = MBBI->getOpcode();
171 case X86::TCRETURNdi:
172 case X86::TCRETURNri:
173 case X86::TCRETURNmi:
174 case X86::TCRETURNdi64:
175 case X86::TCRETURNri64:
176 case X86::TCRETURNmi64:
178 case X86::EH_RETURN64: {
179 SmallSet<uint16_t, 8> Uses;
180 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
181 MachineOperand &MO = MBBI->getOperand(i);
182 if (!MO.isReg() || MO.isDef())
184 unsigned Reg = MO.getReg();
187 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
191 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
193 if (!Uses.count(*CS))
201 static bool isEAXLiveIn(MachineFunction &MF) {
202 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
203 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
204 unsigned Reg = II->first;
206 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
207 Reg == X86::AH || Reg == X86::AL)
214 /// Check whether or not the terminators of \p MBB needs to read EFLAGS.
215 static bool terminatorsNeedFlagsAsInput(const MachineBasicBlock &MBB) {
216 for (const MachineInstr &MI : MBB.terminators()) {
217 bool BreakNext = false;
218 for (const MachineOperand &MO : MI.operands()) {
221 unsigned Reg = MO.getReg();
222 if (Reg != X86::EFLAGS)
225 // This terminator needs an eflag that is not defined
226 // by a previous terminator.
237 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
238 /// stack pointer by a constant value.
239 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator &MBBI,
241 int64_t NumBytes, bool InEpilogue) const {
242 bool isSub = NumBytes < 0;
243 uint64_t Offset = isSub ? -NumBytes : NumBytes;
245 uint64_t Chunk = (1LL << 31) - 1;
246 DebugLoc DL = MBB.findDebugLoc(MBBI);
249 if (Offset > Chunk) {
250 // Rather than emit a long series of instructions for large offsets,
251 // load the offset into a register and do one sub/add
254 if (isSub && !isEAXLiveIn(*MBB.getParent()))
255 Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
257 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
260 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
261 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
264 ? getSUBrrOpcode(Is64Bit)
265 : getADDrrOpcode(Is64Bit);
266 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
269 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
275 uint64_t ThisVal = std::min(Offset, Chunk);
276 if (ThisVal == (Is64Bit ? 8 : 4)) {
277 // Use push / pop instead.
279 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
280 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
283 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
284 : (Is64Bit ? X86::POP64r : X86::POP32r);
285 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
286 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
288 MI->setFlag(MachineInstr::FrameSetup);
290 MI->setFlag(MachineInstr::FrameDestroy);
296 MachineInstrBuilder MI = BuildStackAdjustment(
297 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue);
299 MI.setMIFlag(MachineInstr::FrameSetup);
301 MI.setMIFlag(MachineInstr::FrameDestroy);
307 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
308 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
309 int64_t Offset, bool InEpilogue) const {
310 assert(Offset != 0 && "zero offset stack adjustment requested");
312 // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
316 UseLEA = STI.useLeaForSP();
318 // If we can use LEA for SP but we shouldn't, check that none
319 // of the terminators uses the eflags. Otherwise we will insert
320 // a ADD that will redefine the eflags and break the condition.
321 // Alternatively, we could move the ADD, but this may not be possible
322 // and is an optimization anyway.
323 UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
324 if (UseLEA && !STI.useLeaForSP())
325 UseLEA = terminatorsNeedFlagsAsInput(MBB);
326 // If that assert breaks, that means we do not do the right thing
327 // in canUseAsEpilogue.
328 assert((UseLEA || !terminatorsNeedFlagsAsInput(MBB)) &&
329 "We shouldn't have allowed this insertion point");
332 MachineInstrBuilder MI;
334 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
335 TII.get(getLEArOpcode(Uses64BitFramePtr)),
337 StackPtr, false, Offset);
339 bool IsSub = Offset < 0;
340 uint64_t AbsOffset = IsSub ? -Offset : Offset;
341 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
342 : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
343 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
346 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
351 int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator &MBBI,
353 bool doMergeWithPrevious) const {
354 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
355 (!doMergeWithPrevious && MBBI == MBB.end()))
358 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
359 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
361 unsigned Opc = PI->getOpcode();
364 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
365 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
366 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
367 PI->getOperand(0).getReg() == StackPtr){
368 Offset += PI->getOperand(2).getImm();
370 if (!doMergeWithPrevious) MBBI = NI;
371 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
372 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
373 PI->getOperand(0).getReg() == StackPtr) {
374 Offset -= PI->getOperand(2).getImm();
376 if (!doMergeWithPrevious) MBBI = NI;
382 void X86FrameLowering::BuildCFI(MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator MBBI, DebugLoc DL,
384 MCCFIInstruction CFIInst) const {
385 MachineFunction &MF = *MBB.getParent();
386 unsigned CFIIndex = MF.getMMI().addFrameInst(CFIInst);
387 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
388 .addCFIIndex(CFIIndex);
392 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator MBBI,
395 MachineFunction &MF = *MBB.getParent();
396 MachineFrameInfo *MFI = MF.getFrameInfo();
397 MachineModuleInfo &MMI = MF.getMMI();
398 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
400 // Add callee saved registers to move list.
401 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
402 if (CSI.empty()) return;
404 // Calculate offsets.
405 for (std::vector<CalleeSavedInfo>::const_iterator
406 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
407 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
408 unsigned Reg = I->getReg();
410 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
411 BuildCFI(MBB, MBBI, DL,
412 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
416 /// usesTheStack - This function checks if any of the users of EFLAGS
417 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
418 /// to use the stack, and if we don't adjust the stack we clobber the first
420 /// See X86InstrInfo::copyPhysReg.
421 static bool usesTheStack(const MachineFunction &MF) {
422 const MachineRegisterInfo &MRI = MF.getRegInfo();
424 for (MachineRegisterInfo::reg_instr_iterator
425 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
433 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
434 MachineBasicBlock &MBB,
435 MachineBasicBlock::iterator MBBI,
437 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
441 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
443 CallOp = X86::CALLpcrel32;
447 if (STI.isTargetCygMing()) {
448 Symbol = "___chkstk_ms";
452 } else if (STI.isTargetCygMing())
457 MachineInstrBuilder CI;
459 // All current stack probes take AX and SP as input, clobber flags, and
460 // preserve all registers. x86_64 probes leave RSP unmodified.
461 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
462 // For the large code model, we have to call through a register. Use R11,
463 // as it is scratch in all supported calling conventions.
464 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
465 .addExternalSymbol(Symbol);
466 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
468 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
471 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
472 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
473 CI.addReg(AX, RegState::Implicit)
474 .addReg(SP, RegState::Implicit)
475 .addReg(AX, RegState::Define | RegState::Implicit)
476 .addReg(SP, RegState::Define | RegState::Implicit)
477 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
480 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
481 // themselves. It also does not clobber %rax so we can reuse it when
483 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
489 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
490 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
491 // and might require smaller successive adjustments.
492 const uint64_t Win64MaxSEHOffset = 128;
493 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
494 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
495 return SEHFrameOffset & -16;
498 // If we're forcing a stack realignment we can't rely on just the frame
499 // info, we need to know the ABI stack alignment as well in case we
500 // have a call out. Otherwise just make sure we have some alignment - we'll
501 // go with the minimum SlotSize.
502 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
503 const MachineFrameInfo *MFI = MF.getFrameInfo();
504 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
505 unsigned StackAlign = getStackAlignment();
506 if (MF.getFunction()->hasFnAttribute("stackrealign")) {
508 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
509 else if (MaxAlign < SlotSize)
515 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
516 MachineBasicBlock::iterator MBBI,
518 uint64_t MaxAlign) const {
519 uint64_t Val = -MaxAlign;
521 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
525 .setMIFlag(MachineInstr::FrameSetup);
527 // The EFLAGS implicit def is dead.
528 MI->getOperand(3).setIsDead();
531 /// emitPrologue - Push callee-saved registers onto the stack, which
532 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
533 /// space for local variables. Also emit labels used by the exception handler to
534 /// generate the exception handling frames.
537 Here's a gist of what gets emitted:
539 ; Establish frame pointer, if needed
542 .cfi_def_cfa_offset 16
543 .cfi_offset %rbp, -16
546 .cfi_def_cfa_register %rbp
548 ; Spill general-purpose registers
549 [for all callee-saved GPRs]
552 .cfi_def_cfa_offset (offset from RETADDR)
555 ; If the required stack alignment > default stack alignment
556 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
557 ; of unknown size in the stack frame.
558 [if stack needs re-alignment]
561 ; Allocate space for locals
562 [if target is Windows and allocated space > 4096 bytes]
563 ; Windows needs special care for allocations larger
566 call ___chkstk_ms/___chkstk
572 .seh_stackalloc (size of XMM spill slots)
573 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
578 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
579 ; they may get spilled on any platform, if the current function
580 ; calls @llvm.eh.unwind.init
582 [for all callee-saved XMM registers]
583 movaps %<xmm reg>, -MMM(%rbp)
584 [for all callee-saved XMM registers]
585 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
586 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
588 [for all callee-saved XMM registers]
589 movaps %<xmm reg>, KKK(%rsp)
590 [for all callee-saved XMM registers]
591 .seh_savexmm %<xmm reg>, KKK
595 [if needs base pointer]
597 [if needs to restore base pointer]
602 [for all callee-saved registers]
603 .cfi_offset %<reg>, (offset from %rbp)
605 .cfi_def_cfa_offset (offset from RETADDR)
606 [for all callee-saved registers]
607 .cfi_offset %<reg>, (offset from %rsp)
610 - .seh directives are emitted only for Windows 64 ABI
611 - .cfi directives are emitted for all other ABIs
612 - for 32-bit code, substitute %e?? registers for %r??
615 void X86FrameLowering::emitPrologue(MachineFunction &MF,
616 MachineBasicBlock &MBB) const {
617 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
618 "MF used frame lowering for wrong subtarget");
619 MachineBasicBlock::iterator MBBI = MBB.begin();
620 MachineFrameInfo *MFI = MF.getFrameInfo();
621 const Function *Fn = MF.getFunction();
622 MachineModuleInfo &MMI = MF.getMMI();
623 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
624 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
625 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
626 bool HasFP = hasFP(MF);
627 bool IsWin64CC = STI.isCallingConvWin64(Fn->getCallingConv());
628 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
629 bool NeedsWinCFI = IsWin64Prologue && Fn->needsUnwindTableEntry();
631 !IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
632 unsigned FramePtr = TRI->getFrameRegister(MF);
633 const unsigned MachineFramePtr =
634 STI.isTarget64BitILP32()
635 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
637 unsigned BasePtr = TRI->getBaseRegister();
640 // Add RETADDR move area to callee saved frame size.
641 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
642 if (TailCallReturnAddrDelta && IsWin64Prologue)
643 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
645 if (TailCallReturnAddrDelta < 0)
646 X86FI->setCalleeSavedFrameSize(
647 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
649 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
651 // The default stack probe size is 4096 if the function has no stackprobesize
653 unsigned StackProbeSize = 4096;
654 if (Fn->hasFnAttribute("stack-probe-size"))
655 Fn->getFnAttribute("stack-probe-size")
657 .getAsInteger(0, StackProbeSize);
659 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
660 // function, and use up to 128 bytes of stack space, don't have a frame
661 // pointer, calls, or dynamic alloca then we do not need to adjust the
662 // stack pointer (we fit in the Red Zone). We also check that we don't
663 // push and pop from the stack.
664 if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
665 !TRI->needsStackRealignment(MF) &&
666 !MFI->hasVarSizedObjects() && // No dynamic alloca.
667 !MFI->adjustsStack() && // No calls.
668 !IsWin64CC && // Win64 has no Red Zone
669 !usesTheStack(MF) && // Don't push and pop.
670 !MF.shouldSplitStack()) { // Regular stack
671 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
672 if (HasFP) MinSize += SlotSize;
673 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
674 MFI->setStackSize(StackSize);
677 // Insert stack pointer adjustment for later moving of return addr. Only
678 // applies to tail call optimized functions where the callee argument stack
679 // size is bigger than the callers.
680 if (TailCallReturnAddrDelta < 0) {
681 BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
682 /*InEpilogue=*/false)
683 .setMIFlag(MachineInstr::FrameSetup);
686 // Mapping for machine moves:
688 // DST: VirtualFP AND
689 // SRC: VirtualFP => DW_CFA_def_cfa_offset
690 // ELSE => DW_CFA_def_cfa
692 // SRC: VirtualFP AND
693 // DST: Register => DW_CFA_def_cfa_register
696 // OFFSET < 0 => DW_CFA_offset_extended_sf
697 // REG < 64 => DW_CFA_offset + Reg
698 // ELSE => DW_CFA_offset_extended
700 uint64_t NumBytes = 0;
701 int stackGrowth = -SlotSize;
703 if (MBB.isEHFuncletEntry()) {
704 assert(STI.isOSWindows() && "funclets only supported on Windows");
706 // Set up the FramePtr and BasePtr physical registers using the address
707 // passed as EBP or RDX by the MSVC EH runtime.
710 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
711 .addReg(MachineFramePtr, RegState::Kill)
712 .setMIFlag(MachineInstr::FrameSetup);
713 // Reset EBP / ESI to something good.
714 MBBI = restoreWin32EHStackPointers(MBB, MBBI, DL);
716 // Immediately spill RDX into the home slot. The runtime cares about this.
717 unsigned RDX = Uses64BitFramePtr ? X86::RDX : X86::EDX;
718 // MOV64mr %rdx, 16(%rsp)
719 unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
720 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)),
723 .setMIFlag(MachineInstr::FrameSetup);
725 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
726 .addReg(MachineFramePtr, RegState::Kill)
727 .setMIFlag(MachineInstr::FrameSetup);
728 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
729 .addImm(MachineFramePtr)
730 .setMIFlag(MachineInstr::FrameSetup);
731 // MOV64rr %rdx, %rbp
732 unsigned MOVrr = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
733 BuildMI(MBB, MBBI, DL, TII.get(MOVrr), FramePtr)
735 .setMIFlag(MachineInstr::FrameSetup);
736 assert(!TRI->hasBasePointer(MF) &&
737 "x64 funclets with base ptrs not yet implemented");
740 // For EH funclets, only allocate enough space for outgoing calls.
741 NumBytes = MFI->getMaxCallFrameSize();
743 // Calculate required stack adjustment.
744 uint64_t FrameSize = StackSize - SlotSize;
745 // If required, include space for extra hidden slot for stashing base pointer.
746 if (X86FI->getRestoreBasePointer())
747 FrameSize += SlotSize;
749 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
751 // Callee-saved registers are pushed on stack before the stack is realigned.
752 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
753 NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
755 // Get the offset of the stack slot for the EBP register, which is
756 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
757 // Update the frame offset adjustment.
758 MFI->setOffsetAdjustment(-NumBytes);
760 // Save EBP/RBP into the appropriate stack slot.
761 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
762 .addReg(MachineFramePtr, RegState::Kill)
763 .setMIFlag(MachineInstr::FrameSetup);
766 // Mark the place where EBP/RBP was saved.
767 // Define the current CFA rule to use the provided offset.
769 BuildCFI(MBB, MBBI, DL,
770 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
772 // Change the rule for the FramePtr to be an "offset" rule.
773 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
774 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
775 nullptr, DwarfFramePtr, 2 * stackGrowth));
779 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
781 .setMIFlag(MachineInstr::FrameSetup);
784 if (!IsWin64Prologue) {
785 // Update EBP with the new base value.
786 BuildMI(MBB, MBBI, DL,
787 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
790 .setMIFlag(MachineInstr::FrameSetup);
794 // Mark effective beginning of when frame pointer becomes valid.
795 // Define the current CFA to use the EBP/RBP register.
796 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
797 BuildCFI(MBB, MBBI, DL,
798 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
801 // Mark the FramePtr as live-in in every block.
802 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
803 I->addLiveIn(MachineFramePtr);
805 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
808 // Skip the callee-saved push instructions.
809 bool PushedRegs = false;
810 int StackOffset = 2 * stackGrowth;
812 while (MBBI != MBB.end() &&
813 MBBI->getFlag(MachineInstr::FrameSetup) &&
814 (MBBI->getOpcode() == X86::PUSH32r ||
815 MBBI->getOpcode() == X86::PUSH64r)) {
817 unsigned Reg = MBBI->getOperand(0).getReg();
820 if (!HasFP && NeedsDwarfCFI) {
821 // Mark callee-saved push instruction.
822 // Define the current CFA rule to use the provided offset.
824 BuildCFI(MBB, MBBI, DL,
825 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
826 StackOffset += stackGrowth;
830 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
831 MachineInstr::FrameSetup);
835 // Realign stack after we pushed callee-saved registers (so that we'll be
836 // able to calculate their offsets from the frame pointer).
837 // Don't do this for Win64, it needs to realign the stack after the prologue.
838 if (!IsWin64Prologue && TRI->needsStackRealignment(MF)) {
839 assert(HasFP && "There should be a frame pointer if stack is realigned.");
840 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
843 // If there is an SUB32ri of ESP immediately before this instruction, merge
844 // the two. This can be the case when tail call elimination is enabled and
845 // the callee has more arguments then the caller.
846 NumBytes -= mergeSPUpdates(MBB, MBBI, true);
848 // Adjust stack pointer: ESP -= numbytes.
850 // Windows and cygwin/mingw require a prologue helper routine when allocating
851 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
852 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
853 // stack and adjust the stack pointer in one go. The 64-bit version of
854 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
855 // responsible for adjusting the stack pointer. Touching the stack at 4K
856 // increments is necessary to ensure that the guard pages used by the OS
857 // virtual memory manager are allocated in correct sequence.
858 uint64_t AlignedNumBytes = NumBytes;
859 if (IsWin64Prologue && TRI->needsStackRealignment(MF))
860 AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
861 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
862 // Check whether EAX is livein for this function.
863 bool isEAXAlive = isEAXLiveIn(MF);
866 // Sanity check that EAX is not livein for this function.
867 // It should not be, so throw an assert.
868 assert(!Is64Bit && "EAX is livein in x64 case!");
871 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
872 .addReg(X86::EAX, RegState::Kill)
873 .setMIFlag(MachineInstr::FrameSetup);
877 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
878 // Function prologue is responsible for adjusting the stack pointer.
879 if (isUInt<32>(NumBytes)) {
880 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
882 .setMIFlag(MachineInstr::FrameSetup);
883 } else if (isInt<32>(NumBytes)) {
884 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
886 .setMIFlag(MachineInstr::FrameSetup);
888 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
890 .setMIFlag(MachineInstr::FrameSetup);
893 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
894 // We'll also use 4 already allocated bytes for EAX.
895 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
896 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
897 .setMIFlag(MachineInstr::FrameSetup);
900 // Save a pointer to the MI where we set AX.
901 MachineBasicBlock::iterator SetRAX = MBBI;
904 // Call __chkstk, __chkstk_ms, or __alloca.
905 emitStackProbeCall(MF, MBB, MBBI, DL);
907 // Apply the frame setup flag to all inserted instrs.
908 for (; SetRAX != MBBI; ++SetRAX)
909 SetRAX->setFlag(MachineInstr::FrameSetup);
913 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
915 StackPtr, false, NumBytes - 4);
916 MI->setFlag(MachineInstr::FrameSetup);
917 MBB.insert(MBBI, MI);
919 } else if (NumBytes) {
920 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false);
923 if (NeedsWinCFI && NumBytes)
924 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
926 .setMIFlag(MachineInstr::FrameSetup);
928 int SEHFrameOffset = 0;
929 if (IsWin64Prologue && HasFP) {
930 SEHFrameOffset = calculateSetFPREG(NumBytes);
932 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
933 StackPtr, false, SEHFrameOffset);
935 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr).addReg(StackPtr);
938 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
940 .addImm(SEHFrameOffset)
941 .setMIFlag(MachineInstr::FrameSetup);
944 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
945 const MachineInstr *FrameInstr = &*MBBI;
950 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
951 if (X86::FR64RegClass.contains(Reg)) {
952 unsigned IgnoredFrameReg;
953 int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
954 Offset += SEHFrameOffset;
956 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
959 .setMIFlag(MachineInstr::FrameSetup);
966 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
967 .setMIFlag(MachineInstr::FrameSetup);
969 // Realign stack after we spilled callee-saved registers (so that we'll be
970 // able to calculate their offsets from the frame pointer).
971 // Win64 requires aligning the stack after the prologue.
972 if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
973 assert(HasFP && "There should be a frame pointer if stack is realigned.");
974 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
977 // If we need a base pointer, set it up here. It's whatever the value
978 // of the stack pointer is at this point. Any variable size objects
979 // will be allocated after this, so we can still use the base pointer
980 // to reference locals.
981 if (TRI->hasBasePointer(MF)) {
982 // Update the base pointer with the current stack pointer.
983 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
984 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
986 .setMIFlag(MachineInstr::FrameSetup);
987 if (X86FI->getRestoreBasePointer()) {
988 // Stash value of base pointer. Saving RSP instead of EBP shortens
989 // dependence chain. Used by SjLj EH.
990 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
991 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
992 FramePtr, true, X86FI->getRestoreBasePointerOffset())
994 .setMIFlag(MachineInstr::FrameSetup);
997 if (X86FI->getHasSEHFramePtrSave()) {
998 // Stash the value of the frame pointer relative to the base pointer for
999 // Win32 EH. This supports Win32 EH, which does the inverse of the above:
1000 // it recovers the frame pointer from the base pointer rather than the
1001 // other way around.
1002 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1005 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
1006 assert(UsedReg == BasePtr);
1007 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1009 .setMIFlag(MachineInstr::FrameSetup);
1013 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1014 // Mark end of stack pointer adjustment.
1015 if (!HasFP && NumBytes) {
1016 // Define the current CFA rule to use the provided offset.
1018 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
1019 nullptr, -StackSize + stackGrowth));
1022 // Emit DWARF info specifying the offsets of the callee-saved registers.
1024 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1028 bool X86FrameLowering::canUseLEAForSPInEpilogue(
1029 const MachineFunction &MF) const {
1030 // We can't use LEA instructions for adjusting the stack pointer if this is a
1031 // leaf function in the Win64 ABI. Only ADD instructions may be used to
1032 // deallocate the stack.
1033 // This means that we can use LEA for SP in two situations:
1034 // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1035 // 2. We *have* a frame pointer which means we are permitted to use LEA.
1036 return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1039 static bool isFuncletReturnInstr(MachineInstr *MI) {
1040 switch (MI->getOpcode()) {
1042 case X86::CLEANUPRET:
1047 llvm_unreachable("impossible");
1050 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
1051 MachineBasicBlock &MBB) const {
1052 const MachineFrameInfo *MFI = MF.getFrameInfo();
1053 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1054 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
1056 if (MBBI != MBB.end())
1057 DL = MBBI->getDebugLoc();
1058 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1059 const bool Is64BitILP32 = STI.isTarget64BitILP32();
1060 unsigned FramePtr = TRI->getFrameRegister(MF);
1061 unsigned MachineFramePtr =
1062 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
1065 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1067 IsWin64Prologue && MF.getFunction()->needsUnwindTableEntry();
1069 // Get the number of bytes to allocate from the FrameInfo.
1070 uint64_t StackSize = MFI->getStackSize();
1071 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1072 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1073 uint64_t NumBytes = 0;
1075 if (MBBI->getOpcode() == X86::CATCHRET) {
1076 NumBytes = MFI->getMaxCallFrameSize();
1077 assert(hasFP(MF) && "EH funclets without FP not yet implemented");
1078 MachineBasicBlock *TargetMBB = MBBI->getOperand(0).getMBB();
1080 // If this is SEH, this isn't really a funclet return.
1081 bool IsSEH = isAsynchronousEHPersonality(
1082 classifyEHPersonality(MF.getFunction()->getPersonalityFn()));
1085 restoreWin32EHStackPointers(MBB, MBBI, DL, /*RestoreSP=*/true);
1086 BuildMI(MBB, MBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
1087 MBBI->eraseFromParent();
1091 // For 32-bit, create a new block for the restore code.
1092 MachineBasicBlock *RestoreMBB = TargetMBB;
1093 if (STI.is32Bit()) {
1094 RestoreMBB = MF.CreateMachineBasicBlock(MBB.getBasicBlock());
1095 MF.insert(TargetMBB, RestoreMBB);
1096 MBB.transferSuccessors(RestoreMBB);
1097 MBB.addSuccessor(RestoreMBB);
1098 MBBI->getOperand(0).setMBB(RestoreMBB);
1102 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1104 .setMIFlag(MachineInstr::FrameDestroy);
1106 // Insert frame restoration code in a new block.
1107 if (STI.is32Bit()) {
1108 auto RestoreMBBI = RestoreMBB->begin();
1109 restoreWin32EHStackPointers(*RestoreMBB, RestoreMBBI, DL,
1110 /*RestoreSP=*/true);
1111 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4))
1114 } else if (isFuncletReturnInstr(MBBI)) {
1115 NumBytes = MFI->getMaxCallFrameSize();
1116 assert(hasFP(MF) && "EH funclets without FP not yet implemented");
1117 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1119 .setMIFlag(MachineInstr::FrameDestroy);
1120 } else if (hasFP(MF)) {
1121 // Calculate required stack adjustment.
1122 uint64_t FrameSize = StackSize - SlotSize;
1123 NumBytes = FrameSize - CSSize;
1125 // Callee-saved registers were pushed on stack before the stack was
1127 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1128 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1131 BuildMI(MBB, MBBI, DL,
1132 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr)
1133 .setMIFlag(MachineInstr::FrameDestroy);
1135 NumBytes = StackSize - CSSize;
1137 uint64_t SEHStackAllocAmt = NumBytes;
1139 // Skip the callee-saved pop instructions.
1140 while (MBBI != MBB.begin()) {
1141 MachineBasicBlock::iterator PI = std::prev(MBBI);
1142 unsigned Opc = PI->getOpcode();
1144 if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1145 (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1146 Opc != X86::DBG_VALUE && !PI->isTerminator())
1151 MachineBasicBlock::iterator FirstCSPop = MBBI;
1153 if (MBBI != MBB.end())
1154 DL = MBBI->getDebugLoc();
1156 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1157 // instruction, merge the two instructions.
1158 if (NumBytes || MFI->hasVarSizedObjects())
1159 NumBytes += mergeSPUpdates(MBB, MBBI, true);
1161 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1162 // slot before popping them off! Same applies for the case, when stack was
1164 if (TRI->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1165 if (TRI->needsStackRealignment(MF))
1167 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1168 uint64_t LEAAmount =
1169 IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1171 // There are only two legal forms of epilogue:
1172 // - add SEHAllocationSize, %rsp
1173 // - lea SEHAllocationSize(%FramePtr), %rsp
1175 // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1176 // However, we may use this sequence if we have a frame pointer because the
1177 // effects of the prologue can safely be undone.
1178 if (LEAAmount != 0) {
1179 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1180 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1181 FramePtr, false, LEAAmount);
1184 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1185 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1189 } else if (NumBytes) {
1190 // Adjust stack pointer back: ESP += numbytes.
1191 emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
1195 // Windows unwinder will not invoke function's exception handler if IP is
1196 // either in prologue or in epilogue. This behavior causes a problem when a
1197 // call immediately precedes an epilogue, because the return address points
1198 // into the epilogue. To cope with that, we insert an epilogue marker here,
1199 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1200 // final emitted code.
1202 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1204 // Add the return addr area delta back since we are not tail calling.
1205 int Offset = -1 * X86FI->getTCReturnAddrDelta();
1206 assert(Offset >= 0 && "TCDelta should never be positive");
1208 MBBI = MBB.getFirstTerminator();
1210 // Check for possible merge with preceding ADD instruction.
1211 Offset += mergeSPUpdates(MBB, MBBI, true);
1212 emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
1216 // NOTE: this only has a subset of the full frame index logic. In
1217 // particular, the FI < 0 and AfterFPPop logic is handled in
1218 // X86RegisterInfo::eliminateFrameIndex, but not here. Possibly
1219 // (probably?) it should be moved into here.
1220 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1221 unsigned &FrameReg) const {
1222 const MachineFrameInfo *MFI = MF.getFrameInfo();
1224 // We can't calculate offset from frame pointer if the stack is realigned,
1225 // so enforce usage of stack/base pointer. The base pointer is used when we
1226 // have dynamic allocas in addition to dynamic realignment.
1227 if (TRI->hasBasePointer(MF))
1228 FrameReg = TRI->getBaseRegister();
1229 else if (TRI->needsStackRealignment(MF))
1230 FrameReg = TRI->getStackRegister();
1232 FrameReg = TRI->getFrameRegister(MF);
1234 // Offset will hold the offset from the stack pointer at function entry to the
1236 // We need to factor in additional offsets applied during the prologue to the
1237 // frame, base, and stack pointer depending on which is used.
1238 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1239 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1240 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1241 uint64_t StackSize = MFI->getStackSize();
1242 bool HasFP = hasFP(MF);
1243 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1244 int64_t FPDelta = 0;
1246 if (IsWin64Prologue) {
1247 assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1249 // Calculate required stack adjustment.
1250 uint64_t FrameSize = StackSize - SlotSize;
1251 // If required, include space for extra hidden slot for stashing base pointer.
1252 if (X86FI->getRestoreBasePointer())
1253 FrameSize += SlotSize;
1254 uint64_t NumBytes = FrameSize - CSSize;
1256 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1257 if (FI && FI == X86FI->getFAIndex())
1258 return -SEHFrameOffset;
1260 // FPDelta is the offset from the "traditional" FP location of the old base
1261 // pointer followed by return address and the location required by the
1262 // restricted Win64 prologue.
1263 // Add FPDelta to all offsets below that go through the frame pointer.
1264 FPDelta = FrameSize - SEHFrameOffset;
1265 assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1266 "FPDelta isn't aligned per the Win64 ABI!");
1270 if (TRI->hasBasePointer(MF)) {
1271 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1273 // Skip the saved EBP.
1274 return Offset + SlotSize + FPDelta;
1276 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1277 return Offset + StackSize;
1279 } else if (TRI->needsStackRealignment(MF)) {
1281 // Skip the saved EBP.
1282 return Offset + SlotSize + FPDelta;
1284 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1285 return Offset + StackSize;
1287 // FIXME: Support tail calls
1290 return Offset + StackSize;
1292 // Skip the saved EBP.
1295 // Skip the RETADDR move area
1296 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1297 if (TailCallReturnAddrDelta < 0)
1298 Offset -= TailCallReturnAddrDelta;
1301 return Offset + FPDelta;
1304 // Simplified from getFrameIndexReference keeping only StackPointer cases
1305 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1307 unsigned &FrameReg) const {
1308 const MachineFrameInfo *MFI = MF.getFrameInfo();
1309 // Does not include any dynamic realign.
1310 const uint64_t StackSize = MFI->getStackSize();
1313 // Note: LLVM arranges the stack as:
1314 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1315 // > "Stack Slots" (<--SP)
1316 // We can always address StackSlots from RSP. We can usually (unless
1317 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1318 // address them from RBP. FixedObjects can be placed anywhere in the stack
1319 // frame depending on their specific requirements (i.e. we can actually
1320 // refer to arguments to the function which are stored in the *callers*
1321 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1322 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1324 assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1326 // We don't handle tail calls, and shouldn't be seeing them
1328 int TailCallReturnAddrDelta =
1329 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1330 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1334 // Fill in FrameReg output argument.
1335 FrameReg = TRI->getStackRegister();
1337 // This is how the math works out:
1339 // %rsp grows (i.e. gets lower) left to right. Each box below is
1340 // one word (eight bytes). Obj0 is the stack slot we're trying to
1343 // ----------------------------------
1344 // | BP | Obj0 | Obj1 | ... | ObjN |
1345 // ----------------------------------
1349 // A is the incoming stack pointer.
1350 // (B - A) is the local area offset (-8 for x86-64) [1]
1351 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1353 // |(E - B)| is the StackSize (absolute value, positive). For a
1354 // stack that grown down, this works out to be (B - E). [3]
1356 // E is also the value of %rsp after stack has been set up, and we
1357 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1358 // (C - E) == (C - A) - (B - A) + (B - E)
1359 // { Using [1], [2] and [3] above }
1360 // == getObjectOffset - LocalAreaOffset + StackSize
1363 // Get the Offset from the StackPointer
1364 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1366 return Offset + StackSize;
1369 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1370 MachineFunction &MF, const TargetRegisterInfo *TRI,
1371 std::vector<CalleeSavedInfo> &CSI) const {
1372 MachineFrameInfo *MFI = MF.getFrameInfo();
1373 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1375 unsigned CalleeSavedFrameSize = 0;
1376 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1379 // emitPrologue always spills frame register the first thing.
1380 SpillSlotOffset -= SlotSize;
1381 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1383 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1384 // the frame register, we can delete it from CSI list and not have to worry
1385 // about avoiding it later.
1386 unsigned FPReg = TRI->getFrameRegister(MF);
1387 for (unsigned i = 0; i < CSI.size(); ++i) {
1388 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1389 CSI.erase(CSI.begin() + i);
1395 // Assign slots for GPRs. It increases frame size.
1396 for (unsigned i = CSI.size(); i != 0; --i) {
1397 unsigned Reg = CSI[i - 1].getReg();
1399 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1402 SpillSlotOffset -= SlotSize;
1403 CalleeSavedFrameSize += SlotSize;
1405 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1406 CSI[i - 1].setFrameIdx(SlotIndex);
1409 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1411 // Assign slots for XMMs.
1412 for (unsigned i = CSI.size(); i != 0; --i) {
1413 unsigned Reg = CSI[i - 1].getReg();
1414 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1417 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1419 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1421 SpillSlotOffset -= RC->getSize();
1423 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1424 CSI[i - 1].setFrameIdx(SlotIndex);
1425 MFI->ensureMaxAlignment(RC->getAlignment());
1431 bool X86FrameLowering::spillCalleeSavedRegisters(
1432 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1433 const std::vector<CalleeSavedInfo> &CSI,
1434 const TargetRegisterInfo *TRI) const {
1435 DebugLoc DL = MBB.findDebugLoc(MI);
1437 // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
1438 // for us, and there are no XMM CSRs on Win32.
1439 if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
1442 // Push GPRs. It increases frame size.
1443 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1444 for (unsigned i = CSI.size(); i != 0; --i) {
1445 unsigned Reg = CSI[i - 1].getReg();
1447 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1449 // Add the callee-saved register as live-in. It's killed at the spill.
1452 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1453 .setMIFlag(MachineInstr::FrameSetup);
1456 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1457 // It can be done by spilling XMMs to stack frame.
1458 for (unsigned i = CSI.size(); i != 0; --i) {
1459 unsigned Reg = CSI[i-1].getReg();
1460 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1462 // Add the callee-saved register as live-in. It's killed at the spill.
1464 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1466 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1469 MI->setFlag(MachineInstr::FrameSetup);
1476 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1477 MachineBasicBlock::iterator MI,
1478 const std::vector<CalleeSavedInfo> &CSI,
1479 const TargetRegisterInfo *TRI) const {
1483 // Don't restore CSRs in 32-bit EH funclets. Matches
1484 // spillCalleeSavedRegisters.
1485 if (isFuncletReturnInstr(MI) && STI.is32Bit() && STI.isOSWindows())
1488 DebugLoc DL = MBB.findDebugLoc(MI);
1490 // Reload XMMs from stack frame.
1491 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1492 unsigned Reg = CSI[i].getReg();
1493 if (X86::GR64RegClass.contains(Reg) ||
1494 X86::GR32RegClass.contains(Reg))
1497 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1498 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1502 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1503 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1504 unsigned Reg = CSI[i].getReg();
1505 if (!X86::GR64RegClass.contains(Reg) &&
1506 !X86::GR32RegClass.contains(Reg))
1509 BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
1510 .setMIFlag(MachineInstr::FrameDestroy);
1515 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
1516 BitVector &SavedRegs,
1517 RegScavenger *RS) const {
1518 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1520 MachineFrameInfo *MFI = MF.getFrameInfo();
1522 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1523 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1525 if (TailCallReturnAddrDelta < 0) {
1526 // create RETURNADDR area
1535 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1536 TailCallReturnAddrDelta - SlotSize, true);
1539 // Spill the BasePtr if it's used.
1540 if (TRI->hasBasePointer(MF)) {
1541 SavedRegs.set(TRI->getBaseRegister());
1543 // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
1544 if (MF.getMMI().hasEHFunclets()) {
1545 int FI = MFI->CreateSpillStackObject(SlotSize, SlotSize);
1546 X86FI->setHasSEHFramePtrSave(true);
1547 X86FI->setSEHFramePtrSaveIndex(FI);
1553 HasNestArgument(const MachineFunction *MF) {
1554 const Function *F = MF->getFunction();
1555 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1557 if (I->hasNestAttr())
1563 /// GetScratchRegister - Get a temp register for performing work in the
1564 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1565 /// and the properties of the function either one or two registers will be
1566 /// needed. Set primary to true for the first register, false for the second.
1568 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1569 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1572 if (CallingConvention == CallingConv::HiPE) {
1574 return Primary ? X86::R14 : X86::R13;
1576 return Primary ? X86::EBX : X86::EDI;
1581 return Primary ? X86::R11 : X86::R12;
1583 return Primary ? X86::R11D : X86::R12D;
1586 bool IsNested = HasNestArgument(&MF);
1588 if (CallingConvention == CallingConv::X86_FastCall ||
1589 CallingConvention == CallingConv::Fast) {
1591 report_fatal_error("Segmented stacks does not support fastcall with "
1592 "nested function.");
1593 return Primary ? X86::EAX : X86::ECX;
1596 return Primary ? X86::EDX : X86::EAX;
1597 return Primary ? X86::ECX : X86::EAX;
1600 // The stack limit in the TCB is set to this many bytes above the actual stack
1602 static const uint64_t kSplitStackAvailable = 256;
1604 void X86FrameLowering::adjustForSegmentedStacks(
1605 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1606 MachineFrameInfo *MFI = MF.getFrameInfo();
1608 unsigned TlsReg, TlsOffset;
1611 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1612 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1613 "Scratch register is live-in");
1615 if (MF.getFunction()->isVarArg())
1616 report_fatal_error("Segmented stacks do not support vararg functions.");
1617 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1618 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1619 !STI.isTargetDragonFly())
1620 report_fatal_error("Segmented stacks not supported on this platform.");
1622 // Eventually StackSize will be calculated by a link-time pass; which will
1623 // also decide whether checking code needs to be injected into this particular
1625 StackSize = MFI->getStackSize();
1627 // Do not generate a prologue for functions with a stack of size zero
1631 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1632 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1633 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1634 bool IsNested = false;
1636 // We need to know if the function has a nest argument only in 64 bit mode.
1638 IsNested = HasNestArgument(&MF);
1640 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1641 // allocMBB needs to be last (terminating) instruction.
1643 for (const auto &LI : PrologueMBB.liveins()) {
1644 allocMBB->addLiveIn(LI);
1645 checkMBB->addLiveIn(LI);
1649 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1651 MF.push_front(allocMBB);
1652 MF.push_front(checkMBB);
1654 // When the frame size is less than 256 we just compare the stack
1655 // boundary directly to the value of the stack pointer, per gcc.
1656 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1658 // Read the limit off the current stacklet off the stack_guard location.
1660 if (STI.isTargetLinux()) {
1662 TlsOffset = IsLP64 ? 0x70 : 0x40;
1663 } else if (STI.isTargetDarwin()) {
1665 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1666 } else if (STI.isTargetWin64()) {
1668 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1669 } else if (STI.isTargetFreeBSD()) {
1672 } else if (STI.isTargetDragonFly()) {
1674 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1676 report_fatal_error("Segmented stacks not supported on this platform.");
1679 if (CompareStackPointer)
1680 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1682 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1683 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1685 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1686 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1688 if (STI.isTargetLinux()) {
1691 } else if (STI.isTargetDarwin()) {
1693 TlsOffset = 0x48 + 90*4;
1694 } else if (STI.isTargetWin32()) {
1696 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1697 } else if (STI.isTargetDragonFly()) {
1699 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1700 } else if (STI.isTargetFreeBSD()) {
1701 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1703 report_fatal_error("Segmented stacks not supported on this platform.");
1706 if (CompareStackPointer)
1707 ScratchReg = X86::ESP;
1709 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1710 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1712 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1713 STI.isTargetDragonFly()) {
1714 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1715 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1716 } else if (STI.isTargetDarwin()) {
1718 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1719 unsigned ScratchReg2;
1721 if (CompareStackPointer) {
1722 // The primary scratch register is available for holding the TLS offset.
1723 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1724 SaveScratch2 = false;
1726 // Need to use a second register to hold the TLS offset
1727 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1729 // Unfortunately, with fastcc the second scratch register may hold an
1731 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1734 // If Scratch2 is live-in then it needs to be saved.
1735 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1736 "Scratch register is live-in and not saved");
1739 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1740 .addReg(ScratchReg2, RegState::Kill);
1742 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1744 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1746 .addReg(ScratchReg2).addImm(1).addReg(0)
1751 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1755 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1756 // It jumps to normal execution of the function body.
1757 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
1759 // On 32 bit we first push the arguments size and then the frame size. On 64
1760 // bit, we pass the stack frame size in r10 and the argument size in r11.
1762 // Functions with nested arguments use R10, so it needs to be saved across
1763 // the call to _morestack
1765 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1766 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1767 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1768 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1769 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1772 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1774 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1776 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1777 .addImm(X86FI->getArgumentStackSize());
1779 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1780 .addImm(X86FI->getArgumentStackSize());
1781 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1785 // __morestack is in libgcc
1786 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1787 // Under the large code model, we cannot assume that __morestack lives
1788 // within 2^31 bytes of the call site, so we cannot use pc-relative
1789 // addressing. We cannot perform the call via a temporary register,
1790 // as the rax register may be used to store the static chain, and all
1791 // other suitable registers may be either callee-save or used for
1792 // parameter passing. We cannot use the stack at this point either
1793 // because __morestack manipulates the stack directly.
1795 // To avoid these issues, perform an indirect call via a read-only memory
1796 // location containing the address.
1798 // This solution is not perfect, as it assumes that the .rodata section
1799 // is laid out within 2^31 bytes of each function body, but this seems
1800 // to be sufficient for JIT.
1801 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1805 .addExternalSymbol("__morestack_addr")
1807 MF.getMMI().setUsesMorestackAddr(true);
1810 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1811 .addExternalSymbol("__morestack");
1813 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1814 .addExternalSymbol("__morestack");
1818 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1820 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1822 allocMBB->addSuccessor(&PrologueMBB);
1824 checkMBB->addSuccessor(allocMBB);
1825 checkMBB->addSuccessor(&PrologueMBB);
1832 /// Erlang programs may need a special prologue to handle the stack size they
1833 /// might need at runtime. That is because Erlang/OTP does not implement a C
1834 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1835 /// (for more information see Eric Stenman's Ph.D. thesis:
1836 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1839 /// temp0 = sp - MaxStack
1840 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1844 /// call inc_stack # doubles the stack space
1845 /// temp0 = sp - MaxStack
1846 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1847 void X86FrameLowering::adjustForHiPEPrologue(
1848 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1849 MachineFrameInfo *MFI = MF.getFrameInfo();
1851 // HiPE-specific values
1852 const unsigned HipeLeafWords = 24;
1853 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1854 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1855 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1856 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1857 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1859 assert(STI.isTargetLinux() &&
1860 "HiPE prologue is only supported on Linux operating systems.");
1862 // Compute the largest caller's frame that is needed to fit the callees'
1863 // frames. This 'MaxStack' is computed from:
1865 // a) the fixed frame size, which is the space needed for all spilled temps,
1866 // b) outgoing on-stack parameter areas, and
1867 // c) the minimum stack space this function needs to make available for the
1868 // functions it calls (a tunable ABI property).
1869 if (MFI->hasCalls()) {
1870 unsigned MoreStackForCalls = 0;
1872 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1873 MBBI != MBBE; ++MBBI)
1874 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1879 // Get callee operand.
1880 const MachineOperand &MO = MI->getOperand(0);
1882 // Only take account of global function calls (no closures etc.).
1886 const Function *F = dyn_cast<Function>(MO.getGlobal());
1890 // Do not update 'MaxStack' for primitive and built-in functions
1891 // (encoded with names either starting with "erlang."/"bif_" or not
1892 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1893 // "_", such as the BIF "suspend_0") as they are executed on another
1895 if (F->getName().find("erlang.") != StringRef::npos ||
1896 F->getName().find("bif_") != StringRef::npos ||
1897 F->getName().find_first_of("._") == StringRef::npos)
1900 unsigned CalleeStkArity =
1901 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1902 if (HipeLeafWords - 1 > CalleeStkArity)
1903 MoreStackForCalls = std::max(MoreStackForCalls,
1904 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1906 MaxStack += MoreStackForCalls;
1909 // If the stack frame needed is larger than the guaranteed then runtime checks
1910 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1911 if (MaxStack > Guaranteed) {
1912 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1913 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1915 for (const auto &LI : PrologueMBB.liveins()) {
1916 stackCheckMBB->addLiveIn(LI);
1917 incStackMBB->addLiveIn(LI);
1920 MF.push_front(incStackMBB);
1921 MF.push_front(stackCheckMBB);
1923 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1924 unsigned LEAop, CMPop, CALLop;
1928 LEAop = X86::LEA64r;
1929 CMPop = X86::CMP64rm;
1930 CALLop = X86::CALL64pcrel32;
1931 SPLimitOffset = 0x90;
1935 LEAop = X86::LEA32r;
1936 CMPop = X86::CMP32rm;
1937 CALLop = X86::CALLpcrel32;
1938 SPLimitOffset = 0x4c;
1941 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1942 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1943 "HiPE prologue scratch register is live-in");
1945 // Create new MBB for StackCheck:
1946 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1947 SPReg, false, -MaxStack);
1948 // SPLimitOffset is in a fixed heap location (pointed by BP).
1949 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1950 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1951 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
1953 // Create new MBB for IncStack:
1954 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1955 addExternalSymbol("inc_stack_0");
1956 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1957 SPReg, false, -MaxStack);
1958 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1959 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1960 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1962 stackCheckMBB->addSuccessor(&PrologueMBB, 99);
1963 stackCheckMBB->addSuccessor(incStackMBB, 1);
1964 incStackMBB->addSuccessor(&PrologueMBB, 99);
1965 incStackMBB->addSuccessor(incStackMBB, 1);
1972 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
1973 MachineBasicBlock::iterator MBBI, DebugLoc DL, int Offset) const {
1978 if (Offset % SlotSize)
1981 int NumPops = Offset / SlotSize;
1982 // This is only worth it if we have at most 2 pops.
1983 if (NumPops != 1 && NumPops != 2)
1986 // Handle only the trivial case where the adjustment directly follows
1987 // a call. This is the most common one, anyway.
1988 if (MBBI == MBB.begin())
1990 MachineBasicBlock::iterator Prev = std::prev(MBBI);
1991 if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
1995 unsigned FoundRegs = 0;
1997 auto RegMask = Prev->getOperand(1);
2000 Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
2001 // Try to find up to NumPops free registers.
2002 for (auto Candidate : RegClass) {
2004 // Poor man's liveness:
2005 // Since we're immediately after a call, any register that is clobbered
2006 // by the call and not defined by it can be considered dead.
2007 if (!RegMask.clobbersPhysReg(Candidate))
2011 for (const MachineOperand &MO : Prev->implicit_operands()) {
2012 if (MO.isReg() && MO.isDef() && MO.getReg() == Candidate) {
2021 Regs[FoundRegs++] = Candidate;
2022 if (FoundRegs == (unsigned)NumPops)
2029 // If we found only one free register, but need two, reuse the same one twice.
2030 while (FoundRegs < (unsigned)NumPops)
2031 Regs[FoundRegs++] = Regs[0];
2033 for (int i = 0; i < NumPops; ++i)
2034 BuildMI(MBB, MBBI, DL,
2035 TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
2040 void X86FrameLowering::
2041 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
2042 MachineBasicBlock::iterator I) const {
2043 bool reserveCallFrame = hasReservedCallFrame(MF);
2044 unsigned Opcode = I->getOpcode();
2045 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2046 DebugLoc DL = I->getDebugLoc();
2047 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
2048 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
2051 if (!reserveCallFrame) {
2052 // If the stack pointer can be changed after prologue, turn the
2053 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2054 // adjcallstackdown instruction into 'add ESP, <amt>'
2058 // We need to keep the stack aligned properly. To do this, we round the
2059 // amount of space needed for the outgoing arguments up to the next
2060 // alignment boundary.
2061 unsigned StackAlign = getStackAlignment();
2062 Amount = RoundUpToAlignment(Amount, StackAlign);
2064 // Factor out the amount that gets handled inside the sequence
2065 // (Pushes of argument for frame setup, callee pops for frame destroy)
2066 Amount -= InternalAmt;
2069 // Add Amount to SP to destroy a frame, and subtract to setup.
2070 int Offset = isDestroy ? Amount : -Amount;
2072 if (!(MF.getFunction()->optForMinSize() &&
2073 adjustStackWithPops(MBB, I, DL, Offset)))
2074 BuildStackAdjustment(MBB, I, DL, Offset, /*InEpilogue=*/false);
2080 if (isDestroy && InternalAmt) {
2081 // If we are performing frame pointer elimination and if the callee pops
2082 // something off the stack pointer, add it back. We do this until we have
2083 // more advanced stack pointer tracking ability.
2084 // We are not tracking the stack pointer adjustment by the callee, so make
2085 // sure we restore the stack pointer immediately after the call, there may
2086 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2087 MachineBasicBlock::iterator B = MBB.begin();
2088 while (I != B && !std::prev(I)->isCall())
2090 BuildStackAdjustment(MBB, I, DL, -InternalAmt, /*InEpilogue=*/false);
2094 bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
2095 assert(MBB.getParent() && "Block is not attached to a function!");
2097 if (canUseLEAForSPInEpilogue(*MBB.getParent()))
2100 // If we cannot use LEA to adjust SP, we may need to use ADD, which
2101 // clobbers the EFLAGS. Check that none of the terminators reads the
2102 // EFLAGS, and if one uses it, conservatively assume this is not
2103 // safe to insert the epilogue here.
2104 return !terminatorsNeedFlagsAsInput(MBB);
2107 MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHStackPointers(
2108 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
2109 DebugLoc DL, bool RestoreSP) const {
2110 assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
2111 assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
2112 assert(STI.is32Bit() && !Uses64BitFramePtr &&
2113 "restoring EBP/ESI on non-32-bit target");
2115 MachineFunction &MF = *MBB.getParent();
2116 unsigned FramePtr = TRI->getFrameRegister(MF);
2117 unsigned BasePtr = TRI->getBaseRegister();
2118 MachineModuleInfo &MMI = MF.getMMI();
2119 const Function *Fn = MF.getFunction();
2120 WinEHFuncInfo &FuncInfo = MMI.getWinEHFuncInfo(Fn);
2121 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2122 MachineFrameInfo *MFI = MF.getFrameInfo();
2124 // FIXME: Don't set FrameSetup flag in catchret case.
2126 int FI = FuncInfo.EHRegNodeFrameIndex;
2127 int EHRegSize = MFI->getObjectSize(FI);
2130 // MOV32rm -EHRegSize(%ebp), %esp
2131 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2132 X86::EBP, true, -EHRegSize)
2133 .setMIFlag(MachineInstr::FrameSetup);
2137 int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg);
2138 int EndOffset = -EHRegOffset - EHRegSize;
2139 FuncInfo.EHRegNodeEndOffset = EndOffset;
2140 assert(EndOffset >= 0 &&
2141 "end of registration object above normal EBP position!");
2143 if (UsedReg == FramePtr) {
2144 // ADD $offset, %ebp
2145 assert(UsedReg == FramePtr);
2146 unsigned ADDri = getADDriOpcode(false, EndOffset);
2147 BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2150 .setMIFlag(MachineInstr::FrameSetup)
2154 assert(UsedReg == BasePtr);
2155 // LEA offset(%ebp), %esi
2156 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2157 FramePtr, false, EndOffset)
2158 .setMIFlag(MachineInstr::FrameSetup);
2159 // MOV32rm SavedEBPOffset(%esi), %ebp
2160 assert(X86FI->getHasSEHFramePtrSave());
2162 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
2163 assert(UsedReg == BasePtr);
2164 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
2165 UsedReg, true, Offset)
2166 .setMIFlag(MachineInstr::FrameSetup);