1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/DataLayout.h"
27 #include "llvm/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
35 // FIXME: completely move here.
36 extern cl::opt<bool> ForceStackAlign;
38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
39 return !MF.getFrameInfo()->hasVarSizedObjects();
42 /// hasFP - Return true if the specified function should have a dedicated frame
43 /// pointer register. This is true if the function has variable sized allocas
44 /// or if frame pointer elimination is disabled.
45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 const MachineModuleInfo &MMI = MF.getMMI();
48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
50 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
51 RegInfo->needsStackRealignment(MF) ||
52 MFI->hasVarSizedObjects() ||
53 MFI->isFrameAddressTaken() ||
54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
55 MMI.callsUnwindInit() || MMI.callsEHReturn());
58 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
62 return X86::SUB64ri32;
70 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
74 return X86::ADD64ri32;
82 static unsigned getLEArOpcode(unsigned is64Bit) {
83 return is64Bit ? X86::LEA64r : X86::LEA32r;
86 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
87 /// when it reaches the "return" instruction. We can then pop a stack object
88 /// to this register without worry about clobbering it.
89 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator &MBBI,
91 const TargetRegisterInfo &TRI,
93 const MachineFunction *MF = MBB.getParent();
94 const Function *F = MF->getFunction();
95 if (!F || MF->getMMI().callsEHReturn())
98 static const uint16_t CallerSavedRegs32Bit[] = {
99 X86::EAX, X86::EDX, X86::ECX, 0
102 static const uint16_t CallerSavedRegs64Bit[] = {
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
107 unsigned Opc = MBBI->getOpcode();
112 case X86::TCRETURNdi:
113 case X86::TCRETURNri:
114 case X86::TCRETURNmi:
115 case X86::TCRETURNdi64:
116 case X86::TCRETURNri64:
117 case X86::TCRETURNmi64:
119 case X86::EH_RETURN64: {
120 SmallSet<uint16_t, 8> Uses;
121 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
122 MachineOperand &MO = MBBI->getOperand(i);
123 if (!MO.isReg() || MO.isDef())
125 unsigned Reg = MO.getReg();
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
134 if (!Uses.count(*CS))
143 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
144 /// stack pointer by a constant value.
146 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
147 unsigned StackPtr, int64_t NumBytes,
148 bool Is64Bit, bool UseLEA,
149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
150 bool isSub = NumBytes < 0;
151 uint64_t Offset = isSub ? -NumBytes : NumBytes;
154 Opc = getLEArOpcode(Is64Bit);
157 ? getSUBriOpcode(Is64Bit, Offset)
158 : getADDriOpcode(Is64Bit, Offset);
160 uint64_t Chunk = (1LL << 31) - 1;
161 DebugLoc DL = MBB.findDebugLoc(MBBI);
164 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
165 if (ThisVal == (Is64Bit ? 8 : 4)) {
166 // Use push / pop instead.
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
177 MI->setFlag(MachineInstr::FrameSetup);
183 MachineInstr *MI = NULL;
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
187 StackPtr, false, isSub ? -ThisVal : ThisVal);
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
192 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
196 MI->setFlag(MachineInstr::FrameSetup);
202 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
204 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
205 unsigned StackPtr, uint64_t *NumBytes = NULL) {
206 if (MBBI == MBB.begin()) return;
208 MachineBasicBlock::iterator PI = prior(MBBI);
209 unsigned Opc = PI->getOpcode();
210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
213 PI->getOperand(0).getReg() == StackPtr) {
215 *NumBytes += PI->getOperand(2).getImm();
217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
219 PI->getOperand(0).getReg() == StackPtr) {
221 *NumBytes -= PI->getOperand(2).getImm();
226 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
228 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator &MBBI,
230 unsigned StackPtr, uint64_t *NumBytes = NULL) {
231 // FIXME: THIS ISN'T RUN!!!
234 if (MBBI == MBB.end()) return;
236 MachineBasicBlock::iterator NI = llvm::next(MBBI);
237 if (NI == MBB.end()) return;
239 unsigned Opc = NI->getOpcode();
240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
242 NI->getOperand(0).getReg() == StackPtr) {
244 *NumBytes -= NI->getOperand(2).getImm();
247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
249 NI->getOperand(0).getReg() == StackPtr) {
251 *NumBytes += NI->getOperand(2).getImm();
257 /// mergeSPUpdates - Checks the instruction before/after the passed
258 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the
259 /// stack adjustment is returned as a positive value for ADD/LEA and a negative for
261 static int mergeSPUpdates(MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator &MBBI,
264 bool doMergeWithPrevious) {
265 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
266 (!doMergeWithPrevious && MBBI == MBB.end()))
269 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
270 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
271 unsigned Opc = PI->getOpcode();
274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
277 PI->getOperand(0).getReg() == StackPtr){
278 Offset += PI->getOperand(2).getImm();
280 if (!doMergeWithPrevious) MBBI = NI;
281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
283 PI->getOperand(0).getReg() == StackPtr) {
284 Offset -= PI->getOperand(2).getImm();
286 if (!doMergeWithPrevious) MBBI = NI;
292 static bool isEAXLiveIn(MachineFunction &MF) {
293 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
294 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL)
305 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
307 unsigned FramePtr) const {
308 MachineFrameInfo *MFI = MF.getFrameInfo();
309 MachineModuleInfo &MMI = MF.getMMI();
311 // Add callee saved registers to move list.
312 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
313 if (CSI.empty()) return;
315 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
316 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
317 bool HasFP = hasFP(MF);
319 // Calculate amount of bytes used for return address storing.
320 int stackGrowth = -RegInfo->getSlotSize();
322 // FIXME: This is dirty hack. The code itself is pretty mess right now.
323 // It should be rewritten from scratch and generalized sometimes.
325 // Determine maximum offset (minimum due to stack growth).
326 int64_t MaxOffset = 0;
327 for (std::vector<CalleeSavedInfo>::const_iterator
328 I = CSI.begin(), E = CSI.end(); I != E; ++I)
329 MaxOffset = std::min(MaxOffset,
330 MFI->getObjectOffset(I->getFrameIdx()));
332 // Calculate offsets.
333 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
334 for (std::vector<CalleeSavedInfo>::const_iterator
335 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
336 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
337 unsigned Reg = I->getReg();
338 Offset = MaxOffset - Offset + saveAreaOffset;
340 // Don't output a new machine move if we're re-saving the frame
341 // pointer. This happens when the PrologEpilogInserter has inserted an extra
342 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
343 // generates one when frame pointers are used. If we generate a "machine
344 // move" for this extra "PUSH", the linker will lose track of the fact that
345 // the frame pointer should have the value of the first "PUSH" when it's
348 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
349 // another bug. I.e., one where we generate a prolog like this:
357 // The immediate re-push of EBP is unnecessary. At the least, it's an
358 // optimization bug. EBP can be used as a scratch register in certain
359 // cases, but probably not when we have a frame pointer.
360 if (HasFP && FramePtr == Reg)
363 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
364 MachineLocation CSSrc(Reg);
365 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
369 /// getCompactUnwindRegNum - Get the compact unwind number for a given
370 /// register. The number corresponds to the enum lists in
371 /// compact_unwind_encoding.h.
372 static int getCompactUnwindRegNum(const uint16_t *CURegs, unsigned Reg) {
373 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
380 // Number of registers that can be saved in a compact unwind encoding.
381 #define CU_NUM_SAVED_REGS 6
383 /// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding
384 /// used with frameless stacks. It is passed the number of registers to be saved
385 /// and an array of the registers saved.
387 encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
388 unsigned RegCount, bool Is64Bit) {
389 // The saved registers are numbered from 1 to 6. In order to encode the order
390 // in which they were saved, we re-number them according to their place in the
391 // register order. The re-numbering is relative to the last re-numbered
392 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
401 static const uint16_t CU32BitRegs[] = {
402 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
404 static const uint16_t CU64BitRegs[] = {
405 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
407 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
409 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
410 int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]);
411 if (CUReg == -1) return ~0U;
412 SavedRegs[i] = CUReg;
416 std::swap(SavedRegs[0], SavedRegs[5]);
417 std::swap(SavedRegs[1], SavedRegs[4]);
418 std::swap(SavedRegs[2], SavedRegs[3]);
420 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
421 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i) {
422 unsigned Countless = 0;
423 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
424 if (SavedRegs[j] < SavedRegs[i])
427 RenumRegs[i] = SavedRegs[i] - Countless - 1;
430 // Take the renumbered values and encode them into a 10-bit number.
431 uint32_t permutationEncoding = 0;
434 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
435 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
439 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
440 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
444 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
445 + 3 * RenumRegs[4] + RenumRegs[5];
448 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
452 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
455 permutationEncoding |= RenumRegs[5];
459 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
460 "Invalid compact register encoding!");
461 return permutationEncoding;
464 /// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a
465 /// compact encoding with a frame pointer.
467 encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
469 static const uint16_t CU32BitRegs[] = {
470 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
472 static const uint16_t CU64BitRegs[] = {
473 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
475 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
477 // Encode the registers in the order they were saved, 3-bits per register. The
478 // registers are numbered from 1 to CU_NUM_SAVED_REGS.
480 for (int I = CU_NUM_SAVED_REGS - 1, Idx = 0; I != -1; --I) {
481 unsigned Reg = SavedRegs[I];
482 if (Reg == 0) continue;
484 int CURegNum = getCompactUnwindRegNum(CURegs, Reg);
485 if (CURegNum == -1) return ~0U;
487 // Encode the 3-bit register number in order, skipping over 3-bits for each
489 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
492 assert((RegEnc & 0x3FFFF) == RegEnc && "Invalid compact register encoding!");
496 uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const {
497 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
498 unsigned FramePtr = RegInfo->getFrameRegister(MF);
499 unsigned StackPtr = RegInfo->getStackRegister();
501 bool Is64Bit = STI.is64Bit();
502 bool HasFP = hasFP(MF);
504 unsigned SavedRegs[CU_NUM_SAVED_REGS] = { 0, 0, 0, 0, 0, 0 };
505 unsigned SavedRegIdx = 0;
507 unsigned OffsetSize = (Is64Bit ? 8 : 4);
509 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
510 unsigned PushInstrSize = 1;
511 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
512 unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
513 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
515 unsigned StackDivide = (Is64Bit ? 8 : 4);
517 unsigned InstrOffset = 0;
518 unsigned StackAdjust = 0;
519 unsigned StackSize = 0;
521 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB.
522 bool ExpectEnd = false;
523 for (MachineBasicBlock::iterator
524 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) {
525 MachineInstr &MI = *MBBI;
526 unsigned Opc = MI.getOpcode();
527 if (Opc == X86::PROLOG_LABEL) continue;
528 if (!MI.getFlag(MachineInstr::FrameSetup)) break;
530 // We don't exect any more prolog instructions.
531 if (ExpectEnd) return 0;
533 if (Opc == PushInstr) {
534 // If there are too many saved registers, we cannot use compact encoding.
535 if (SavedRegIdx >= CU_NUM_SAVED_REGS) return 0;
537 SavedRegs[SavedRegIdx++] = MI.getOperand(0).getReg();
538 StackAdjust += OffsetSize;
539 InstrOffset += PushInstrSize;
540 } else if (Opc == MoveInstr) {
541 unsigned SrcReg = MI.getOperand(1).getReg();
542 unsigned DstReg = MI.getOperand(0).getReg();
544 if (DstReg != FramePtr || SrcReg != StackPtr)
548 memset(SavedRegs, 0, sizeof(SavedRegs));
550 InstrOffset += MoveInstrSize;
551 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
552 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
554 // We already have a stack size.
557 if (!MI.getOperand(0).isReg() ||
558 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() ||
559 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm())
560 // We need this to be a stack adjustment pointer. Something like:
562 // %RSP<def> = SUB64ri8 %RSP, 48
565 StackSize = MI.getOperand(2).getImm() / StackDivide;
566 SubtractInstrIdx += InstrOffset;
571 // Encode that we are using EBP/RBP as the frame pointer.
572 uint32_t CompactUnwindEncoding = 0;
573 StackAdjust /= StackDivide;
575 if ((StackAdjust & 0xFF) != StackAdjust)
576 // Offset was too big for compact encoding.
579 // Get the encoding of the saved registers when we have a frame pointer.
580 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
581 if (RegEnc == ~0U) return 0;
583 CompactUnwindEncoding |= 0x01000000;
584 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
585 CompactUnwindEncoding |= RegEnc & 0x7FFF;
588 uint32_t TotalStackSize = StackAdjust + StackSize;
589 if ((TotalStackSize & 0xFF) == TotalStackSize) {
590 // Frameless stack with a small stack size.
591 CompactUnwindEncoding |= 0x02000000;
593 // Encode the stack size.
594 CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16;
596 if ((StackAdjust & 0x7) != StackAdjust)
597 // The extra stack adjustments are too big for us to handle.
600 // Frameless stack with an offset too large for us to encode compactly.
601 CompactUnwindEncoding |= 0x03000000;
603 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
605 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
607 // Encode any extra stack stack adjustments (done via push instructions).
608 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
611 // Encode the number of registers saved.
612 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
614 // Get the encoding of the saved registers when we don't have a frame
617 encodeCompactUnwindRegistersWithoutFrame(SavedRegs, SavedRegIdx,
619 if (RegEnc == ~0U) return 0;
621 // Encode the register encoding.
622 CompactUnwindEncoding |= RegEnc & 0x3FF;
625 return CompactUnwindEncoding;
628 /// emitPrologue - Push callee-saved registers onto the stack, which
629 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
630 /// space for local variables. Also emit labels used by the exception handler to
631 /// generate the exception handling frames.
632 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
633 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
634 MachineBasicBlock::iterator MBBI = MBB.begin();
635 MachineFrameInfo *MFI = MF.getFrameInfo();
636 const Function *Fn = MF.getFunction();
637 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
638 const X86InstrInfo &TII = *TM.getInstrInfo();
639 MachineModuleInfo &MMI = MF.getMMI();
640 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
641 bool needsFrameMoves = MMI.hasDebugInfo() ||
642 Fn->needsUnwindTableEntry();
643 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
644 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
645 bool HasFP = hasFP(MF);
646 bool Is64Bit = STI.is64Bit();
647 bool IsWin64 = STI.isTargetWin64();
648 bool UseLEA = STI.useLeaForSP();
649 unsigned StackAlign = getStackAlignment();
650 unsigned SlotSize = RegInfo->getSlotSize();
651 unsigned FramePtr = RegInfo->getFrameRegister(MF);
652 unsigned StackPtr = RegInfo->getStackRegister();
653 unsigned BasePtr = RegInfo->getBaseRegister();
656 // If we're forcing a stack realignment we can't rely on just the frame
657 // info, we need to know the ABI stack alignment as well in case we
658 // have a call out. Otherwise just make sure we have some alignment - we'll
659 // go with the minimum SlotSize.
660 if (ForceStackAlign) {
662 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
663 else if (MaxAlign < SlotSize)
667 // Add RETADDR move area to callee saved frame size.
668 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
669 if (TailCallReturnAddrDelta < 0)
670 X86FI->setCalleeSavedFrameSize(
671 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
673 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
674 // function, and use up to 128 bytes of stack space, don't have a frame
675 // pointer, calls, or dynamic alloca then we do not need to adjust the
676 // stack pointer (we fit in the Red Zone).
677 if (Is64Bit && !Fn->getFnAttributes().hasAttribute(Attribute::NoRedZone) &&
678 !RegInfo->needsStackRealignment(MF) &&
679 !MFI->hasVarSizedObjects() && // No dynamic alloca.
680 !MFI->adjustsStack() && // No calls.
681 !IsWin64 && // Win64 has no Red Zone
682 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack
683 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
684 if (HasFP) MinSize += SlotSize;
685 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
686 MFI->setStackSize(StackSize);
689 // Insert stack pointer adjustment for later moving of return addr. Only
690 // applies to tail call optimized functions where the callee argument stack
691 // size is bigger than the callers.
692 if (TailCallReturnAddrDelta < 0) {
694 BuildMI(MBB, MBBI, DL,
695 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
698 .addImm(-TailCallReturnAddrDelta)
699 .setMIFlag(MachineInstr::FrameSetup);
700 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
703 // Mapping for machine moves:
705 // DST: VirtualFP AND
706 // SRC: VirtualFP => DW_CFA_def_cfa_offset
707 // ELSE => DW_CFA_def_cfa
709 // SRC: VirtualFP AND
710 // DST: Register => DW_CFA_def_cfa_register
713 // OFFSET < 0 => DW_CFA_offset_extended_sf
714 // REG < 64 => DW_CFA_offset + Reg
715 // ELSE => DW_CFA_offset_extended
717 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
718 uint64_t NumBytes = 0;
719 int stackGrowth = -SlotSize;
722 // Calculate required stack adjustment.
723 uint64_t FrameSize = StackSize - SlotSize;
724 if (RegInfo->needsStackRealignment(MF)) {
725 // Callee-saved registers are pushed on stack before the stack
727 FrameSize -= X86FI->getCalleeSavedFrameSize();
728 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
730 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
733 // Get the offset of the stack slot for the EBP register, which is
734 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
735 // Update the frame offset adjustment.
736 MFI->setOffsetAdjustment(-NumBytes);
738 // Save EBP/RBP into the appropriate stack slot.
739 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
740 .addReg(FramePtr, RegState::Kill)
741 .setMIFlag(MachineInstr::FrameSetup);
743 if (needsFrameMoves) {
744 // Mark the place where EBP/RBP was saved.
745 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
746 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
749 // Define the current CFA rule to use the provided offset.
751 MachineLocation SPDst(MachineLocation::VirtualFP);
752 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
753 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
755 MachineLocation SPDst(StackPtr);
756 MachineLocation SPSrc(StackPtr, stackGrowth);
757 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
760 // Change the rule for the FramePtr to be an "offset" rule.
761 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
762 MachineLocation FPSrc(FramePtr);
763 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
766 // Update EBP with the new base value.
767 BuildMI(MBB, MBBI, DL,
768 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
770 .setMIFlag(MachineInstr::FrameSetup);
772 if (needsFrameMoves) {
773 // Mark effective beginning of when frame pointer becomes valid.
774 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
775 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
778 // Define the current CFA to use the EBP/RBP register.
779 MachineLocation FPDst(FramePtr);
780 MachineLocation FPSrc(MachineLocation::VirtualFP);
781 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
784 // Mark the FramePtr as live-in in every block except the entry.
785 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
787 I->addLiveIn(FramePtr);
789 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
792 // Skip the callee-saved push instructions.
793 bool PushedRegs = false;
794 int StackOffset = 2 * stackGrowth;
796 while (MBBI != MBB.end() &&
797 (MBBI->getOpcode() == X86::PUSH32r ||
798 MBBI->getOpcode() == X86::PUSH64r)) {
800 MBBI->setFlag(MachineInstr::FrameSetup);
803 if (!HasFP && needsFrameMoves) {
804 // Mark callee-saved push instruction.
805 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
806 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
808 // Define the current CFA rule to use the provided offset.
809 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr;
810 MachineLocation SPDst(Ptr);
811 MachineLocation SPSrc(Ptr, StackOffset);
812 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
813 StackOffset += stackGrowth;
817 // Realign stack after we pushed callee-saved registers (so that we'll be
818 // able to calculate their offsets from the frame pointer).
820 // NOTE: We push the registers before realigning the stack, so
821 // vector callee-saved (xmm) registers may be saved w/o proper
822 // alignment in this way. However, currently these regs are saved in
823 // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so
824 // this shouldn't be a problem.
825 if (RegInfo->needsStackRealignment(MF)) {
826 assert(HasFP && "There should be a frame pointer if stack is realigned.");
828 BuildMI(MBB, MBBI, DL,
829 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
832 .setMIFlag(MachineInstr::FrameSetup);
834 // The EFLAGS implicit def is dead.
835 MI->getOperand(3).setIsDead();
838 // If there is an SUB32ri of ESP immediately before this instruction, merge
839 // the two. This can be the case when tail call elimination is enabled and
840 // the callee has more arguments then the caller.
841 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
843 // If there is an ADD32ri or SUB32ri of ESP immediately after this
844 // instruction, merge the two instructions.
845 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
847 // Adjust stack pointer: ESP -= numbytes.
849 // Windows and cygwin/mingw require a prologue helper routine when allocating
850 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
851 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
852 // stack and adjust the stack pointer in one go. The 64-bit version of
853 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
854 // responsible for adjusting the stack pointer. Touching the stack at 4K
855 // increments is necessary to ensure that the guard pages used by the OS
856 // virtual memory manager are allocated in correct sequence.
857 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) {
858 const char *StackProbeSymbol;
859 bool isSPUpdateNeeded = false;
862 if (STI.isTargetCygMing())
863 StackProbeSymbol = "___chkstk";
865 StackProbeSymbol = "__chkstk";
866 isSPUpdateNeeded = true;
868 } else if (STI.isTargetCygMing())
869 StackProbeSymbol = "_alloca";
871 StackProbeSymbol = "_chkstk";
873 // Check whether EAX is livein for this function.
874 bool isEAXAlive = isEAXLiveIn(MF);
877 // Sanity check that EAX is not livein for this function.
878 // It should not be, so throw an assert.
879 assert(!Is64Bit && "EAX is livein in x64 case!");
882 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
883 .addReg(X86::EAX, RegState::Kill)
884 .setMIFlag(MachineInstr::FrameSetup);
888 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
889 // Function prologue is responsible for adjusting the stack pointer.
890 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
892 .setMIFlag(MachineInstr::FrameSetup);
894 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
895 // We'll also use 4 already allocated bytes for EAX.
896 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
897 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
898 .setMIFlag(MachineInstr::FrameSetup);
901 BuildMI(MBB, MBBI, DL,
902 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
903 .addExternalSymbol(StackProbeSymbol)
904 .addReg(StackPtr, RegState::Define | RegState::Implicit)
905 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
906 .setMIFlag(MachineInstr::FrameSetup);
908 // MSVC x64's __chkstk needs to adjust %rsp.
909 // FIXME: %rax preserves the offset and should be available.
910 if (isSPUpdateNeeded)
911 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
912 UseLEA, TII, *RegInfo);
916 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
918 StackPtr, false, NumBytes - 4);
919 MI->setFlag(MachineInstr::FrameSetup);
920 MBB.insert(MBBI, MI);
923 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
924 UseLEA, TII, *RegInfo);
926 // If we need a base pointer, set it up here. It's whatever the value
927 // of the stack pointer is at this point. Any variable size objects
928 // will be allocated after this, so we can still use the base pointer
929 // to reference locals.
930 if (RegInfo->hasBasePointer(MF)) {
931 // Update the frame pointer with the current stack pointer.
932 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
933 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
935 .setMIFlag(MachineInstr::FrameSetup);
938 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
939 // Mark end of stack pointer adjustment.
940 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
941 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
944 if (!HasFP && NumBytes) {
945 // Define the current CFA rule to use the provided offset.
947 MachineLocation SPDst(MachineLocation::VirtualFP);
948 MachineLocation SPSrc(MachineLocation::VirtualFP,
949 -StackSize + stackGrowth);
950 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
952 MachineLocation SPDst(StackPtr);
953 MachineLocation SPSrc(StackPtr, stackGrowth);
954 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
958 // Emit DWARF info specifying the offsets of the callee-saved registers.
960 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
963 // Darwin 10.7 and greater has support for compact unwind encoding.
964 if (STI.getTargetTriple().isMacOSX() &&
965 !STI.getTargetTriple().isMacOSXVersionLT(10, 7))
966 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
969 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
970 MachineBasicBlock &MBB) const {
971 const MachineFrameInfo *MFI = MF.getFrameInfo();
972 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
973 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
974 const X86InstrInfo &TII = *TM.getInstrInfo();
975 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
976 assert(MBBI != MBB.end() && "Returning block has no instructions");
977 unsigned RetOpcode = MBBI->getOpcode();
978 DebugLoc DL = MBBI->getDebugLoc();
979 bool Is64Bit = STI.is64Bit();
980 bool UseLEA = STI.useLeaForSP();
981 unsigned StackAlign = getStackAlignment();
982 unsigned SlotSize = RegInfo->getSlotSize();
983 unsigned FramePtr = RegInfo->getFrameRegister(MF);
984 unsigned StackPtr = RegInfo->getStackRegister();
988 llvm_unreachable("Can only insert epilog into returning blocks");
991 case X86::TCRETURNdi:
992 case X86::TCRETURNri:
993 case X86::TCRETURNmi:
994 case X86::TCRETURNdi64:
995 case X86::TCRETURNri64:
996 case X86::TCRETURNmi64:
998 case X86::EH_RETURN64:
999 break; // These are ok
1002 // Get the number of bytes to allocate from the FrameInfo.
1003 uint64_t StackSize = MFI->getStackSize();
1004 uint64_t MaxAlign = MFI->getMaxAlignment();
1005 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1006 uint64_t NumBytes = 0;
1008 // If we're forcing a stack realignment we can't rely on just the frame
1009 // info, we need to know the ABI stack alignment as well in case we
1010 // have a call out. Otherwise just make sure we have some alignment - we'll
1011 // go with the minimum.
1012 if (ForceStackAlign) {
1013 if (MFI->hasCalls())
1014 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1016 MaxAlign = MaxAlign ? MaxAlign : 4;
1020 // Calculate required stack adjustment.
1021 uint64_t FrameSize = StackSize - SlotSize;
1022 if (RegInfo->needsStackRealignment(MF)) {
1023 // Callee-saved registers were pushed on stack before the stack
1025 FrameSize -= CSSize;
1026 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
1028 NumBytes = FrameSize - CSSize;
1032 BuildMI(MBB, MBBI, DL,
1033 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1035 NumBytes = StackSize - CSSize;
1038 // Skip the callee-saved pop instructions.
1039 while (MBBI != MBB.begin()) {
1040 MachineBasicBlock::iterator PI = prior(MBBI);
1041 unsigned Opc = PI->getOpcode();
1043 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1044 !PI->isTerminator())
1049 MachineBasicBlock::iterator FirstCSPop = MBBI;
1051 DL = MBBI->getDebugLoc();
1053 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1054 // instruction, merge the two instructions.
1055 if (NumBytes || MFI->hasVarSizedObjects())
1056 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1058 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1059 // slot before popping them off! Same applies for the case, when stack was
1061 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1062 if (RegInfo->needsStackRealignment(MF))
1065 unsigned Opc = getLEArOpcode(Is64Bit);
1066 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1067 FramePtr, false, -CSSize);
1069 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1070 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1073 } else if (NumBytes) {
1074 // Adjust stack pointer back: ESP += numbytes.
1075 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, UseLEA, TII, *RegInfo);
1078 // We're returning from function via eh_return.
1079 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1080 MBBI = MBB.getLastNonDebugInstr();
1081 MachineOperand &DestAddr = MBBI->getOperand(0);
1082 assert(DestAddr.isReg() && "Offset should be in register!");
1083 BuildMI(MBB, MBBI, DL,
1084 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1085 StackPtr).addReg(DestAddr.getReg());
1086 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1087 RetOpcode == X86::TCRETURNmi ||
1088 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1089 RetOpcode == X86::TCRETURNmi64) {
1090 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1091 // Tail call return: adjust the stack pointer and jump to callee.
1092 MBBI = MBB.getLastNonDebugInstr();
1093 MachineOperand &JumpTarget = MBBI->getOperand(0);
1094 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1095 assert(StackAdjust.isImm() && "Expecting immediate value.");
1097 // Adjust stack pointer.
1098 int StackAdj = StackAdjust.getImm();
1099 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1101 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1103 // Incoporate the retaddr area.
1104 Offset = StackAdj-MaxTCDelta;
1105 assert(Offset >= 0 && "Offset should never be negative");
1108 // Check for possible merge with preceding ADD instruction.
1109 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1110 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, UseLEA, TII, *RegInfo);
1113 // Jump to label or value in register.
1114 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1115 MachineInstrBuilder MIB =
1116 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1117 ? X86::TAILJMPd : X86::TAILJMPd64));
1118 if (JumpTarget.isGlobal())
1119 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1120 JumpTarget.getTargetFlags());
1122 assert(JumpTarget.isSymbol());
1123 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1124 JumpTarget.getTargetFlags());
1126 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1127 MachineInstrBuilder MIB =
1128 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1129 ? X86::TAILJMPm : X86::TAILJMPm64));
1130 for (unsigned i = 0; i != 5; ++i)
1131 MIB.addOperand(MBBI->getOperand(i));
1132 } else if (RetOpcode == X86::TCRETURNri64) {
1133 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1134 addReg(JumpTarget.getReg(), RegState::Kill);
1136 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1137 addReg(JumpTarget.getReg(), RegState::Kill);
1140 MachineInstr *NewMI = prior(MBBI);
1141 NewMI->copyImplicitOps(MF, MBBI);
1143 // Delete the pseudo instruction TCRETURN.
1145 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1146 (X86FI->getTCReturnAddrDelta() < 0)) {
1147 // Add the return addr area delta back since we are not tail calling.
1148 int delta = -1*X86FI->getTCReturnAddrDelta();
1149 MBBI = MBB.getLastNonDebugInstr();
1151 // Check for possible merge with preceding ADD instruction.
1152 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1153 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, UseLEA, TII, *RegInfo);
1157 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
1158 const X86RegisterInfo *RegInfo =
1159 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1160 const MachineFrameInfo *MFI = MF.getFrameInfo();
1161 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1162 uint64_t StackSize = MFI->getStackSize();
1164 if (RegInfo->hasBasePointer(MF)) {
1165 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1167 // Skip the saved EBP.
1168 return Offset + RegInfo->getSlotSize();
1170 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1171 return Offset + StackSize;
1173 } else if (RegInfo->needsStackRealignment(MF)) {
1175 // Skip the saved EBP.
1176 return Offset + RegInfo->getSlotSize();
1178 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1179 return Offset + StackSize;
1181 // FIXME: Support tail calls
1184 return Offset + StackSize;
1186 // Skip the saved EBP.
1187 Offset += RegInfo->getSlotSize();
1189 // Skip the RETADDR move area
1190 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1191 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1192 if (TailCallReturnAddrDelta < 0)
1193 Offset -= TailCallReturnAddrDelta;
1199 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1200 unsigned &FrameReg) const {
1201 const X86RegisterInfo *RegInfo =
1202 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1203 // We can't calculate offset from frame pointer if the stack is realigned,
1204 // so enforce usage of stack/base pointer. The base pointer is used when we
1205 // have dynamic allocas in addition to dynamic realignment.
1206 if (RegInfo->hasBasePointer(MF))
1207 FrameReg = RegInfo->getBaseRegister();
1208 else if (RegInfo->needsStackRealignment(MF))
1209 FrameReg = RegInfo->getStackRegister();
1211 FrameReg = RegInfo->getFrameRegister(MF);
1212 return getFrameIndexOffset(MF, FI);
1215 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1216 MachineBasicBlock::iterator MI,
1217 const std::vector<CalleeSavedInfo> &CSI,
1218 const TargetRegisterInfo *TRI) const {
1222 DebugLoc DL = MBB.findDebugLoc(MI);
1224 MachineFunction &MF = *MBB.getParent();
1226 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
1227 unsigned FPReg = TRI->getFrameRegister(MF);
1228 unsigned CalleeFrameSize = 0;
1230 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1231 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1233 // Push GPRs. It increases frame size.
1234 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1235 for (unsigned i = CSI.size(); i != 0; --i) {
1236 unsigned Reg = CSI[i-1].getReg();
1237 if (!X86::GR64RegClass.contains(Reg) &&
1238 !X86::GR32RegClass.contains(Reg))
1240 // Add the callee-saved register as live-in. It's killed at the spill.
1243 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
1245 CalleeFrameSize += SlotSize;
1246 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1247 .setMIFlag(MachineInstr::FrameSetup);
1250 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
1252 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1253 // It can be done by spilling XMMs to stack frame.
1254 // Note that only Win64 ABI might spill XMMs.
1255 for (unsigned i = CSI.size(); i != 0; --i) {
1256 unsigned Reg = CSI[i-1].getReg();
1257 if (X86::GR64RegClass.contains(Reg) ||
1258 X86::GR32RegClass.contains(Reg))
1260 // Add the callee-saved register as live-in. It's killed at the spill.
1262 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1263 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1270 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1271 MachineBasicBlock::iterator MI,
1272 const std::vector<CalleeSavedInfo> &CSI,
1273 const TargetRegisterInfo *TRI) const {
1277 DebugLoc DL = MBB.findDebugLoc(MI);
1279 MachineFunction &MF = *MBB.getParent();
1280 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1282 // Reload XMMs from stack frame.
1283 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1284 unsigned Reg = CSI[i].getReg();
1285 if (X86::GR64RegClass.contains(Reg) ||
1286 X86::GR32RegClass.contains(Reg))
1288 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1289 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1294 unsigned FPReg = TRI->getFrameRegister(MF);
1295 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1296 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1297 unsigned Reg = CSI[i].getReg();
1298 if (!X86::GR64RegClass.contains(Reg) &&
1299 !X86::GR32RegClass.contains(Reg))
1302 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
1304 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1310 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1311 RegScavenger *RS) const {
1312 MachineFrameInfo *MFI = MF.getFrameInfo();
1313 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
1314 unsigned SlotSize = RegInfo->getSlotSize();
1316 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1317 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1319 if (TailCallReturnAddrDelta < 0) {
1320 // create RETURNADDR area
1329 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1330 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
1334 assert((TailCallReturnAddrDelta <= 0) &&
1335 "The Delta should always be zero or negative");
1336 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
1338 // Create a frame entry for the EBP register that must be saved.
1339 int FrameIdx = MFI->CreateFixedObject(SlotSize,
1341 TFI.getOffsetOfLocalArea() +
1342 TailCallReturnAddrDelta,
1344 assert(FrameIdx == MFI->getObjectIndexBegin() &&
1345 "Slot for EBP register must be last in order to be found!");
1349 // Spill the BasePtr if it's used.
1350 if (RegInfo->hasBasePointer(MF))
1351 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1355 HasNestArgument(const MachineFunction *MF) {
1356 const Function *F = MF->getFunction();
1357 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1359 if (I->hasNestAttr())
1366 /// GetScratchRegister - Get a register for performing work in the segmented
1367 /// stack prologue. Depending on platform and the properties of the function
1368 /// either one or two registers will be needed. Set primary to true for
1369 /// the first register, false for the second.
1371 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1373 return Primary ? X86::R11 : X86::R12;
1375 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1376 bool IsNested = HasNestArgument(&MF);
1378 if (CallingConvention == CallingConv::X86_FastCall ||
1379 CallingConvention == CallingConv::Fast) {
1381 report_fatal_error("Segmented stacks does not support fastcall with "
1382 "nested function.");
1383 return Primary ? X86::EAX : X86::ECX;
1386 return Primary ? X86::EDX : X86::EAX;
1387 return Primary ? X86::ECX : X86::EAX;
1390 // The stack limit in the TCB is set to this many bytes above the actual stack
1392 static const uint64_t kSplitStackAvailable = 256;
1395 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1396 MachineBasicBlock &prologueMBB = MF.front();
1397 MachineFrameInfo *MFI = MF.getFrameInfo();
1398 const X86InstrInfo &TII = *TM.getInstrInfo();
1400 bool Is64Bit = STI.is64Bit();
1401 unsigned TlsReg, TlsOffset;
1403 const X86Subtarget *ST = &MF.getTarget().getSubtarget<X86Subtarget>();
1405 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1406 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1407 "Scratch register is live-in");
1409 if (MF.getFunction()->isVarArg())
1410 report_fatal_error("Segmented stacks do not support vararg functions.");
1411 if (!ST->isTargetLinux() && !ST->isTargetDarwin() &&
1412 !ST->isTargetWin32() && !ST->isTargetFreeBSD())
1413 report_fatal_error("Segmented stacks not supported on this platform.");
1415 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1416 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1417 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1418 bool IsNested = false;
1420 // We need to know if the function has a nest argument only in 64 bit mode.
1422 IsNested = HasNestArgument(&MF);
1424 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1425 // allocMBB needs to be last (terminating) instruction.
1427 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1428 e = prologueMBB.livein_end(); i != e; i++) {
1429 allocMBB->addLiveIn(*i);
1430 checkMBB->addLiveIn(*i);
1434 allocMBB->addLiveIn(X86::R10);
1436 MF.push_front(allocMBB);
1437 MF.push_front(checkMBB);
1439 // Eventually StackSize will be calculated by a link-time pass; which will
1440 // also decide whether checking code needs to be injected into this particular
1442 StackSize = MFI->getStackSize();
1444 // When the frame size is less than 256 we just compare the stack
1445 // boundary directly to the value of the stack pointer, per gcc.
1446 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1448 // Read the limit off the current stacklet off the stack_guard location.
1450 if (ST->isTargetLinux()) {
1453 } else if (ST->isTargetDarwin()) {
1455 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1456 } else if (ST->isTargetFreeBSD()) {
1460 report_fatal_error("Segmented stacks not supported on this platform.");
1463 if (CompareStackPointer)
1464 ScratchReg = X86::RSP;
1466 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1467 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1469 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1470 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1472 if (ST->isTargetLinux()) {
1475 } else if (ST->isTargetDarwin()) {
1477 TlsOffset = 0x48 + 90*4;
1478 } else if (ST->isTargetWin32()) {
1480 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1481 } else if (ST->isTargetFreeBSD()) {
1482 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1484 report_fatal_error("Segmented stacks not supported on this platform.");
1487 if (CompareStackPointer)
1488 ScratchReg = X86::ESP;
1490 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1491 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1493 if (ST->isTargetLinux() || ST->isTargetWin32()) {
1494 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1495 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1496 } else if (ST->isTargetDarwin()) {
1498 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
1499 unsigned ScratchReg2;
1501 if (CompareStackPointer) {
1502 // The primary scratch register is available for holding the TLS offset
1503 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1504 SaveScratch2 = false;
1506 // Need to use a second register to hold the TLS offset
1507 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1509 // Unfortunately, with fastcc the second scratch register may hold an arg
1510 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1513 // If Scratch2 is live-in then it needs to be saved
1514 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1515 "Scratch register is live-in and not saved");
1518 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1519 .addReg(ScratchReg2, RegState::Kill);
1521 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1523 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1525 .addReg(ScratchReg2).addImm(1).addReg(0)
1530 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1534 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1535 // It jumps to normal execution of the function body.
1536 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1538 // On 32 bit we first push the arguments size and then the frame size. On 64
1539 // bit, we pass the stack frame size in r10 and the argument size in r11.
1541 // Functions with nested arguments use R10, so it needs to be saved across
1542 // the call to _morestack
1545 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1547 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1549 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1550 .addImm(X86FI->getArgumentStackSize());
1551 MF.getRegInfo().setPhysRegUsed(X86::R10);
1552 MF.getRegInfo().setPhysRegUsed(X86::R11);
1554 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1555 .addImm(X86FI->getArgumentStackSize());
1556 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1560 // __morestack is in libgcc
1562 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1563 .addExternalSymbol("__morestack");
1565 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1566 .addExternalSymbol("__morestack");
1569 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1571 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1573 allocMBB->addSuccessor(&prologueMBB);
1575 checkMBB->addSuccessor(allocMBB);
1576 checkMBB->addSuccessor(&prologueMBB);