1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/ADT/SmallSet.h"
35 // FIXME: completely move here.
36 extern cl::opt<bool> ForceStackAlign;
38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
39 return !MF.getFrameInfo()->hasVarSizedObjects();
42 /// hasFP - Return true if the specified function should have a dedicated frame
43 /// pointer register. This is true if the function has variable sized allocas
44 /// or if frame pointer elimination is disabled.
45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 const MachineModuleInfo &MMI = MF.getMMI();
48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
50 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
51 RegInfo->needsStackRealignment(MF) ||
52 MFI->hasVarSizedObjects() ||
53 MFI->isFrameAddressTaken() ||
54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
55 MMI.callsUnwindInit() || MMI.callsEHReturn());
58 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
62 return X86::SUB64ri32;
70 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
74 return X86::ADD64ri32;
82 static unsigned getLEArOpcode(unsigned is64Bit) {
83 return is64Bit ? X86::LEA64r : X86::LEA32r;
86 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
87 /// when it reaches the "return" instruction. We can then pop a stack object
88 /// to this register without worry about clobbering it.
89 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator &MBBI,
91 const TargetRegisterInfo &TRI,
93 const MachineFunction *MF = MBB.getParent();
94 const Function *F = MF->getFunction();
95 if (!F || MF->getMMI().callsEHReturn())
98 static const uint16_t CallerSavedRegs32Bit[] = {
99 X86::EAX, X86::EDX, X86::ECX, 0
102 static const uint16_t CallerSavedRegs64Bit[] = {
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
107 unsigned Opc = MBBI->getOpcode();
112 case X86::TCRETURNdi:
113 case X86::TCRETURNri:
114 case X86::TCRETURNmi:
115 case X86::TCRETURNdi64:
116 case X86::TCRETURNri64:
117 case X86::TCRETURNmi64:
119 case X86::EH_RETURN64: {
120 SmallSet<uint16_t, 8> Uses;
121 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
122 MachineOperand &MO = MBBI->getOperand(i);
123 if (!MO.isReg() || MO.isDef())
125 unsigned Reg = MO.getReg();
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
134 if (!Uses.count(*CS))
143 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
144 /// stack pointer by a constant value.
146 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
147 unsigned StackPtr, int64_t NumBytes,
148 bool Is64Bit, bool UseLEA,
149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
150 bool isSub = NumBytes < 0;
151 uint64_t Offset = isSub ? -NumBytes : NumBytes;
154 Opc = getLEArOpcode(Is64Bit);
157 ? getSUBriOpcode(Is64Bit, Offset)
158 : getADDriOpcode(Is64Bit, Offset);
160 uint64_t Chunk = (1LL << 31) - 1;
161 DebugLoc DL = MBB.findDebugLoc(MBBI);
164 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
165 if (ThisVal == (Is64Bit ? 8 : 4)) {
166 // Use push / pop instead.
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
177 MI->setFlag(MachineInstr::FrameSetup);
183 MachineInstr *MI = NULL;
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
187 StackPtr, false, isSub ? -ThisVal : ThisVal);
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
192 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
196 MI->setFlag(MachineInstr::FrameSetup);
202 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
204 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
205 unsigned StackPtr, uint64_t *NumBytes = NULL) {
206 if (MBBI == MBB.begin()) return;
208 MachineBasicBlock::iterator PI = prior(MBBI);
209 unsigned Opc = PI->getOpcode();
210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
213 PI->getOperand(0).getReg() == StackPtr) {
215 *NumBytes += PI->getOperand(2).getImm();
217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
219 PI->getOperand(0).getReg() == StackPtr) {
221 *NumBytes -= PI->getOperand(2).getImm();
226 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
228 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator &MBBI,
230 unsigned StackPtr, uint64_t *NumBytes = NULL) {
231 // FIXME: THIS ISN'T RUN!!!
234 if (MBBI == MBB.end()) return;
236 MachineBasicBlock::iterator NI = llvm::next(MBBI);
237 if (NI == MBB.end()) return;
239 unsigned Opc = NI->getOpcode();
240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
242 NI->getOperand(0).getReg() == StackPtr) {
244 *NumBytes -= NI->getOperand(2).getImm();
247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
249 NI->getOperand(0).getReg() == StackPtr) {
251 *NumBytes += NI->getOperand(2).getImm();
257 /// mergeSPUpdates - Checks the instruction before/after the passed
258 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the
259 /// stack adjustment is returned as a positive value for ADD/LEA and a negative for
261 static int mergeSPUpdates(MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator &MBBI,
264 bool doMergeWithPrevious) {
265 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
266 (!doMergeWithPrevious && MBBI == MBB.end()))
269 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
270 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
271 unsigned Opc = PI->getOpcode();
274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
277 PI->getOperand(0).getReg() == StackPtr){
278 Offset += PI->getOperand(2).getImm();
280 if (!doMergeWithPrevious) MBBI = NI;
281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
283 PI->getOperand(0).getReg() == StackPtr) {
284 Offset -= PI->getOperand(2).getImm();
286 if (!doMergeWithPrevious) MBBI = NI;
292 static bool isEAXLiveIn(MachineFunction &MF) {
293 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
294 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL)
305 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
307 unsigned FramePtr) const {
308 MachineFrameInfo *MFI = MF.getFrameInfo();
309 MachineModuleInfo &MMI = MF.getMMI();
311 // Add callee saved registers to move list.
312 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
313 if (CSI.empty()) return;
315 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
316 const TargetData *TD = TM.getTargetData();
317 bool HasFP = hasFP(MF);
319 // Calculate amount of bytes used for return address storing.
320 int stackGrowth = -TD->getPointerSize();
322 // FIXME: This is dirty hack. The code itself is pretty mess right now.
323 // It should be rewritten from scratch and generalized sometimes.
325 // Determine maximum offset (minimum due to stack growth).
326 int64_t MaxOffset = 0;
327 for (std::vector<CalleeSavedInfo>::const_iterator
328 I = CSI.begin(), E = CSI.end(); I != E; ++I)
329 MaxOffset = std::min(MaxOffset,
330 MFI->getObjectOffset(I->getFrameIdx()));
332 // Calculate offsets.
333 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
334 for (std::vector<CalleeSavedInfo>::const_iterator
335 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
336 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
337 unsigned Reg = I->getReg();
338 Offset = MaxOffset - Offset + saveAreaOffset;
340 // Don't output a new machine move if we're re-saving the frame
341 // pointer. This happens when the PrologEpilogInserter has inserted an extra
342 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
343 // generates one when frame pointers are used. If we generate a "machine
344 // move" for this extra "PUSH", the linker will lose track of the fact that
345 // the frame pointer should have the value of the first "PUSH" when it's
348 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
349 // another bug. I.e., one where we generate a prolog like this:
357 // The immediate re-push of EBP is unnecessary. At the least, it's an
358 // optimization bug. EBP can be used as a scratch register in certain
359 // cases, but probably not when we have a frame pointer.
360 if (HasFP && FramePtr == Reg)
363 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
364 MachineLocation CSSrc(Reg);
365 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
369 /// getCompactUnwindRegNum - Get the compact unwind number for a given
370 /// register. The number corresponds to the enum lists in
371 /// compact_unwind_encoding.h.
372 static int getCompactUnwindRegNum(const uint16_t *CURegs, unsigned Reg) {
373 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
380 // Number of registers that can be saved in a compact unwind encoding.
381 #define CU_NUM_SAVED_REGS 6
383 /// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding
384 /// used with frameless stacks. It is passed the number of registers to be saved
385 /// and an array of the registers saved.
387 encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
388 unsigned RegCount, bool Is64Bit) {
389 // The saved registers are numbered from 1 to 6. In order to encode the order
390 // in which they were saved, we re-number them according to their place in the
391 // register order. The re-numbering is relative to the last re-numbered
392 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
401 static const uint16_t CU32BitRegs[] = {
402 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
404 static const uint16_t CU64BitRegs[] = {
405 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
407 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
409 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
410 int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]);
411 if (CUReg == -1) return ~0U;
412 SavedRegs[i] = CUReg;
416 std::swap(SavedRegs[0], SavedRegs[5]);
417 std::swap(SavedRegs[1], SavedRegs[4]);
418 std::swap(SavedRegs[2], SavedRegs[3]);
420 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
421 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i) {
422 unsigned Countless = 0;
423 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
424 if (SavedRegs[j] < SavedRegs[i])
427 RenumRegs[i] = SavedRegs[i] - Countless - 1;
430 // Take the renumbered values and encode them into a 10-bit number.
431 uint32_t permutationEncoding = 0;
434 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
435 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
439 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
440 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
444 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
445 + 3 * RenumRegs[4] + RenumRegs[5];
448 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
452 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
455 permutationEncoding |= RenumRegs[5];
459 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
460 "Invalid compact register encoding!");
461 return permutationEncoding;
464 /// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a
465 /// compact encoding with a frame pointer.
467 encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
469 static const uint16_t CU32BitRegs[] = {
470 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
472 static const uint16_t CU64BitRegs[] = {
473 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
475 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
477 // Encode the registers in the order they were saved, 3-bits per register. The
478 // registers are numbered from 1 to CU_NUM_SAVED_REGS.
480 for (int I = CU_NUM_SAVED_REGS - 1, Idx = 0; I != -1; --I) {
481 unsigned Reg = SavedRegs[I];
482 if (Reg == 0) continue;
484 int CURegNum = getCompactUnwindRegNum(CURegs, Reg);
485 if (CURegNum == -1) return ~0U;
487 // Encode the 3-bit register number in order, skipping over 3-bits for each
489 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
492 assert((RegEnc & 0x3FFFF) == RegEnc && "Invalid compact register encoding!");
496 uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const {
497 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
498 unsigned FramePtr = RegInfo->getFrameRegister(MF);
499 unsigned StackPtr = RegInfo->getStackRegister();
501 bool Is64Bit = STI.is64Bit();
502 bool HasFP = hasFP(MF);
504 unsigned SavedRegs[CU_NUM_SAVED_REGS] = { 0, 0, 0, 0, 0, 0 };
505 unsigned SavedRegIdx = 0;
507 unsigned OffsetSize = (Is64Bit ? 8 : 4);
509 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
510 unsigned PushInstrSize = 1;
511 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
512 unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
513 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
515 unsigned StackDivide = (Is64Bit ? 8 : 4);
517 unsigned InstrOffset = 0;
518 unsigned StackAdjust = 0;
519 unsigned StackSize = 0;
521 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB.
522 bool ExpectEnd = false;
523 for (MachineBasicBlock::iterator
524 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) {
525 MachineInstr &MI = *MBBI;
526 unsigned Opc = MI.getOpcode();
527 if (Opc == X86::PROLOG_LABEL) continue;
528 if (!MI.getFlag(MachineInstr::FrameSetup)) break;
530 // We don't exect any more prolog instructions.
531 if (ExpectEnd) return 0;
533 if (Opc == PushInstr) {
534 // If there are too many saved registers, we cannot use compact encoding.
535 if (SavedRegIdx >= CU_NUM_SAVED_REGS) return 0;
537 SavedRegs[SavedRegIdx++] = MI.getOperand(0).getReg();
538 StackAdjust += OffsetSize;
539 InstrOffset += PushInstrSize;
540 } else if (Opc == MoveInstr) {
541 unsigned SrcReg = MI.getOperand(1).getReg();
542 unsigned DstReg = MI.getOperand(0).getReg();
544 if (DstReg != FramePtr || SrcReg != StackPtr)
548 memset(SavedRegs, 0, sizeof(SavedRegs));
550 InstrOffset += MoveInstrSize;
551 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
552 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
554 // We already have a stack size.
557 if (!MI.getOperand(0).isReg() ||
558 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() ||
559 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm())
560 // We need this to be a stack adjustment pointer. Something like:
562 // %RSP<def> = SUB64ri8 %RSP, 48
565 StackSize = MI.getOperand(2).getImm() / StackDivide;
566 SubtractInstrIdx += InstrOffset;
571 // Encode that we are using EBP/RBP as the frame pointer.
572 uint32_t CompactUnwindEncoding = 0;
573 StackAdjust /= StackDivide;
575 if ((StackAdjust & 0xFF) != StackAdjust)
576 // Offset was too big for compact encoding.
579 // Get the encoding of the saved registers when we have a frame pointer.
580 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
581 if (RegEnc == ~0U) return 0;
583 CompactUnwindEncoding |= 0x01000000;
584 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
585 CompactUnwindEncoding |= RegEnc & 0x7FFF;
588 uint32_t TotalStackSize = StackAdjust + StackSize;
589 if ((TotalStackSize & 0xFF) == TotalStackSize) {
590 // Frameless stack with a small stack size.
591 CompactUnwindEncoding |= 0x02000000;
593 // Encode the stack size.
594 CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16;
596 if ((StackAdjust & 0x7) != StackAdjust)
597 // The extra stack adjustments are too big for us to handle.
600 // Frameless stack with an offset too large for us to encode compactly.
601 CompactUnwindEncoding |= 0x03000000;
603 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
605 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
607 // Encode any extra stack stack adjustments (done via push instructions).
608 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
611 // Encode the number of registers saved.
612 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
614 // Get the encoding of the saved registers when we don't have a frame
617 encodeCompactUnwindRegistersWithoutFrame(SavedRegs, SavedRegIdx,
619 if (RegEnc == ~0U) return 0;
621 // Encode the register encoding.
622 CompactUnwindEncoding |= RegEnc & 0x3FF;
625 return CompactUnwindEncoding;
628 /// emitPrologue - Push callee-saved registers onto the stack, which
629 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
630 /// space for local variables. Also emit labels used by the exception handler to
631 /// generate the exception handling frames.
632 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
633 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
634 MachineBasicBlock::iterator MBBI = MBB.begin();
635 MachineFrameInfo *MFI = MF.getFrameInfo();
636 const Function *Fn = MF.getFunction();
637 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
638 const X86InstrInfo &TII = *TM.getInstrInfo();
639 MachineModuleInfo &MMI = MF.getMMI();
640 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
641 bool needsFrameMoves = MMI.hasDebugInfo() ||
642 Fn->needsUnwindTableEntry();
643 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
644 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
645 bool HasFP = hasFP(MF);
646 bool Is64Bit = STI.is64Bit();
647 bool IsWin64 = STI.isTargetWin64();
648 bool UseLEA = STI.useLeaForSP();
649 unsigned StackAlign = getStackAlignment();
650 unsigned SlotSize = RegInfo->getSlotSize();
651 unsigned FramePtr = RegInfo->getFrameRegister(MF);
652 unsigned StackPtr = RegInfo->getStackRegister();
653 unsigned BasePtr = RegInfo->getBaseRegister();
656 // If we're forcing a stack realignment we can't rely on just the frame
657 // info, we need to know the ABI stack alignment as well in case we
658 // have a call out. Otherwise just make sure we have some alignment - we'll
659 // go with the minimum SlotSize.
660 if (ForceStackAlign) {
662 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
663 else if (MaxAlign < SlotSize)
667 // Add RETADDR move area to callee saved frame size.
668 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
669 if (TailCallReturnAddrDelta < 0)
670 X86FI->setCalleeSavedFrameSize(
671 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
673 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
674 // function, and use up to 128 bytes of stack space, don't have a frame
675 // pointer, calls, or dynamic alloca then we do not need to adjust the
676 // stack pointer (we fit in the Red Zone).
677 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
678 !RegInfo->needsStackRealignment(MF) &&
679 !MFI->hasVarSizedObjects() && // No dynamic alloca.
680 !MFI->adjustsStack() && // No calls.
681 !IsWin64 && // Win64 has no Red Zone
682 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack
683 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
684 if (HasFP) MinSize += SlotSize;
685 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
686 MFI->setStackSize(StackSize);
689 // Insert stack pointer adjustment for later moving of return addr. Only
690 // applies to tail call optimized functions where the callee argument stack
691 // size is bigger than the callers.
692 if (TailCallReturnAddrDelta < 0) {
694 BuildMI(MBB, MBBI, DL,
695 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
698 .addImm(-TailCallReturnAddrDelta)
699 .setMIFlag(MachineInstr::FrameSetup);
700 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
703 // Mapping for machine moves:
705 // DST: VirtualFP AND
706 // SRC: VirtualFP => DW_CFA_def_cfa_offset
707 // ELSE => DW_CFA_def_cfa
709 // SRC: VirtualFP AND
710 // DST: Register => DW_CFA_def_cfa_register
713 // OFFSET < 0 => DW_CFA_offset_extended_sf
714 // REG < 64 => DW_CFA_offset + Reg
715 // ELSE => DW_CFA_offset_extended
717 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
718 const TargetData *TD = MF.getTarget().getTargetData();
719 uint64_t NumBytes = 0;
720 int stackGrowth = -TD->getPointerSize();
723 // Calculate required stack adjustment.
724 uint64_t FrameSize = StackSize - SlotSize;
725 if (RegInfo->needsStackRealignment(MF)) {
726 // Callee-saved registers are pushed on stack before the stack
728 FrameSize -= X86FI->getCalleeSavedFrameSize();
729 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
731 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
734 // Get the offset of the stack slot for the EBP register, which is
735 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
736 // Update the frame offset adjustment.
737 MFI->setOffsetAdjustment(-NumBytes);
739 // Save EBP/RBP into the appropriate stack slot.
740 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
741 .addReg(FramePtr, RegState::Kill)
742 .setMIFlag(MachineInstr::FrameSetup);
744 if (needsFrameMoves) {
745 // Mark the place where EBP/RBP was saved.
746 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
747 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
750 // Define the current CFA rule to use the provided offset.
752 MachineLocation SPDst(MachineLocation::VirtualFP);
753 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
754 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
756 MachineLocation SPDst(StackPtr);
757 MachineLocation SPSrc(StackPtr, stackGrowth);
758 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
761 // Change the rule for the FramePtr to be an "offset" rule.
762 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
763 MachineLocation FPSrc(FramePtr);
764 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
767 // Update EBP with the new base value.
768 BuildMI(MBB, MBBI, DL,
769 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
771 .setMIFlag(MachineInstr::FrameSetup);
773 if (needsFrameMoves) {
774 // Mark effective beginning of when frame pointer becomes valid.
775 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
776 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
779 // Define the current CFA to use the EBP/RBP register.
780 MachineLocation FPDst(FramePtr);
781 MachineLocation FPSrc(MachineLocation::VirtualFP);
782 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
785 // Mark the FramePtr as live-in in every block except the entry.
786 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
788 I->addLiveIn(FramePtr);
790 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
793 // Skip the callee-saved push instructions.
794 bool PushedRegs = false;
795 int StackOffset = 2 * stackGrowth;
797 while (MBBI != MBB.end() &&
798 (MBBI->getOpcode() == X86::PUSH32r ||
799 MBBI->getOpcode() == X86::PUSH64r)) {
801 MBBI->setFlag(MachineInstr::FrameSetup);
804 if (!HasFP && needsFrameMoves) {
805 // Mark callee-saved push instruction.
806 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
807 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
809 // Define the current CFA rule to use the provided offset.
810 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr;
811 MachineLocation SPDst(Ptr);
812 MachineLocation SPSrc(Ptr, StackOffset);
813 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
814 StackOffset += stackGrowth;
818 // Realign stack after we pushed callee-saved registers (so that we'll be
819 // able to calculate their offsets from the frame pointer).
821 // NOTE: We push the registers before realigning the stack, so
822 // vector callee-saved (xmm) registers may be saved w/o proper
823 // alignment in this way. However, currently these regs are saved in
824 // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so
825 // this shouldn't be a problem.
826 if (RegInfo->needsStackRealignment(MF)) {
827 assert(HasFP && "There should be a frame pointer if stack is realigned.");
829 BuildMI(MBB, MBBI, DL,
830 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
833 .setMIFlag(MachineInstr::FrameSetup);
835 // The EFLAGS implicit def is dead.
836 MI->getOperand(3).setIsDead();
839 DL = MBB.findDebugLoc(MBBI);
841 // If there is an SUB32ri of ESP immediately before this instruction, merge
842 // the two. This can be the case when tail call elimination is enabled and
843 // the callee has more arguments then the caller.
844 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
846 // If there is an ADD32ri or SUB32ri of ESP immediately after this
847 // instruction, merge the two instructions.
848 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
850 // Adjust stack pointer: ESP -= numbytes.
852 // Windows and cygwin/mingw require a prologue helper routine when allocating
853 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
854 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
855 // stack and adjust the stack pointer in one go. The 64-bit version of
856 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
857 // responsible for adjusting the stack pointer. Touching the stack at 4K
858 // increments is necessary to ensure that the guard pages used by the OS
859 // virtual memory manager are allocated in correct sequence.
860 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) {
861 const char *StackProbeSymbol;
862 bool isSPUpdateNeeded = false;
865 if (STI.isTargetCygMing())
866 StackProbeSymbol = "___chkstk";
868 StackProbeSymbol = "__chkstk";
869 isSPUpdateNeeded = true;
871 } else if (STI.isTargetCygMing())
872 StackProbeSymbol = "_alloca";
874 StackProbeSymbol = "_chkstk";
876 // Check whether EAX is livein for this function.
877 bool isEAXAlive = isEAXLiveIn(MF);
880 // Sanity check that EAX is not livein for this function.
881 // It should not be, so throw an assert.
882 assert(!Is64Bit && "EAX is livein in x64 case!");
885 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
886 .addReg(X86::EAX, RegState::Kill)
887 .setMIFlag(MachineInstr::FrameSetup);
891 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
892 // Function prologue is responsible for adjusting the stack pointer.
893 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
895 .setMIFlag(MachineInstr::FrameSetup);
897 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
898 // We'll also use 4 already allocated bytes for EAX.
899 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
900 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
901 .setMIFlag(MachineInstr::FrameSetup);
904 BuildMI(MBB, MBBI, DL,
905 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
906 .addExternalSymbol(StackProbeSymbol)
907 .addReg(StackPtr, RegState::Define | RegState::Implicit)
908 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
909 .setMIFlag(MachineInstr::FrameSetup);
911 // MSVC x64's __chkstk needs to adjust %rsp.
912 // FIXME: %rax preserves the offset and should be available.
913 if (isSPUpdateNeeded)
914 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
915 UseLEA, TII, *RegInfo);
919 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
921 StackPtr, false, NumBytes - 4);
922 MI->setFlag(MachineInstr::FrameSetup);
923 MBB.insert(MBBI, MI);
926 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
927 UseLEA, TII, *RegInfo);
929 // If we need a base pointer, set it up here. It's whatever the value
930 // of the stack pointer is at this point. Any variable size objects
931 // will be allocated after this, so we can still use the base pointer
932 // to reference locals.
933 if (RegInfo->hasBasePointer(MF)) {
934 // Update the frame pointer with the current stack pointer.
935 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
936 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
938 .setMIFlag(MachineInstr::FrameSetup);
941 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
942 // Mark end of stack pointer adjustment.
943 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
944 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
947 if (!HasFP && NumBytes) {
948 // Define the current CFA rule to use the provided offset.
950 MachineLocation SPDst(MachineLocation::VirtualFP);
951 MachineLocation SPSrc(MachineLocation::VirtualFP,
952 -StackSize + stackGrowth);
953 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
955 MachineLocation SPDst(StackPtr);
956 MachineLocation SPSrc(StackPtr, stackGrowth);
957 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
961 // Emit DWARF info specifying the offsets of the callee-saved registers.
963 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
966 // Darwin 10.7 and greater has support for compact unwind encoding.
967 if (STI.getTargetTriple().isMacOSX() &&
968 !STI.getTargetTriple().isMacOSXVersionLT(10, 7))
969 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
972 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
973 MachineBasicBlock &MBB) const {
974 const MachineFrameInfo *MFI = MF.getFrameInfo();
975 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
976 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
977 const X86InstrInfo &TII = *TM.getInstrInfo();
978 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
979 assert(MBBI != MBB.end() && "Returning block has no instructions");
980 unsigned RetOpcode = MBBI->getOpcode();
981 DebugLoc DL = MBBI->getDebugLoc();
982 bool Is64Bit = STI.is64Bit();
983 bool UseLEA = STI.useLeaForSP();
984 unsigned StackAlign = getStackAlignment();
985 unsigned SlotSize = RegInfo->getSlotSize();
986 unsigned FramePtr = RegInfo->getFrameRegister(MF);
987 unsigned StackPtr = RegInfo->getStackRegister();
991 llvm_unreachable("Can only insert epilog into returning blocks");
994 case X86::TCRETURNdi:
995 case X86::TCRETURNri:
996 case X86::TCRETURNmi:
997 case X86::TCRETURNdi64:
998 case X86::TCRETURNri64:
999 case X86::TCRETURNmi64:
1000 case X86::EH_RETURN:
1001 case X86::EH_RETURN64:
1002 break; // These are ok
1005 // Get the number of bytes to allocate from the FrameInfo.
1006 uint64_t StackSize = MFI->getStackSize();
1007 uint64_t MaxAlign = MFI->getMaxAlignment();
1008 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1009 uint64_t NumBytes = 0;
1011 // If we're forcing a stack realignment we can't rely on just the frame
1012 // info, we need to know the ABI stack alignment as well in case we
1013 // have a call out. Otherwise just make sure we have some alignment - we'll
1014 // go with the minimum.
1015 if (ForceStackAlign) {
1016 if (MFI->hasCalls())
1017 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1019 MaxAlign = MaxAlign ? MaxAlign : 4;
1023 // Calculate required stack adjustment.
1024 uint64_t FrameSize = StackSize - SlotSize;
1025 if (RegInfo->needsStackRealignment(MF)) {
1026 // Callee-saved registers were pushed on stack before the stack
1028 FrameSize -= CSSize;
1029 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
1031 NumBytes = FrameSize - CSSize;
1035 BuildMI(MBB, MBBI, DL,
1036 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1038 NumBytes = StackSize - CSSize;
1041 // Skip the callee-saved pop instructions.
1042 while (MBBI != MBB.begin()) {
1043 MachineBasicBlock::iterator PI = prior(MBBI);
1044 unsigned Opc = PI->getOpcode();
1046 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1047 !PI->isTerminator())
1052 MachineBasicBlock::iterator FirstCSPop = MBBI;
1054 DL = MBBI->getDebugLoc();
1056 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1057 // instruction, merge the two instructions.
1058 if (NumBytes || MFI->hasVarSizedObjects())
1059 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1061 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1062 // slot before popping them off! Same applies for the case, when stack was
1064 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1065 if (RegInfo->needsStackRealignment(MF))
1068 unsigned Opc = getLEArOpcode(Is64Bit);
1069 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1070 FramePtr, false, -CSSize);
1072 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1073 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1076 } else if (NumBytes) {
1077 // Adjust stack pointer back: ESP += numbytes.
1078 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, UseLEA, TII, *RegInfo);
1081 // We're returning from function via eh_return.
1082 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1083 MBBI = MBB.getLastNonDebugInstr();
1084 MachineOperand &DestAddr = MBBI->getOperand(0);
1085 assert(DestAddr.isReg() && "Offset should be in register!");
1086 BuildMI(MBB, MBBI, DL,
1087 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1088 StackPtr).addReg(DestAddr.getReg());
1089 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1090 RetOpcode == X86::TCRETURNmi ||
1091 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1092 RetOpcode == X86::TCRETURNmi64) {
1093 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1094 // Tail call return: adjust the stack pointer and jump to callee.
1095 MBBI = MBB.getLastNonDebugInstr();
1096 MachineOperand &JumpTarget = MBBI->getOperand(0);
1097 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1098 assert(StackAdjust.isImm() && "Expecting immediate value.");
1100 // Adjust stack pointer.
1101 int StackAdj = StackAdjust.getImm();
1102 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1104 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1106 // Incoporate the retaddr area.
1107 Offset = StackAdj-MaxTCDelta;
1108 assert(Offset >= 0 && "Offset should never be negative");
1111 // Check for possible merge with preceding ADD instruction.
1112 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1113 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, UseLEA, TII, *RegInfo);
1116 // Jump to label or value in register.
1117 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1118 MachineInstrBuilder MIB =
1119 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1120 ? X86::TAILJMPd : X86::TAILJMPd64));
1121 if (JumpTarget.isGlobal())
1122 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1123 JumpTarget.getTargetFlags());
1125 assert(JumpTarget.isSymbol());
1126 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1127 JumpTarget.getTargetFlags());
1129 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1130 MachineInstrBuilder MIB =
1131 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1132 ? X86::TAILJMPm : X86::TAILJMPm64));
1133 for (unsigned i = 0; i != 5; ++i)
1134 MIB.addOperand(MBBI->getOperand(i));
1135 } else if (RetOpcode == X86::TCRETURNri64) {
1136 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1137 addReg(JumpTarget.getReg(), RegState::Kill);
1139 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1140 addReg(JumpTarget.getReg(), RegState::Kill);
1143 MachineInstr *NewMI = prior(MBBI);
1144 NewMI->copyImplicitOps(MBBI);
1146 // Delete the pseudo instruction TCRETURN.
1148 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1149 (X86FI->getTCReturnAddrDelta() < 0)) {
1150 // Add the return addr area delta back since we are not tail calling.
1151 int delta = -1*X86FI->getTCReturnAddrDelta();
1152 MBBI = MBB.getLastNonDebugInstr();
1154 // Check for possible merge with preceding ADD instruction.
1155 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1156 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, UseLEA, TII, *RegInfo);
1160 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
1161 const X86RegisterInfo *RegInfo =
1162 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1163 const MachineFrameInfo *MFI = MF.getFrameInfo();
1164 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1165 uint64_t StackSize = MFI->getStackSize();
1167 if (RegInfo->hasBasePointer(MF)) {
1168 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1170 // Skip the saved EBP.
1171 return Offset + RegInfo->getSlotSize();
1173 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1174 return Offset + StackSize;
1176 } else if (RegInfo->needsStackRealignment(MF)) {
1178 // Skip the saved EBP.
1179 return Offset + RegInfo->getSlotSize();
1181 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1182 return Offset + StackSize;
1184 // FIXME: Support tail calls
1187 return Offset + StackSize;
1189 // Skip the saved EBP.
1190 Offset += RegInfo->getSlotSize();
1192 // Skip the RETADDR move area
1193 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1194 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1195 if (TailCallReturnAddrDelta < 0)
1196 Offset -= TailCallReturnAddrDelta;
1202 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1203 unsigned &FrameReg) const {
1204 const X86RegisterInfo *RegInfo =
1205 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1206 // We can't calculate offset from frame pointer if the stack is realigned,
1207 // so enforce usage of stack/base pointer. The base pointer is used when we
1208 // have dynamic allocas in addition to dynamic realignment.
1209 if (RegInfo->hasBasePointer(MF))
1210 FrameReg = RegInfo->getBaseRegister();
1211 else if (RegInfo->needsStackRealignment(MF))
1212 FrameReg = RegInfo->getStackRegister();
1214 FrameReg = RegInfo->getFrameRegister(MF);
1215 return getFrameIndexOffset(MF, FI);
1218 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1219 MachineBasicBlock::iterator MI,
1220 const std::vector<CalleeSavedInfo> &CSI,
1221 const TargetRegisterInfo *TRI) const {
1225 DebugLoc DL = MBB.findDebugLoc(MI);
1227 MachineFunction &MF = *MBB.getParent();
1229 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
1230 unsigned FPReg = TRI->getFrameRegister(MF);
1231 unsigned CalleeFrameSize = 0;
1233 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1234 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1236 // Push GPRs. It increases frame size.
1237 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1238 for (unsigned i = CSI.size(); i != 0; --i) {
1239 unsigned Reg = CSI[i-1].getReg();
1240 if (!X86::GR64RegClass.contains(Reg) &&
1241 !X86::GR32RegClass.contains(Reg))
1243 // Add the callee-saved register as live-in. It's killed at the spill.
1246 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
1248 CalleeFrameSize += SlotSize;
1249 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1250 .setMIFlag(MachineInstr::FrameSetup);
1253 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
1255 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1256 // It can be done by spilling XMMs to stack frame.
1257 // Note that only Win64 ABI might spill XMMs.
1258 for (unsigned i = CSI.size(); i != 0; --i) {
1259 unsigned Reg = CSI[i-1].getReg();
1260 if (X86::GR64RegClass.contains(Reg) ||
1261 X86::GR32RegClass.contains(Reg))
1263 // Add the callee-saved register as live-in. It's killed at the spill.
1265 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1266 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1273 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1274 MachineBasicBlock::iterator MI,
1275 const std::vector<CalleeSavedInfo> &CSI,
1276 const TargetRegisterInfo *TRI) const {
1280 DebugLoc DL = MBB.findDebugLoc(MI);
1282 MachineFunction &MF = *MBB.getParent();
1283 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1285 // Reload XMMs from stack frame.
1286 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1287 unsigned Reg = CSI[i].getReg();
1288 if (X86::GR64RegClass.contains(Reg) ||
1289 X86::GR32RegClass.contains(Reg))
1291 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1292 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1297 unsigned FPReg = TRI->getFrameRegister(MF);
1298 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1299 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1300 unsigned Reg = CSI[i].getReg();
1301 if (!X86::GR64RegClass.contains(Reg) &&
1302 !X86::GR32RegClass.contains(Reg))
1305 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
1307 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1313 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1314 RegScavenger *RS) const {
1315 MachineFrameInfo *MFI = MF.getFrameInfo();
1316 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
1317 unsigned SlotSize = RegInfo->getSlotSize();
1319 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1320 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1322 if (TailCallReturnAddrDelta < 0) {
1323 // create RETURNADDR area
1332 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1333 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
1337 assert((TailCallReturnAddrDelta <= 0) &&
1338 "The Delta should always be zero or negative");
1339 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
1341 // Create a frame entry for the EBP register that must be saved.
1342 int FrameIdx = MFI->CreateFixedObject(SlotSize,
1344 TFI.getOffsetOfLocalArea() +
1345 TailCallReturnAddrDelta,
1347 assert(FrameIdx == MFI->getObjectIndexBegin() &&
1348 "Slot for EBP register must be last in order to be found!");
1352 // Spill the BasePtr if it's used.
1353 if (RegInfo->hasBasePointer(MF))
1354 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1358 HasNestArgument(const MachineFunction *MF) {
1359 const Function *F = MF->getFunction();
1360 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1362 if (I->hasNestAttr())
1369 /// GetScratchRegister - Get a register for performing work in the segmented
1370 /// stack prologue. Depending on platform and the properties of the function
1371 /// either one or two registers will be needed. Set primary to true for
1372 /// the first register, false for the second.
1374 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1376 return Primary ? X86::R11 : X86::R12;
1378 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1379 bool IsNested = HasNestArgument(&MF);
1381 if (CallingConvention == CallingConv::X86_FastCall ||
1382 CallingConvention == CallingConv::Fast) {
1384 report_fatal_error("Segmented stacks does not support fastcall with "
1385 "nested function.");
1386 return Primary ? X86::EAX : X86::ECX;
1389 return Primary ? X86::EDX : X86::EAX;
1390 return Primary ? X86::ECX : X86::EAX;
1393 // The stack limit in the TCB is set to this many bytes above the actual stack
1395 static const uint64_t kSplitStackAvailable = 256;
1398 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1399 MachineBasicBlock &prologueMBB = MF.front();
1400 MachineFrameInfo *MFI = MF.getFrameInfo();
1401 const X86InstrInfo &TII = *TM.getInstrInfo();
1403 bool Is64Bit = STI.is64Bit();
1404 unsigned TlsReg, TlsOffset;
1406 const X86Subtarget *ST = &MF.getTarget().getSubtarget<X86Subtarget>();
1408 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1409 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1410 "Scratch register is live-in");
1412 if (MF.getFunction()->isVarArg())
1413 report_fatal_error("Segmented stacks do not support vararg functions.");
1414 if (!ST->isTargetLinux() && !ST->isTargetDarwin() &&
1415 !ST->isTargetWin32() && !ST->isTargetFreeBSD())
1416 report_fatal_error("Segmented stacks not supported on this platform.");
1418 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1419 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1420 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1421 bool IsNested = false;
1423 // We need to know if the function has a nest argument only in 64 bit mode.
1425 IsNested = HasNestArgument(&MF);
1427 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1428 // allocMBB needs to be last (terminating) instruction.
1430 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1431 e = prologueMBB.livein_end(); i != e; i++) {
1432 allocMBB->addLiveIn(*i);
1433 checkMBB->addLiveIn(*i);
1437 allocMBB->addLiveIn(X86::R10);
1439 MF.push_front(allocMBB);
1440 MF.push_front(checkMBB);
1442 // Eventually StackSize will be calculated by a link-time pass; which will
1443 // also decide whether checking code needs to be injected into this particular
1445 StackSize = MFI->getStackSize();
1447 // When the frame size is less than 256 we just compare the stack
1448 // boundary directly to the value of the stack pointer, per gcc.
1449 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1451 // Read the limit off the current stacklet off the stack_guard location.
1453 if (ST->isTargetLinux()) {
1456 } else if (ST->isTargetDarwin()) {
1458 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1459 } else if (ST->isTargetFreeBSD()) {
1463 report_fatal_error("Segmented stacks not supported on this platform.");
1466 if (CompareStackPointer)
1467 ScratchReg = X86::RSP;
1469 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1470 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1472 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1473 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1475 if (ST->isTargetLinux()) {
1478 } else if (ST->isTargetDarwin()) {
1480 TlsOffset = 0x48 + 90*4;
1481 } else if (ST->isTargetWin32()) {
1483 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1484 } else if (ST->isTargetFreeBSD()) {
1485 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1487 report_fatal_error("Segmented stacks not supported on this platform.");
1490 if (CompareStackPointer)
1491 ScratchReg = X86::ESP;
1493 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1494 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1496 if (ST->isTargetLinux() || ST->isTargetWin32()) {
1497 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1498 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1499 } else if (ST->isTargetDarwin()) {
1501 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
1502 unsigned ScratchReg2;
1504 if (CompareStackPointer) {
1505 // The primary scratch register is available for holding the TLS offset
1506 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1507 SaveScratch2 = false;
1509 // Need to use a second register to hold the TLS offset
1510 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1512 // Unfortunately, with fastcc the second scratch register may hold an arg
1513 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1516 // If Scratch2 is live-in then it needs to be saved
1517 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1518 "Scratch register is live-in and not saved");
1521 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1522 .addReg(ScratchReg2, RegState::Kill);
1524 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1526 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1528 .addReg(ScratchReg2).addImm(1).addReg(0)
1533 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1537 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1538 // It jumps to normal execution of the function body.
1539 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1541 // On 32 bit we first push the arguments size and then the frame size. On 64
1542 // bit, we pass the stack frame size in r10 and the argument size in r11.
1544 // Functions with nested arguments use R10, so it needs to be saved across
1545 // the call to _morestack
1548 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1550 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1552 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1553 .addImm(X86FI->getArgumentStackSize());
1554 MF.getRegInfo().setPhysRegUsed(X86::R10);
1555 MF.getRegInfo().setPhysRegUsed(X86::R11);
1557 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1558 .addImm(X86FI->getArgumentStackSize());
1559 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1563 // __morestack is in libgcc
1565 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1566 .addExternalSymbol("__morestack");
1568 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1569 .addExternalSymbol("__morestack");
1572 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1574 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1576 allocMBB->addSuccessor(&prologueMBB);
1578 checkMBB->addSuccessor(allocMBB);
1579 checkMBB->addSuccessor(&prologueMBB);