1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
36 // FIXME: completely move here.
37 extern cl::opt<bool> ForceStackAlign;
39 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
40 return !MF.getFrameInfo()->hasVarSizedObjects();
43 /// hasFP - Return true if the specified function should have a dedicated frame
44 /// pointer register. This is true if the function has variable sized allocas
45 /// or if frame pointer elimination is disabled.
46 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
47 const MachineFrameInfo *MFI = MF.getFrameInfo();
48 const MachineModuleInfo &MMI = MF.getMMI();
49 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
51 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
52 RegInfo->needsStackRealignment(MF) ||
53 MFI->hasVarSizedObjects() ||
54 MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
55 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
56 MMI.callsUnwindInit() || MMI.callsEHReturn());
59 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
63 return X86::SUB64ri32;
71 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
75 return X86::ADD64ri32;
83 static unsigned getLEArOpcode(unsigned IsLP64) {
84 return IsLP64 ? X86::LEA64r : X86::LEA32r;
87 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
88 /// when it reaches the "return" instruction. We can then pop a stack object
89 /// to this register without worry about clobbering it.
90 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator &MBBI,
92 const TargetRegisterInfo &TRI,
94 const MachineFunction *MF = MBB.getParent();
95 const Function *F = MF->getFunction();
96 if (!F || MF->getMMI().callsEHReturn())
99 static const uint16_t CallerSavedRegs32Bit[] = {
100 X86::EAX, X86::EDX, X86::ECX, 0
103 static const uint16_t CallerSavedRegs64Bit[] = {
104 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
105 X86::R8, X86::R9, X86::R10, X86::R11, 0
108 unsigned Opc = MBBI->getOpcode();
115 case X86::TCRETURNdi:
116 case X86::TCRETURNri:
117 case X86::TCRETURNmi:
118 case X86::TCRETURNdi64:
119 case X86::TCRETURNri64:
120 case X86::TCRETURNmi64:
122 case X86::EH_RETURN64: {
123 SmallSet<uint16_t, 8> Uses;
124 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
125 MachineOperand &MO = MBBI->getOperand(i);
126 if (!MO.isReg() || MO.isDef())
128 unsigned Reg = MO.getReg();
131 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
135 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
137 if (!Uses.count(*CS))
146 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
147 /// stack pointer by a constant value.
149 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
150 unsigned StackPtr, int64_t NumBytes,
151 bool Is64BitTarget, bool Is64BitStackPtr, bool UseLEA,
152 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
153 bool isSub = NumBytes < 0;
154 uint64_t Offset = isSub ? -NumBytes : NumBytes;
157 Opc = getLEArOpcode(Is64BitStackPtr);
160 ? getSUBriOpcode(Is64BitStackPtr, Offset)
161 : getADDriOpcode(Is64BitStackPtr, Offset);
163 uint64_t Chunk = (1LL << 31) - 1;
164 DebugLoc DL = MBB.findDebugLoc(MBBI);
167 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
168 if (ThisVal == (Is64BitTarget ? 8 : 4)) {
169 // Use push / pop instead.
171 ? (unsigned)(Is64BitTarget ? X86::RAX : X86::EAX)
172 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64BitTarget);
175 ? (Is64BitTarget ? X86::PUSH64r : X86::PUSH32r)
176 : (Is64BitTarget ? X86::POP64r : X86::POP32r);
177 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
178 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
180 MI->setFlag(MachineInstr::FrameSetup);
186 MachineInstr *MI = nullptr;
189 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
190 StackPtr, false, isSub ? -ThisVal : ThisVal);
192 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
195 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
199 MI->setFlag(MachineInstr::FrameSetup);
205 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
207 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
208 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
209 if (MBBI == MBB.begin()) return;
211 MachineBasicBlock::iterator PI = std::prev(MBBI);
212 unsigned Opc = PI->getOpcode();
213 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
214 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
215 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
216 PI->getOperand(0).getReg() == StackPtr) {
218 *NumBytes += PI->getOperand(2).getImm();
220 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
221 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
222 PI->getOperand(0).getReg() == StackPtr) {
224 *NumBytes -= PI->getOperand(2).getImm();
229 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower
232 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
233 MachineBasicBlock::iterator &MBBI,
234 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
235 // FIXME: THIS ISN'T RUN!!!
238 if (MBBI == MBB.end()) return;
240 MachineBasicBlock::iterator NI = std::next(MBBI);
241 if (NI == MBB.end()) return;
243 unsigned Opc = NI->getOpcode();
244 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
245 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
246 NI->getOperand(0).getReg() == StackPtr) {
248 *NumBytes -= NI->getOperand(2).getImm();
251 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
252 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
253 NI->getOperand(0).getReg() == StackPtr) {
255 *NumBytes += NI->getOperand(2).getImm();
261 /// mergeSPUpdates - Checks the instruction before/after the passed
262 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
263 /// the stack adjustment is returned as a positive value for ADD/LEA and a
264 /// negative for SUB.
265 static int mergeSPUpdates(MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
267 bool doMergeWithPrevious) {
268 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
269 (!doMergeWithPrevious && MBBI == MBB.end()))
272 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
273 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
275 unsigned Opc = PI->getOpcode();
278 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
279 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
280 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
281 PI->getOperand(0).getReg() == StackPtr){
282 Offset += PI->getOperand(2).getImm();
284 if (!doMergeWithPrevious) MBBI = NI;
285 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
286 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
287 PI->getOperand(0).getReg() == StackPtr) {
288 Offset -= PI->getOperand(2).getImm();
290 if (!doMergeWithPrevious) MBBI = NI;
296 static bool isEAXLiveIn(MachineFunction &MF) {
297 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
298 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
299 unsigned Reg = II->first;
301 if (Reg == X86::EAX || Reg == X86::AX ||
302 Reg == X86::AH || Reg == X86::AL)
310 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
311 MachineBasicBlock::iterator MBBI,
313 MachineFunction &MF = *MBB.getParent();
314 MachineFrameInfo *MFI = MF.getFrameInfo();
315 MachineModuleInfo &MMI = MF.getMMI();
316 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
317 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
319 // Add callee saved registers to move list.
320 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
321 if (CSI.empty()) return;
323 // Calculate offsets.
324 for (std::vector<CalleeSavedInfo>::const_iterator
325 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
326 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
327 unsigned Reg = I->getReg();
329 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
331 MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg,
333 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
334 .addCFIIndex(CFIIndex);
338 /// usesTheStack - This function checks if any of the users of EFLAGS
339 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
340 /// to use the stack, and if we don't adjust the stack we clobber the first
342 /// See X86InstrInfo::copyPhysReg.
343 static bool usesTheStack(const MachineFunction &MF) {
344 const MachineRegisterInfo &MRI = MF.getRegInfo();
346 for (MachineRegisterInfo::reg_instr_iterator
347 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
355 void X86FrameLowering::getStackProbeFunction(const X86Subtarget &STI,
357 const char *&Symbol) {
358 CallOp = STI.is64Bit() ? X86::W64ALLOCA : X86::CALLpcrel32;
361 if (STI.isTargetCygMing()) {
362 Symbol = "___chkstk_ms";
366 } else if (STI.isTargetCygMing())
372 /// emitPrologue - Push callee-saved registers onto the stack, which
373 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
374 /// space for local variables. Also emit labels used by the exception handler to
375 /// generate the exception handling frames.
378 Here's a gist of what gets emitted:
380 ; Establish frame pointer, if needed
383 .cfi_def_cfa_offset 16
384 .cfi_offset %rbp, -16
387 .cfi_def_cfa_register %rbp
389 ; Spill general-purpose registers
390 [for all callee-saved GPRs]
393 .cfi_def_cfa_offset (offset from RETADDR)
396 ; If the required stack alignment > default stack alignment
397 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
398 ; of unknown size in the stack frame.
399 [if stack needs re-alignment]
402 ; Allocate space for locals
403 [if target is Windows and allocated space > 4096 bytes]
404 ; Windows needs special care for allocations larger
407 call ___chkstk_ms/___chkstk
413 .seh_stackalloc (size of XMM spill slots)
414 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
419 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
420 ; they may get spilled on any platform, if the current function
421 ; calls @llvm.eh.unwind.init
423 [for all callee-saved XMM registers]
424 movaps %<xmm reg>, -MMM(%rbp)
425 [for all callee-saved XMM registers]
426 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
427 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
429 [for all callee-saved XMM registers]
430 movaps %<xmm reg>, KKK(%rsp)
431 [for all callee-saved XMM registers]
432 .seh_savexmm %<xmm reg>, KKK
436 [if needs base pointer]
441 [for all callee-saved registers]
442 .cfi_offset %<reg>, (offset from %rbp)
444 .cfi_def_cfa_offset (offset from RETADDR)
445 [for all callee-saved registers]
446 .cfi_offset %<reg>, (offset from %rsp)
449 - .seh directives are emitted only for Windows 64 ABI
450 - .cfi directives are emitted for all other ABIs
451 - for 32-bit code, substitute %e?? registers for %r??
454 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
455 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
456 MachineBasicBlock::iterator MBBI = MBB.begin();
457 MachineFrameInfo *MFI = MF.getFrameInfo();
458 const Function *Fn = MF.getFunction();
459 const X86RegisterInfo *RegInfo =
460 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
461 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
462 MachineModuleInfo &MMI = MF.getMMI();
463 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
464 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
465 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
466 bool HasFP = hasFP(MF);
467 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
468 bool Is64Bit = STI.is64Bit();
469 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
470 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
471 bool IsWin64 = STI.isTargetWin64();
473 MF.getTarget().getMCAsmInfo()->getExceptionHandlingType() ==
474 ExceptionHandling::WinEH; // Not necessarily synonymous with IsWin64.
475 bool NeedsWinEH = IsWinEH && Fn->needsUnwindTableEntry();
477 !IsWinEH && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
478 bool UseLEA = STI.useLeaForSP();
479 unsigned StackAlign = getStackAlignment();
480 unsigned SlotSize = RegInfo->getSlotSize();
481 unsigned FramePtr = RegInfo->getFrameRegister(MF);
482 const unsigned MachineFramePtr = STI.isTarget64BitILP32() ?
483 getX86SubSuperRegister(FramePtr, MVT::i64, false) : FramePtr;
484 unsigned StackPtr = RegInfo->getStackRegister();
485 unsigned BasePtr = RegInfo->getBaseRegister();
488 // If we're forcing a stack realignment we can't rely on just the frame
489 // info, we need to know the ABI stack alignment as well in case we
490 // have a call out. Otherwise just make sure we have some alignment - we'll
491 // go with the minimum SlotSize.
492 if (ForceStackAlign) {
494 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
495 else if (MaxAlign < SlotSize)
499 // Add RETADDR move area to callee saved frame size.
500 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
501 if (TailCallReturnAddrDelta < 0)
502 X86FI->setCalleeSavedFrameSize(
503 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
505 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMacho());
507 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
508 // function, and use up to 128 bytes of stack space, don't have a frame
509 // pointer, calls, or dynamic alloca then we do not need to adjust the
510 // stack pointer (we fit in the Red Zone). We also check that we don't
511 // push and pop from the stack.
512 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
513 Attribute::NoRedZone) &&
514 !RegInfo->needsStackRealignment(MF) &&
515 !MFI->hasVarSizedObjects() && // No dynamic alloca.
516 !MFI->adjustsStack() && // No calls.
517 !IsWin64 && // Win64 has no Red Zone
518 !usesTheStack(MF) && // Don't push and pop.
519 !MF.shouldSplitStack()) { // Regular stack
520 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
521 if (HasFP) MinSize += SlotSize;
522 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
523 MFI->setStackSize(StackSize);
526 // Insert stack pointer adjustment for later moving of return addr. Only
527 // applies to tail call optimized functions where the callee argument stack
528 // size is bigger than the callers.
529 if (TailCallReturnAddrDelta < 0) {
531 BuildMI(MBB, MBBI, DL,
532 TII.get(getSUBriOpcode(Uses64BitFramePtr, -TailCallReturnAddrDelta)),
535 .addImm(-TailCallReturnAddrDelta)
536 .setMIFlag(MachineInstr::FrameSetup);
537 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
540 // Mapping for machine moves:
542 // DST: VirtualFP AND
543 // SRC: VirtualFP => DW_CFA_def_cfa_offset
544 // ELSE => DW_CFA_def_cfa
546 // SRC: VirtualFP AND
547 // DST: Register => DW_CFA_def_cfa_register
550 // OFFSET < 0 => DW_CFA_offset_extended_sf
551 // REG < 64 => DW_CFA_offset + Reg
552 // ELSE => DW_CFA_offset_extended
554 uint64_t NumBytes = 0;
555 int stackGrowth = -SlotSize;
558 // Calculate required stack adjustment.
559 uint64_t FrameSize = StackSize - SlotSize;
560 if (RegInfo->needsStackRealignment(MF)) {
561 // Callee-saved registers are pushed on stack before the stack
563 FrameSize -= X86FI->getCalleeSavedFrameSize();
564 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
566 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
569 // Get the offset of the stack slot for the EBP register, which is
570 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
571 // Update the frame offset adjustment.
572 MFI->setOffsetAdjustment(-NumBytes);
574 // Save EBP/RBP into the appropriate stack slot.
575 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
576 .addReg(MachineFramePtr, RegState::Kill)
577 .setMIFlag(MachineInstr::FrameSetup);
580 // Mark the place where EBP/RBP was saved.
581 // Define the current CFA rule to use the provided offset.
583 unsigned CFIIndex = MMI.addFrameInst(
584 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
585 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
586 .addCFIIndex(CFIIndex);
588 // Change the rule for the FramePtr to be an "offset" rule.
589 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
590 CFIIndex = MMI.addFrameInst(
591 MCCFIInstruction::createOffset(nullptr,
592 DwarfFramePtr, 2 * stackGrowth));
593 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
594 .addCFIIndex(CFIIndex);
598 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
600 .setMIFlag(MachineInstr::FrameSetup);
603 // Update EBP with the new base value.
604 BuildMI(MBB, MBBI, DL,
605 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), FramePtr)
607 .setMIFlag(MachineInstr::FrameSetup);
610 // Mark effective beginning of when frame pointer becomes valid.
611 // Define the current CFA to use the EBP/RBP register.
612 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
613 unsigned CFIIndex = MMI.addFrameInst(
614 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
615 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
616 .addCFIIndex(CFIIndex);
619 // Mark the FramePtr as live-in in every block.
620 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
621 I->addLiveIn(MachineFramePtr);
623 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
626 // Skip the callee-saved push instructions.
627 bool PushedRegs = false;
628 int StackOffset = 2 * stackGrowth;
630 while (MBBI != MBB.end() &&
631 (MBBI->getOpcode() == X86::PUSH32r ||
632 MBBI->getOpcode() == X86::PUSH64r)) {
634 unsigned Reg = MBBI->getOperand(0).getReg();
637 if (!HasFP && NeedsDwarfCFI) {
638 // Mark callee-saved push instruction.
639 // Define the current CFA rule to use the provided offset.
641 unsigned CFIIndex = MMI.addFrameInst(
642 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
643 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
644 .addCFIIndex(CFIIndex);
645 StackOffset += stackGrowth;
649 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
650 MachineInstr::FrameSetup);
654 // Realign stack after we pushed callee-saved registers (so that we'll be
655 // able to calculate their offsets from the frame pointer).
656 if (RegInfo->needsStackRealignment(MF)) {
657 assert(HasFP && "There should be a frame pointer if stack is realigned.");
659 BuildMI(MBB, MBBI, DL,
660 TII.get(Uses64BitFramePtr ? X86::AND64ri32 : X86::AND32ri), StackPtr)
663 .setMIFlag(MachineInstr::FrameSetup);
665 // The EFLAGS implicit def is dead.
666 MI->getOperand(3).setIsDead();
669 // If there is an SUB32ri of ESP immediately before this instruction, merge
670 // the two. This can be the case when tail call elimination is enabled and
671 // the callee has more arguments then the caller.
672 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
674 // If there is an ADD32ri or SUB32ri of ESP immediately after this
675 // instruction, merge the two instructions.
676 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
678 // Adjust stack pointer: ESP -= numbytes.
680 static const size_t PageSize = 4096;
682 // Windows and cygwin/mingw require a prologue helper routine when allocating
683 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
684 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
685 // stack and adjust the stack pointer in one go. The 64-bit version of
686 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
687 // responsible for adjusting the stack pointer. Touching the stack at 4K
688 // increments is necessary to ensure that the guard pages used by the OS
689 // virtual memory manager are allocated in correct sequence.
690 if (NumBytes >= PageSize && UseStackProbe) {
691 const char *StackProbeSymbol;
694 getStackProbeFunction(STI, CallOp, StackProbeSymbol);
696 // Check whether EAX is livein for this function.
697 bool isEAXAlive = isEAXLiveIn(MF);
700 // Sanity check that EAX is not livein for this function.
701 // It should not be, so throw an assert.
702 assert(!Is64Bit && "EAX is livein in x64 case!");
705 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
706 .addReg(X86::EAX, RegState::Kill)
707 .setMIFlag(MachineInstr::FrameSetup);
711 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
712 // Function prologue is responsible for adjusting the stack pointer.
713 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
715 .setMIFlag(MachineInstr::FrameSetup);
717 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
718 // We'll also use 4 already allocated bytes for EAX.
719 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
720 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
721 .setMIFlag(MachineInstr::FrameSetup);
724 BuildMI(MBB, MBBI, DL,
726 .addExternalSymbol(StackProbeSymbol)
727 .addReg(StackPtr, RegState::Define | RegState::Implicit)
728 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
729 .setMIFlag(MachineInstr::FrameSetup);
732 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
733 // themself. It also does not clobber %rax so we can reuse it when
735 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), StackPtr)
738 .setMIFlag(MachineInstr::FrameSetup);
742 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
744 StackPtr, false, NumBytes - 4);
745 MI->setFlag(MachineInstr::FrameSetup);
746 MBB.insert(MBBI, MI);
748 } else if (NumBytes) {
749 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, Uses64BitFramePtr,
750 UseLEA, TII, *RegInfo);
753 int SEHFrameOffset = 0;
756 // We need to set frame base offset low enough such that all saved
757 // register offsets would be positive relative to it, but we can't
758 // just use NumBytes, because .seh_setframe offset must be <=240.
759 // So we pretend to have only allocated enough space to spill the
760 // non-volatile registers.
761 // We don't care about the rest of stack allocation, because unwinder
762 // will restore SP to (BP - SEHFrameOffset)
763 for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
764 int offset = MFI->getObjectOffset(Info.getFrameIdx());
765 SEHFrameOffset = std::max(SEHFrameOffset, abs(offset));
767 SEHFrameOffset += SEHFrameOffset % 16; // ensure alignmant
769 // This only needs to account for XMM spill slots, GPR slots
770 // are covered by the .seh_pushreg's emitted above.
771 unsigned Size = SEHFrameOffset - X86FI->getCalleeSavedFrameSize();
773 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
775 .setMIFlag(MachineInstr::FrameSetup);
778 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
780 .addImm(SEHFrameOffset)
781 .setMIFlag(MachineInstr::FrameSetup);
783 // SP will be the base register for restoring XMMs
785 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
787 .setMIFlag(MachineInstr::FrameSetup);
792 // Skip the rest of register spilling code
793 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
796 // Emit SEH info for non-GPRs
798 for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
799 unsigned Reg = Info.getReg();
800 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
802 assert(X86::FR64RegClass.contains(Reg) && "Unexpected register class");
804 int Offset = getFrameIndexOffset(MF, Info.getFrameIdx());
805 Offset += SEHFrameOffset;
807 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
810 .setMIFlag(MachineInstr::FrameSetup);
813 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
814 .setMIFlag(MachineInstr::FrameSetup);
817 // If we need a base pointer, set it up here. It's whatever the value
818 // of the stack pointer is at this point. Any variable size objects
819 // will be allocated after this, so we can still use the base pointer
820 // to reference locals.
821 if (RegInfo->hasBasePointer(MF)) {
822 // Update the base pointer with the current stack pointer.
823 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
824 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
826 .setMIFlag(MachineInstr::FrameSetup);
829 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
830 // Mark end of stack pointer adjustment.
831 if (!HasFP && NumBytes) {
832 // Define the current CFA rule to use the provided offset.
834 unsigned CFIIndex = MMI.addFrameInst(
835 MCCFIInstruction::createDefCfaOffset(nullptr,
836 -StackSize + stackGrowth));
838 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
839 .addCFIIndex(CFIIndex);
842 // Emit DWARF info specifying the offsets of the callee-saved registers.
844 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
848 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
849 MachineBasicBlock &MBB) const {
850 const MachineFrameInfo *MFI = MF.getFrameInfo();
851 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
852 const X86RegisterInfo *RegInfo =
853 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
854 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
855 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
856 assert(MBBI != MBB.end() && "Returning block has no instructions");
857 unsigned RetOpcode = MBBI->getOpcode();
858 DebugLoc DL = MBBI->getDebugLoc();
859 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
860 bool Is64Bit = STI.is64Bit();
861 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
862 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
863 const bool Is64BitILP32 = STI.isTarget64BitILP32();
864 bool UseLEA = STI.useLeaForSP();
865 unsigned StackAlign = getStackAlignment();
866 unsigned SlotSize = RegInfo->getSlotSize();
867 unsigned FramePtr = RegInfo->getFrameRegister(MF);
868 unsigned MachineFramePtr = Is64BitILP32 ?
869 getX86SubSuperRegister(FramePtr, MVT::i64, false) : FramePtr;
870 unsigned StackPtr = RegInfo->getStackRegister();
873 MF.getTarget().getMCAsmInfo()->getExceptionHandlingType() ==
874 ExceptionHandling::WinEH;
875 bool NeedsWinEH = IsWinEH && MF.getFunction()->needsUnwindTableEntry();
879 llvm_unreachable("Can only insert epilog into returning blocks");
884 case X86::TCRETURNdi:
885 case X86::TCRETURNri:
886 case X86::TCRETURNmi:
887 case X86::TCRETURNdi64:
888 case X86::TCRETURNri64:
889 case X86::TCRETURNmi64:
891 case X86::EH_RETURN64:
892 break; // These are ok
895 // Get the number of bytes to allocate from the FrameInfo.
896 uint64_t StackSize = MFI->getStackSize();
897 uint64_t MaxAlign = MFI->getMaxAlignment();
898 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
899 uint64_t NumBytes = 0;
901 // If we're forcing a stack realignment we can't rely on just the frame
902 // info, we need to know the ABI stack alignment as well in case we
903 // have a call out. Otherwise just make sure we have some alignment - we'll
904 // go with the minimum.
905 if (ForceStackAlign) {
907 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
909 MaxAlign = MaxAlign ? MaxAlign : 4;
913 // Calculate required stack adjustment.
914 uint64_t FrameSize = StackSize - SlotSize;
915 if (RegInfo->needsStackRealignment(MF)) {
916 // Callee-saved registers were pushed on stack before the stack
919 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
921 NumBytes = FrameSize - CSSize;
925 BuildMI(MBB, MBBI, DL,
926 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
928 NumBytes = StackSize - CSSize;
931 // Skip the callee-saved pop instructions.
932 while (MBBI != MBB.begin()) {
933 MachineBasicBlock::iterator PI = std::prev(MBBI);
934 unsigned Opc = PI->getOpcode();
936 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
942 MachineBasicBlock::iterator FirstCSPop = MBBI;
944 DL = MBBI->getDebugLoc();
946 // If there is an ADD32ri or SUB32ri of ESP immediately before this
947 // instruction, merge the two instructions.
948 if (NumBytes || MFI->hasVarSizedObjects())
949 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
951 // If dynamic alloca is used, then reset esp to point to the last callee-saved
952 // slot before popping them off! Same applies for the case, when stack was
954 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
955 if (RegInfo->needsStackRealignment(MF))
958 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
959 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
960 FramePtr, false, -CSSize);
963 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
964 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
968 } else if (NumBytes) {
969 // Adjust stack pointer back: ESP += numbytes.
970 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, Uses64BitFramePtr, UseLEA,
975 // Windows unwinder will not invoke function's exception handler if IP is
976 // either in prologue or in epilogue. This behavior causes a problem when a
977 // call immediately precedes an epilogue, because the return address points
978 // into the epilogue. To cope with that, we insert an epilogue marker here,
979 // then replace it with a 'nop' if it ends up immediately after a CALL in the
980 // final emitted code.
982 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
984 // We're returning from function via eh_return.
985 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
986 MBBI = MBB.getLastNonDebugInstr();
987 MachineOperand &DestAddr = MBBI->getOperand(0);
988 assert(DestAddr.isReg() && "Offset should be in register!");
989 BuildMI(MBB, MBBI, DL,
990 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
991 StackPtr).addReg(DestAddr.getReg());
992 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
993 RetOpcode == X86::TCRETURNmi ||
994 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
995 RetOpcode == X86::TCRETURNmi64) {
996 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
997 // Tail call return: adjust the stack pointer and jump to callee.
998 MBBI = MBB.getLastNonDebugInstr();
999 MachineOperand &JumpTarget = MBBI->getOperand(0);
1000 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1001 assert(StackAdjust.isImm() && "Expecting immediate value.");
1003 // Adjust stack pointer.
1004 int StackAdj = StackAdjust.getImm();
1005 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1007 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1009 // Incoporate the retaddr area.
1010 Offset = StackAdj-MaxTCDelta;
1011 assert(Offset >= 0 && "Offset should never be negative");
1014 // Check for possible merge with preceding ADD instruction.
1015 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1016 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, Uses64BitFramePtr,
1017 UseLEA, TII, *RegInfo);
1020 // Jump to label or value in register.
1021 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1022 MachineInstrBuilder MIB =
1023 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1024 ? X86::TAILJMPd : X86::TAILJMPd64));
1025 if (JumpTarget.isGlobal())
1026 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1027 JumpTarget.getTargetFlags());
1029 assert(JumpTarget.isSymbol());
1030 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1031 JumpTarget.getTargetFlags());
1033 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1034 MachineInstrBuilder MIB =
1035 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1036 ? X86::TAILJMPm : X86::TAILJMPm64));
1037 for (unsigned i = 0; i != 5; ++i)
1038 MIB.addOperand(MBBI->getOperand(i));
1039 } else if (RetOpcode == X86::TCRETURNri64) {
1040 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1041 addReg(JumpTarget.getReg(), RegState::Kill);
1043 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1044 addReg(JumpTarget.getReg(), RegState::Kill);
1047 MachineInstr *NewMI = std::prev(MBBI);
1048 NewMI->copyImplicitOps(MF, MBBI);
1050 // Delete the pseudo instruction TCRETURN.
1052 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
1053 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
1054 (X86FI->getTCReturnAddrDelta() < 0)) {
1055 // Add the return addr area delta back since we are not tail calling.
1056 int delta = -1*X86FI->getTCReturnAddrDelta();
1057 MBBI = MBB.getLastNonDebugInstr();
1059 // Check for possible merge with preceding ADD instruction.
1060 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1061 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, Uses64BitFramePtr, UseLEA, TII,
1066 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1068 const X86RegisterInfo *RegInfo =
1069 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1070 const MachineFrameInfo *MFI = MF.getFrameInfo();
1071 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1072 uint64_t StackSize = MFI->getStackSize();
1074 if (RegInfo->hasBasePointer(MF)) {
1075 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1077 // Skip the saved EBP.
1078 return Offset + RegInfo->getSlotSize();
1080 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1081 return Offset + StackSize;
1083 } else if (RegInfo->needsStackRealignment(MF)) {
1085 // Skip the saved EBP.
1086 return Offset + RegInfo->getSlotSize();
1088 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1089 return Offset + StackSize;
1091 // FIXME: Support tail calls
1094 return Offset + StackSize;
1096 // Skip the saved EBP.
1097 Offset += RegInfo->getSlotSize();
1099 // Skip the RETADDR move area
1100 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1101 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1102 if (TailCallReturnAddrDelta < 0)
1103 Offset -= TailCallReturnAddrDelta;
1109 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1110 unsigned &FrameReg) const {
1111 const X86RegisterInfo *RegInfo =
1112 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1113 // We can't calculate offset from frame pointer if the stack is realigned,
1114 // so enforce usage of stack/base pointer. The base pointer is used when we
1115 // have dynamic allocas in addition to dynamic realignment.
1116 if (RegInfo->hasBasePointer(MF))
1117 FrameReg = RegInfo->getBaseRegister();
1118 else if (RegInfo->needsStackRealignment(MF))
1119 FrameReg = RegInfo->getStackRegister();
1121 FrameReg = RegInfo->getFrameRegister(MF);
1122 return getFrameIndexOffset(MF, FI);
1125 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1126 MachineFunction &MF, const TargetRegisterInfo *TRI,
1127 std::vector<CalleeSavedInfo> &CSI) const {
1128 MachineFrameInfo *MFI = MF.getFrameInfo();
1129 const X86RegisterInfo *RegInfo =
1130 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1131 unsigned SlotSize = RegInfo->getSlotSize();
1132 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1134 unsigned CalleeSavedFrameSize = 0;
1135 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1138 // emitPrologue always spills frame register the first thing.
1139 SpillSlotOffset -= SlotSize;
1140 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1142 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1143 // the frame register, we can delete it from CSI list and not have to worry
1144 // about avoiding it later.
1145 unsigned FPReg = RegInfo->getFrameRegister(MF);
1146 for (unsigned i = 0; i < CSI.size(); ++i) {
1147 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1148 CSI.erase(CSI.begin() + i);
1154 // Assign slots for GPRs. It increases frame size.
1155 for (unsigned i = CSI.size(); i != 0; --i) {
1156 unsigned Reg = CSI[i - 1].getReg();
1158 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1161 SpillSlotOffset -= SlotSize;
1162 CalleeSavedFrameSize += SlotSize;
1164 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1165 CSI[i - 1].setFrameIdx(SlotIndex);
1168 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1170 // Assign slots for XMMs.
1171 for (unsigned i = CSI.size(); i != 0; --i) {
1172 unsigned Reg = CSI[i - 1].getReg();
1173 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1176 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
1178 SpillSlotOffset -= abs(SpillSlotOffset) % RC->getAlignment();
1180 SpillSlotOffset -= RC->getSize();
1182 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1183 CSI[i - 1].setFrameIdx(SlotIndex);
1184 MFI->ensureMaxAlignment(RC->getAlignment());
1190 bool X86FrameLowering::spillCalleeSavedRegisters(
1191 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1192 const std::vector<CalleeSavedInfo> &CSI,
1193 const TargetRegisterInfo *TRI) const {
1194 DebugLoc DL = MBB.findDebugLoc(MI);
1196 MachineFunction &MF = *MBB.getParent();
1197 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1198 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1200 // Push GPRs. It increases frame size.
1201 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1202 for (unsigned i = CSI.size(); i != 0; --i) {
1203 unsigned Reg = CSI[i - 1].getReg();
1205 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1207 // Add the callee-saved register as live-in. It's killed at the spill.
1210 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1211 .setMIFlag(MachineInstr::FrameSetup);
1214 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1215 // It can be done by spilling XMMs to stack frame.
1216 for (unsigned i = CSI.size(); i != 0; --i) {
1217 unsigned Reg = CSI[i-1].getReg();
1218 if (X86::GR64RegClass.contains(Reg) ||
1219 X86::GR32RegClass.contains(Reg))
1221 // Add the callee-saved register as live-in. It's killed at the spill.
1223 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1225 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1228 MI->setFlag(MachineInstr::FrameSetup);
1235 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1236 MachineBasicBlock::iterator MI,
1237 const std::vector<CalleeSavedInfo> &CSI,
1238 const TargetRegisterInfo *TRI) const {
1242 DebugLoc DL = MBB.findDebugLoc(MI);
1244 MachineFunction &MF = *MBB.getParent();
1245 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1246 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1248 // Reload XMMs from stack frame.
1249 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1250 unsigned Reg = CSI[i].getReg();
1251 if (X86::GR64RegClass.contains(Reg) ||
1252 X86::GR32RegClass.contains(Reg))
1255 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1256 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1260 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1261 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1262 unsigned Reg = CSI[i].getReg();
1263 if (!X86::GR64RegClass.contains(Reg) &&
1264 !X86::GR32RegClass.contains(Reg))
1267 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1273 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1274 RegScavenger *RS) const {
1275 MachineFrameInfo *MFI = MF.getFrameInfo();
1276 const X86RegisterInfo *RegInfo =
1277 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1278 unsigned SlotSize = RegInfo->getSlotSize();
1280 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1281 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1283 if (TailCallReturnAddrDelta < 0) {
1284 // create RETURNADDR area
1293 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1294 TailCallReturnAddrDelta - SlotSize, true);
1297 // Spill the BasePtr if it's used.
1298 if (RegInfo->hasBasePointer(MF))
1299 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1303 HasNestArgument(const MachineFunction *MF) {
1304 const Function *F = MF->getFunction();
1305 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1307 if (I->hasNestAttr())
1313 /// GetScratchRegister - Get a temp register for performing work in the
1314 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1315 /// and the properties of the function either one or two registers will be
1316 /// needed. Set primary to true for the first register, false for the second.
1318 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1319 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1322 if (CallingConvention == CallingConv::HiPE) {
1324 return Primary ? X86::R14 : X86::R13;
1326 return Primary ? X86::EBX : X86::EDI;
1330 return Primary ? X86::R11 : X86::R12;
1332 bool IsNested = HasNestArgument(&MF);
1334 if (CallingConvention == CallingConv::X86_FastCall ||
1335 CallingConvention == CallingConv::Fast) {
1337 report_fatal_error("Segmented stacks does not support fastcall with "
1338 "nested function.");
1339 return Primary ? X86::EAX : X86::ECX;
1342 return Primary ? X86::EDX : X86::EAX;
1343 return Primary ? X86::ECX : X86::EAX;
1346 // The stack limit in the TCB is set to this many bytes above the actual stack
1348 static const uint64_t kSplitStackAvailable = 256;
1351 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1352 MachineBasicBlock &prologueMBB = MF.front();
1353 MachineFrameInfo *MFI = MF.getFrameInfo();
1354 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1356 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1357 bool Is64Bit = STI.is64Bit();
1358 unsigned TlsReg, TlsOffset;
1361 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1362 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1363 "Scratch register is live-in");
1365 if (MF.getFunction()->isVarArg())
1366 report_fatal_error("Segmented stacks do not support vararg functions.");
1367 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1368 !STI.isTargetWin32() && !STI.isTargetWin64() && !STI.isTargetFreeBSD())
1369 report_fatal_error("Segmented stacks not supported on this platform.");
1371 // Eventually StackSize will be calculated by a link-time pass; which will
1372 // also decide whether checking code needs to be injected into this particular
1374 StackSize = MFI->getStackSize();
1376 // Do not generate a prologue for functions with a stack of size zero
1380 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1381 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1382 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1383 bool IsNested = false;
1385 // We need to know if the function has a nest argument only in 64 bit mode.
1387 IsNested = HasNestArgument(&MF);
1389 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1390 // allocMBB needs to be last (terminating) instruction.
1392 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1393 e = prologueMBB.livein_end(); i != e; i++) {
1394 allocMBB->addLiveIn(*i);
1395 checkMBB->addLiveIn(*i);
1399 allocMBB->addLiveIn(X86::R10);
1401 MF.push_front(allocMBB);
1402 MF.push_front(checkMBB);
1404 // When the frame size is less than 256 we just compare the stack
1405 // boundary directly to the value of the stack pointer, per gcc.
1406 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1408 // Read the limit off the current stacklet off the stack_guard location.
1410 if (STI.isTargetLinux()) {
1413 } else if (STI.isTargetDarwin()) {
1415 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1416 } else if (STI.isTargetWin64()) {
1418 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1419 } else if (STI.isTargetFreeBSD()) {
1423 report_fatal_error("Segmented stacks not supported on this platform.");
1426 if (CompareStackPointer)
1427 ScratchReg = X86::RSP;
1429 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1430 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1432 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1433 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1435 if (STI.isTargetLinux()) {
1438 } else if (STI.isTargetDarwin()) {
1440 TlsOffset = 0x48 + 90*4;
1441 } else if (STI.isTargetWin32()) {
1443 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1444 } else if (STI.isTargetFreeBSD()) {
1445 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1447 report_fatal_error("Segmented stacks not supported on this platform.");
1450 if (CompareStackPointer)
1451 ScratchReg = X86::ESP;
1453 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1454 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1456 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64()) {
1457 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1458 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1459 } else if (STI.isTargetDarwin()) {
1461 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1462 unsigned ScratchReg2;
1464 if (CompareStackPointer) {
1465 // The primary scratch register is available for holding the TLS offset.
1466 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1467 SaveScratch2 = false;
1469 // Need to use a second register to hold the TLS offset
1470 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1472 // Unfortunately, with fastcc the second scratch register may hold an
1474 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1477 // If Scratch2 is live-in then it needs to be saved.
1478 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1479 "Scratch register is live-in and not saved");
1482 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1483 .addReg(ScratchReg2, RegState::Kill);
1485 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1487 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1489 .addReg(ScratchReg2).addImm(1).addReg(0)
1494 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1498 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1499 // It jumps to normal execution of the function body.
1500 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1502 // On 32 bit we first push the arguments size and then the frame size. On 64
1503 // bit, we pass the stack frame size in r10 and the argument size in r11.
1505 // Functions with nested arguments use R10, so it needs to be saved across
1506 // the call to _morestack
1509 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1511 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1513 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1514 .addImm(X86FI->getArgumentStackSize());
1515 MF.getRegInfo().setPhysRegUsed(X86::R10);
1516 MF.getRegInfo().setPhysRegUsed(X86::R11);
1518 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1519 .addImm(X86FI->getArgumentStackSize());
1520 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1524 // __morestack is in libgcc
1526 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1527 .addExternalSymbol("__morestack");
1529 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1530 .addExternalSymbol("__morestack");
1533 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1535 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1537 allocMBB->addSuccessor(&prologueMBB);
1539 checkMBB->addSuccessor(allocMBB);
1540 checkMBB->addSuccessor(&prologueMBB);
1547 /// Erlang programs may need a special prologue to handle the stack size they
1548 /// might need at runtime. That is because Erlang/OTP does not implement a C
1549 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1550 /// (for more information see Eric Stenman's Ph.D. thesis:
1551 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1554 /// temp0 = sp - MaxStack
1555 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1559 /// call inc_stack # doubles the stack space
1560 /// temp0 = sp - MaxStack
1561 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1562 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1563 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1564 MachineFrameInfo *MFI = MF.getFrameInfo();
1565 const unsigned SlotSize =
1566 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo())
1568 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1569 const bool Is64Bit = STI.is64Bit();
1571 // HiPE-specific values
1572 const unsigned HipeLeafWords = 24;
1573 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1574 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1575 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1576 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1577 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1579 assert(STI.isTargetLinux() &&
1580 "HiPE prologue is only supported on Linux operating systems.");
1582 // Compute the largest caller's frame that is needed to fit the callees'
1583 // frames. This 'MaxStack' is computed from:
1585 // a) the fixed frame size, which is the space needed for all spilled temps,
1586 // b) outgoing on-stack parameter areas, and
1587 // c) the minimum stack space this function needs to make available for the
1588 // functions it calls (a tunable ABI property).
1589 if (MFI->hasCalls()) {
1590 unsigned MoreStackForCalls = 0;
1592 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1593 MBBI != MBBE; ++MBBI)
1594 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1599 // Get callee operand.
1600 const MachineOperand &MO = MI->getOperand(0);
1602 // Only take account of global function calls (no closures etc.).
1606 const Function *F = dyn_cast<Function>(MO.getGlobal());
1610 // Do not update 'MaxStack' for primitive and built-in functions
1611 // (encoded with names either starting with "erlang."/"bif_" or not
1612 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1613 // "_", such as the BIF "suspend_0") as they are executed on another
1615 if (F->getName().find("erlang.") != StringRef::npos ||
1616 F->getName().find("bif_") != StringRef::npos ||
1617 F->getName().find_first_of("._") == StringRef::npos)
1620 unsigned CalleeStkArity =
1621 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1622 if (HipeLeafWords - 1 > CalleeStkArity)
1623 MoreStackForCalls = std::max(MoreStackForCalls,
1624 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1626 MaxStack += MoreStackForCalls;
1629 // If the stack frame needed is larger than the guaranteed then runtime checks
1630 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1631 if (MaxStack > Guaranteed) {
1632 MachineBasicBlock &prologueMBB = MF.front();
1633 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1634 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1636 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1637 E = prologueMBB.livein_end(); I != E; I++) {
1638 stackCheckMBB->addLiveIn(*I);
1639 incStackMBB->addLiveIn(*I);
1642 MF.push_front(incStackMBB);
1643 MF.push_front(stackCheckMBB);
1645 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1646 unsigned LEAop, CMPop, CALLop;
1650 LEAop = X86::LEA64r;
1651 CMPop = X86::CMP64rm;
1652 CALLop = X86::CALL64pcrel32;
1653 SPLimitOffset = 0x90;
1657 LEAop = X86::LEA32r;
1658 CMPop = X86::CMP32rm;
1659 CALLop = X86::CALLpcrel32;
1660 SPLimitOffset = 0x4c;
1663 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1664 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1665 "HiPE prologue scratch register is live-in");
1667 // Create new MBB for StackCheck:
1668 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1669 SPReg, false, -MaxStack);
1670 // SPLimitOffset is in a fixed heap location (pointed by BP).
1671 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1672 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1673 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1675 // Create new MBB for IncStack:
1676 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1677 addExternalSymbol("inc_stack_0");
1678 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1679 SPReg, false, -MaxStack);
1680 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1681 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1682 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1684 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1685 stackCheckMBB->addSuccessor(incStackMBB, 1);
1686 incStackMBB->addSuccessor(&prologueMBB, 99);
1687 incStackMBB->addSuccessor(incStackMBB, 1);
1694 void X86FrameLowering::
1695 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1696 MachineBasicBlock::iterator I) const {
1697 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1698 const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>(
1699 MF.getSubtarget().getRegisterInfo());
1700 unsigned StackPtr = RegInfo.getStackRegister();
1701 bool reseveCallFrame = hasReservedCallFrame(MF);
1702 int Opcode = I->getOpcode();
1703 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1704 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1705 bool IsLP64 = STI.isTarget64BitLP64();
1706 DebugLoc DL = I->getDebugLoc();
1707 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
1708 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1711 if (!reseveCallFrame) {
1712 // If the stack pointer can be changed after prologue, turn the
1713 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1714 // adjcallstackdown instruction into 'add ESP, <amt>'
1715 // TODO: consider using push / pop instead of sub + store / add
1719 // We need to keep the stack aligned properly. To do this, we round the
1720 // amount of space needed for the outgoing arguments up to the next
1721 // alignment boundary.
1722 unsigned StackAlign = MF.getTarget()
1724 ->getFrameLowering()
1725 ->getStackAlignment();
1726 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1728 MachineInstr *New = nullptr;
1729 if (Opcode == TII.getCallFrameSetupOpcode()) {
1730 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1735 assert(Opcode == TII.getCallFrameDestroyOpcode());
1737 // Factor out the amount the callee already popped.
1738 Amount -= CalleeAmt;
1741 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1742 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1743 .addReg(StackPtr).addImm(Amount);
1748 // The EFLAGS implicit def is dead.
1749 New->getOperand(3).setIsDead();
1751 // Replace the pseudo instruction with a new instruction.
1758 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1759 // If we are performing frame pointer elimination and if the callee pops
1760 // something off the stack pointer, add it back. We do this until we have
1761 // more advanced stack pointer tracking ability.
1762 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1763 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1764 .addReg(StackPtr).addImm(CalleeAmt);
1766 // The EFLAGS implicit def is dead.
1767 New->getOperand(3).setIsDead();
1769 // We are not tracking the stack pointer adjustment by the callee, so make
1770 // sure we restore the stack pointer immediately after the call, there may
1771 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1772 MachineBasicBlock::iterator B = MBB.begin();
1773 while (I != B && !std::prev(I)->isCall())