1 //=======- X86FrameLowering.cpp - X86 Frame Information --------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/ADT/SmallSet.h"
35 // FIXME: completely move here.
36 extern cl::opt<bool> ForceStackAlign;
38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
39 return !MF.getFrameInfo()->hasVarSizedObjects();
42 /// hasFP - Return true if the specified function should have a dedicated frame
43 /// pointer register. This is true if the function has variable sized allocas
44 /// or if frame pointer elimination is disabled.
45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 const MachineModuleInfo &MMI = MF.getMMI();
48 const TargetRegisterInfo *RI = TM.getRegisterInfo();
50 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
51 RI->needsStackRealignment(MF) ||
52 MFI->hasVarSizedObjects() ||
53 MFI->isFrameAddressTaken() ||
54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
55 MMI.callsUnwindInit());
58 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
62 return X86::SUB64ri32;
70 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
74 return X86::ADD64ri32;
82 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
83 /// when it reaches the "return" instruction. We can then pop a stack object
84 /// to this register without worry about clobbering it.
85 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator &MBBI,
87 const TargetRegisterInfo &TRI,
89 const MachineFunction *MF = MBB.getParent();
90 const Function *F = MF->getFunction();
91 if (!F || MF->getMMI().callsEHReturn())
94 static const unsigned CallerSavedRegs32Bit[] = {
95 X86::EAX, X86::EDX, X86::ECX, 0
98 static const unsigned CallerSavedRegs64Bit[] = {
99 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
100 X86::R8, X86::R9, X86::R10, X86::R11, 0
103 unsigned Opc = MBBI->getOpcode();
108 case X86::TCRETURNdi:
109 case X86::TCRETURNri:
110 case X86::TCRETURNmi:
111 case X86::TCRETURNdi64:
112 case X86::TCRETURNri64:
113 case X86::TCRETURNmi64:
115 case X86::EH_RETURN64: {
116 SmallSet<unsigned, 8> Uses;
117 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
118 MachineOperand &MO = MBBI->getOperand(i);
119 if (!MO.isReg() || MO.isDef())
121 unsigned Reg = MO.getReg();
124 for (const unsigned *AsI = TRI.getOverlaps(Reg); *AsI; ++AsI)
128 const unsigned *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
130 if (!Uses.count(*CS))
139 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
140 /// stack pointer by a constant value.
142 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
143 unsigned StackPtr, int64_t NumBytes,
144 bool Is64Bit, const TargetInstrInfo &TII,
145 const TargetRegisterInfo &TRI) {
146 bool isSub = NumBytes < 0;
147 uint64_t Offset = isSub ? -NumBytes : NumBytes;
148 unsigned Opc = isSub ?
149 getSUBriOpcode(Is64Bit, Offset) :
150 getADDriOpcode(Is64Bit, Offset);
151 uint64_t Chunk = (1LL << 31) - 1;
152 DebugLoc DL = MBB.findDebugLoc(MBBI);
155 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
156 if (ThisVal == (Is64Bit ? 8 : 4)) {
157 // Use push / pop instead.
159 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
160 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
163 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
164 : (Is64Bit ? X86::POP64r : X86::POP32r);
165 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
166 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
168 MI->setFlag(MachineInstr::FrameSetup);
175 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
179 MI->setFlag(MachineInstr::FrameSetup);
180 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
185 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
187 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
188 unsigned StackPtr, uint64_t *NumBytes = NULL) {
189 if (MBBI == MBB.begin()) return;
191 MachineBasicBlock::iterator PI = prior(MBBI);
192 unsigned Opc = PI->getOpcode();
193 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
194 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
195 PI->getOperand(0).getReg() == StackPtr) {
197 *NumBytes += PI->getOperand(2).getImm();
199 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
200 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
201 PI->getOperand(0).getReg() == StackPtr) {
203 *NumBytes -= PI->getOperand(2).getImm();
208 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
210 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
211 MachineBasicBlock::iterator &MBBI,
212 unsigned StackPtr, uint64_t *NumBytes = NULL) {
213 // FIXME: THIS ISN'T RUN!!!
216 if (MBBI == MBB.end()) return;
218 MachineBasicBlock::iterator NI = llvm::next(MBBI);
219 if (NI == MBB.end()) return;
221 unsigned Opc = NI->getOpcode();
222 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
223 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
224 NI->getOperand(0).getReg() == StackPtr) {
226 *NumBytes -= NI->getOperand(2).getImm();
229 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
230 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
231 NI->getOperand(0).getReg() == StackPtr) {
233 *NumBytes += NI->getOperand(2).getImm();
239 /// mergeSPUpdates - Checks the instruction before/after the passed
240 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
241 /// stack adjustment is returned as a positive value for ADD and a negative for
243 static int mergeSPUpdates(MachineBasicBlock &MBB,
244 MachineBasicBlock::iterator &MBBI,
246 bool doMergeWithPrevious) {
247 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
248 (!doMergeWithPrevious && MBBI == MBB.end()))
251 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
252 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
253 unsigned Opc = PI->getOpcode();
256 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
257 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
258 PI->getOperand(0).getReg() == StackPtr){
259 Offset += PI->getOperand(2).getImm();
261 if (!doMergeWithPrevious) MBBI = NI;
262 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
263 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
264 PI->getOperand(0).getReg() == StackPtr) {
265 Offset -= PI->getOperand(2).getImm();
267 if (!doMergeWithPrevious) MBBI = NI;
273 static bool isEAXLiveIn(MachineFunction &MF) {
274 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
275 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
276 unsigned Reg = II->first;
278 if (Reg == X86::EAX || Reg == X86::AX ||
279 Reg == X86::AH || Reg == X86::AL)
286 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
288 unsigned FramePtr) const {
289 MachineFrameInfo *MFI = MF.getFrameInfo();
290 MachineModuleInfo &MMI = MF.getMMI();
292 // Add callee saved registers to move list.
293 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
294 if (CSI.empty()) return;
296 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
297 const TargetData *TD = TM.getTargetData();
298 bool HasFP = hasFP(MF);
300 // Calculate amount of bytes used for return address storing.
301 int stackGrowth = -TD->getPointerSize();
303 // FIXME: This is dirty hack. The code itself is pretty mess right now.
304 // It should be rewritten from scratch and generalized sometimes.
306 // Determine maximum offset (minimum due to stack growth).
307 int64_t MaxOffset = 0;
308 for (std::vector<CalleeSavedInfo>::const_iterator
309 I = CSI.begin(), E = CSI.end(); I != E; ++I)
310 MaxOffset = std::min(MaxOffset,
311 MFI->getObjectOffset(I->getFrameIdx()));
313 // Calculate offsets.
314 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
315 for (std::vector<CalleeSavedInfo>::const_iterator
316 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
317 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
318 unsigned Reg = I->getReg();
319 Offset = MaxOffset - Offset + saveAreaOffset;
321 // Don't output a new machine move if we're re-saving the frame
322 // pointer. This happens when the PrologEpilogInserter has inserted an extra
323 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
324 // generates one when frame pointers are used. If we generate a "machine
325 // move" for this extra "PUSH", the linker will lose track of the fact that
326 // the frame pointer should have the value of the first "PUSH" when it's
329 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
330 // another bug. I.e., one where we generate a prolog like this:
338 // The immediate re-push of EBP is unnecessary. At the least, it's an
339 // optimization bug. EBP can be used as a scratch register in certain
340 // cases, but probably not when we have a frame pointer.
341 if (HasFP && FramePtr == Reg)
344 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
345 MachineLocation CSSrc(Reg);
346 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
350 /// getCompactUnwindRegNum - Get the compact unwind number for a given
351 /// register. The number corresponds to the enum lists in
352 /// compact_unwind_encoding.h.
353 static int getCompactUnwindRegNum(const unsigned *CURegs, unsigned Reg) {
354 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
361 // Number of registers that can be saved in a compact unwind encoding.
362 #define CU_NUM_SAVED_REGS 6
364 /// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding
365 /// used with frameless stacks. It is passed the number of registers to be saved
366 /// and an array of the registers saved.
368 encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
369 unsigned RegCount, bool Is64Bit) {
370 // The saved registers are numbered from 1 to 6. In order to encode the order
371 // in which they were saved, we re-number them according to their place in the
372 // register order. The re-numbering is relative to the last re-numbered
373 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
382 static const unsigned CU32BitRegs[] = {
383 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
385 static const unsigned CU64BitRegs[] = {
386 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
388 const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
390 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
391 int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]);
392 if (CUReg == -1) return ~0U;
393 SavedRegs[i] = CUReg;
397 std::swap(SavedRegs[0], SavedRegs[5]);
398 std::swap(SavedRegs[1], SavedRegs[4]);
399 std::swap(SavedRegs[2], SavedRegs[3]);
401 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
402 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i) {
403 unsigned Countless = 0;
404 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
405 if (SavedRegs[j] < SavedRegs[i])
408 RenumRegs[i] = SavedRegs[i] - Countless - 1;
411 // Take the renumbered values and encode them into a 10-bit number.
412 uint32_t permutationEncoding = 0;
415 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
416 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
420 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
421 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
425 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
426 + 3 * RenumRegs[4] + RenumRegs[5];
429 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
433 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
436 permutationEncoding |= RenumRegs[5];
440 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
441 "Invalid compact register encoding!");
442 return permutationEncoding;
445 /// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a
446 /// compact encoding with a frame pointer.
448 encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
450 static const unsigned CU32BitRegs[] = {
451 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
453 static const unsigned CU64BitRegs[] = {
454 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
456 const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
458 // FIXME: The code below is WRONG and breaks tests on i386, see
459 // SingleSource/Regression/C++/EH/ctor_dtor_count.exec
460 // SingleSource/Regression/C++/EH/exception_spec_test.exec
461 // SingleSource/Regression/C++/EH/function_try_block.exec
462 // SingleSource/Regression/C++/EH/throw_rethrow_test.exec
465 // Encode the registers in the order they were saved, 3-bits per register. The
466 // registers are numbered from 1 to 6.
468 for (int I = 0; I != 6; ++I) {
469 unsigned Reg = SavedRegs[I];
471 int CURegNum = getCompactUnwindRegNum(CURegs, Reg);
475 // Encode the 3-bit register number in order, skipping over 3-bits for each
477 RegEnc |= (CURegNum & 0x7) << ((5 - I) * 3);
480 assert((RegEnc & 0x3FFFF) == RegEnc && "Invalid compact register encoding!");
484 uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const {
485 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
486 unsigned FramePtr = RegInfo->getFrameRegister(MF);
487 unsigned StackPtr = RegInfo->getStackRegister();
489 bool Is64Bit = STI.is64Bit();
490 bool HasFP = hasFP(MF);
492 unsigned SavedRegs[CU_NUM_SAVED_REGS] = { 0, 0, 0, 0, 0, 0 };
493 unsigned SavedRegIdx = 0;
495 unsigned OffsetSize = (Is64Bit ? 8 : 4);
497 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
498 unsigned PushInstrSize = 1;
499 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
500 unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
501 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
503 unsigned StackDivide = (Is64Bit ? 8 : 4);
505 unsigned InstrOffset = 0;
506 unsigned StackAdjust = 0;
507 unsigned StackSize = 0;
509 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB.
510 bool ExpectEnd = false;
511 for (MachineBasicBlock::iterator
512 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) {
513 MachineInstr &MI = *MBBI;
514 unsigned Opc = MI.getOpcode();
515 if (Opc == X86::PROLOG_LABEL) continue;
516 if (!MI.getFlag(MachineInstr::FrameSetup)) break;
518 // We don't exect any more prolog instructions.
519 if (ExpectEnd) return 0;
521 if (Opc == PushInstr) {
522 // If there are too many saved registers, we cannot use compact encoding.
523 if (SavedRegIdx >= CU_NUM_SAVED_REGS) return 0;
525 SavedRegs[SavedRegIdx++] = MI.getOperand(0).getReg();
526 StackAdjust += OffsetSize;
527 InstrOffset += PushInstrSize;
528 } else if (Opc == MoveInstr) {
529 unsigned SrcReg = MI.getOperand(1).getReg();
530 unsigned DstReg = MI.getOperand(0).getReg();
532 if (DstReg != FramePtr || SrcReg != StackPtr)
536 memset(SavedRegs, 0, sizeof(SavedRegs));
538 InstrOffset += MoveInstrSize;
539 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
540 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
542 // We already have a stack size.
545 if (!MI.getOperand(0).isReg() ||
546 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() ||
547 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm())
548 // We need this to be a stack adjustment pointer. Something like:
550 // %RSP<def> = SUB64ri8 %RSP, 48
553 StackSize = MI.getOperand(2).getImm() / StackDivide;
554 SubtractInstrIdx += InstrOffset;
559 // Encode that we are using EBP/RBP as the frame pointer.
560 uint32_t CompactUnwindEncoding = 0;
561 StackAdjust /= StackDivide;
563 if ((StackAdjust & 0xFF) != StackAdjust)
564 // Offset was too big for compact encoding.
567 // Get the encoding of the saved registers when we have a frame pointer.
568 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
569 if (RegEnc == ~0U) return 0;
571 CompactUnwindEncoding |= 0x01000000;
572 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
573 CompactUnwindEncoding |= RegEnc & 0x7FFF;
576 uint32_t TotalStackSize = StackAdjust + StackSize;
577 if ((TotalStackSize & 0xFF) == TotalStackSize) {
578 // Frameless stack with a small stack size.
579 CompactUnwindEncoding |= 0x02000000;
581 // Encode the stack size.
582 CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16;
584 if ((StackAdjust & 0x7) != StackAdjust)
585 // The extra stack adjustments are too big for us to handle.
588 // Frameless stack with an offset too large for us to encode compactly.
589 CompactUnwindEncoding |= 0x03000000;
591 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
593 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
595 // Encode any extra stack stack adjustments (done via push instructions).
596 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
599 // Encode the number of registers saved.
600 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
602 // Get the encoding of the saved registers when we don't have a frame
605 encodeCompactUnwindRegistersWithoutFrame(SavedRegs, SavedRegIdx,
607 if (RegEnc == ~0U) return 0;
609 // Encode the register encoding.
610 CompactUnwindEncoding |= RegEnc & 0x3FF;
613 return CompactUnwindEncoding;
616 /// emitPrologue - Push callee-saved registers onto the stack, which
617 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
618 /// space for local variables. Also emit labels used by the exception handler to
619 /// generate the exception handling frames.
620 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
621 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
622 MachineBasicBlock::iterator MBBI = MBB.begin();
623 MachineFrameInfo *MFI = MF.getFrameInfo();
624 const Function *Fn = MF.getFunction();
625 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
626 const X86InstrInfo &TII = *TM.getInstrInfo();
627 MachineModuleInfo &MMI = MF.getMMI();
628 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
629 bool needsFrameMoves = MMI.hasDebugInfo() ||
630 Fn->needsUnwindTableEntry();
631 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
632 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
633 bool HasFP = hasFP(MF);
634 bool Is64Bit = STI.is64Bit();
635 bool IsWin64 = STI.isTargetWin64();
636 unsigned StackAlign = getStackAlignment();
637 unsigned SlotSize = RegInfo->getSlotSize();
638 unsigned FramePtr = RegInfo->getFrameRegister(MF);
639 unsigned StackPtr = RegInfo->getStackRegister();
642 // If we're forcing a stack realignment we can't rely on just the frame
643 // info, we need to know the ABI stack alignment as well in case we
644 // have a call out. Otherwise just make sure we have some alignment - we'll
645 // go with the minimum SlotSize.
646 if (ForceStackAlign) {
648 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
649 else if (MaxAlign < SlotSize)
653 // Add RETADDR move area to callee saved frame size.
654 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
655 if (TailCallReturnAddrDelta < 0)
656 X86FI->setCalleeSavedFrameSize(
657 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
659 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
660 // function, and use up to 128 bytes of stack space, don't have a frame
661 // pointer, calls, or dynamic alloca then we do not need to adjust the
662 // stack pointer (we fit in the Red Zone).
663 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
664 !RegInfo->needsStackRealignment(MF) &&
665 !MFI->hasVarSizedObjects() && // No dynamic alloca.
666 !MFI->adjustsStack() && // No calls.
667 !IsWin64 && // Win64 has no Red Zone
668 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack
669 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
670 if (HasFP) MinSize += SlotSize;
671 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
672 MFI->setStackSize(StackSize);
675 // Insert stack pointer adjustment for later moving of return addr. Only
676 // applies to tail call optimized functions where the callee argument stack
677 // size is bigger than the callers.
678 if (TailCallReturnAddrDelta < 0) {
680 BuildMI(MBB, MBBI, DL,
681 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
684 .addImm(-TailCallReturnAddrDelta)
685 .setMIFlag(MachineInstr::FrameSetup);
686 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
689 // Mapping for machine moves:
691 // DST: VirtualFP AND
692 // SRC: VirtualFP => DW_CFA_def_cfa_offset
693 // ELSE => DW_CFA_def_cfa
695 // SRC: VirtualFP AND
696 // DST: Register => DW_CFA_def_cfa_register
699 // OFFSET < 0 => DW_CFA_offset_extended_sf
700 // REG < 64 => DW_CFA_offset + Reg
701 // ELSE => DW_CFA_offset_extended
703 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
704 const TargetData *TD = MF.getTarget().getTargetData();
705 uint64_t NumBytes = 0;
706 int stackGrowth = -TD->getPointerSize();
709 // Calculate required stack adjustment.
710 uint64_t FrameSize = StackSize - SlotSize;
711 if (RegInfo->needsStackRealignment(MF))
712 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
714 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
716 // Get the offset of the stack slot for the EBP register, which is
717 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
718 // Update the frame offset adjustment.
719 MFI->setOffsetAdjustment(-NumBytes);
721 // Save EBP/RBP into the appropriate stack slot.
722 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
723 .addReg(FramePtr, RegState::Kill)
724 .setMIFlag(MachineInstr::FrameSetup);
726 if (needsFrameMoves) {
727 // Mark the place where EBP/RBP was saved.
728 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
729 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
732 // Define the current CFA rule to use the provided offset.
734 MachineLocation SPDst(MachineLocation::VirtualFP);
735 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
736 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
738 MachineLocation SPDst(StackPtr);
739 MachineLocation SPSrc(StackPtr, stackGrowth);
740 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
743 // Change the rule for the FramePtr to be an "offset" rule.
744 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
745 MachineLocation FPSrc(FramePtr);
746 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
749 // Update EBP with the new base value.
750 BuildMI(MBB, MBBI, DL,
751 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
753 .setMIFlag(MachineInstr::FrameSetup);
755 if (needsFrameMoves) {
756 // Mark effective beginning of when frame pointer becomes valid.
757 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
758 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
761 // Define the current CFA to use the EBP/RBP register.
762 MachineLocation FPDst(FramePtr);
763 MachineLocation FPSrc(MachineLocation::VirtualFP);
764 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
767 // Mark the FramePtr as live-in in every block except the entry.
768 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
770 I->addLiveIn(FramePtr);
773 if (RegInfo->needsStackRealignment(MF)) {
775 BuildMI(MBB, MBBI, DL,
776 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
779 .setMIFlag(MachineInstr::FrameSetup);
781 // The EFLAGS implicit def is dead.
782 MI->getOperand(3).setIsDead();
785 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
788 // Skip the callee-saved push instructions.
789 bool PushedRegs = false;
790 int StackOffset = 2 * stackGrowth;
792 while (MBBI != MBB.end() &&
793 (MBBI->getOpcode() == X86::PUSH32r ||
794 MBBI->getOpcode() == X86::PUSH64r)) {
796 MBBI->setFlag(MachineInstr::FrameSetup);
799 if (!HasFP && needsFrameMoves) {
800 // Mark callee-saved push instruction.
801 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
802 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
804 // Define the current CFA rule to use the provided offset.
805 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr;
806 MachineLocation SPDst(Ptr);
807 MachineLocation SPSrc(Ptr, StackOffset);
808 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
809 StackOffset += stackGrowth;
813 DL = MBB.findDebugLoc(MBBI);
815 // If there is an SUB32ri of ESP immediately before this instruction, merge
816 // the two. This can be the case when tail call elimination is enabled and
817 // the callee has more arguments then the caller.
818 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
820 // If there is an ADD32ri or SUB32ri of ESP immediately after this
821 // instruction, merge the two instructions.
822 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
824 // Adjust stack pointer: ESP -= numbytes.
826 // Windows and cygwin/mingw require a prologue helper routine when allocating
827 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
828 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
829 // stack and adjust the stack pointer in one go. The 64-bit version of
830 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
831 // responsible for adjusting the stack pointer. Touching the stack at 4K
832 // increments is necessary to ensure that the guard pages used by the OS
833 // virtual memory manager are allocated in correct sequence.
834 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) {
835 const char *StackProbeSymbol;
836 bool isSPUpdateNeeded = false;
839 if (STI.isTargetCygMing())
840 StackProbeSymbol = "___chkstk";
842 StackProbeSymbol = "__chkstk";
843 isSPUpdateNeeded = true;
845 } else if (STI.isTargetCygMing())
846 StackProbeSymbol = "_alloca";
848 StackProbeSymbol = "_chkstk";
850 // Check whether EAX is livein for this function.
851 bool isEAXAlive = isEAXLiveIn(MF);
854 // Sanity check that EAX is not livein for this function.
855 // It should not be, so throw an assert.
856 assert(!Is64Bit && "EAX is livein in x64 case!");
859 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
860 .addReg(X86::EAX, RegState::Kill)
861 .setMIFlag(MachineInstr::FrameSetup);
865 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
866 // Function prologue is responsible for adjusting the stack pointer.
867 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
869 .setMIFlag(MachineInstr::FrameSetup);
871 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
872 // We'll also use 4 already allocated bytes for EAX.
873 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
874 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
875 .setMIFlag(MachineInstr::FrameSetup);
878 BuildMI(MBB, MBBI, DL,
879 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
880 .addExternalSymbol(StackProbeSymbol)
881 .addReg(StackPtr, RegState::Define | RegState::Implicit)
882 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
883 .setMIFlag(MachineInstr::FrameSetup);
885 // MSVC x64's __chkstk needs to adjust %rsp.
886 // FIXME: %rax preserves the offset and should be available.
887 if (isSPUpdateNeeded)
888 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
893 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
895 StackPtr, false, NumBytes - 4);
896 MI->setFlag(MachineInstr::FrameSetup);
897 MBB.insert(MBBI, MI);
900 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
903 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
904 // Mark end of stack pointer adjustment.
905 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
906 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
909 if (!HasFP && NumBytes) {
910 // Define the current CFA rule to use the provided offset.
912 MachineLocation SPDst(MachineLocation::VirtualFP);
913 MachineLocation SPSrc(MachineLocation::VirtualFP,
914 -StackSize + stackGrowth);
915 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
917 MachineLocation SPDst(StackPtr);
918 MachineLocation SPSrc(StackPtr, stackGrowth);
919 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
923 // Emit DWARF info specifying the offsets of the callee-saved registers.
925 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
928 // Darwin 10.7 and greater has support for compact unwind encoding.
929 if (STI.getTargetTriple().isMacOSX() &&
930 !STI.getTargetTriple().isMacOSXVersionLT(10, 7))
931 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
934 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
935 MachineBasicBlock &MBB) const {
936 const MachineFrameInfo *MFI = MF.getFrameInfo();
937 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
938 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
939 const X86InstrInfo &TII = *TM.getInstrInfo();
940 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
941 assert(MBBI != MBB.end() && "Returning block has no instructions");
942 unsigned RetOpcode = MBBI->getOpcode();
943 DebugLoc DL = MBBI->getDebugLoc();
944 bool Is64Bit = STI.is64Bit();
945 unsigned StackAlign = getStackAlignment();
946 unsigned SlotSize = RegInfo->getSlotSize();
947 unsigned FramePtr = RegInfo->getFrameRegister(MF);
948 unsigned StackPtr = RegInfo->getStackRegister();
952 llvm_unreachable("Can only insert epilog into returning blocks");
955 case X86::TCRETURNdi:
956 case X86::TCRETURNri:
957 case X86::TCRETURNmi:
958 case X86::TCRETURNdi64:
959 case X86::TCRETURNri64:
960 case X86::TCRETURNmi64:
962 case X86::EH_RETURN64:
963 break; // These are ok
966 // Get the number of bytes to allocate from the FrameInfo.
967 uint64_t StackSize = MFI->getStackSize();
968 uint64_t MaxAlign = MFI->getMaxAlignment();
969 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
970 uint64_t NumBytes = 0;
972 // If we're forcing a stack realignment we can't rely on just the frame
973 // info, we need to know the ABI stack alignment as well in case we
974 // have a call out. Otherwise just make sure we have some alignment - we'll
975 // go with the minimum.
976 if (ForceStackAlign) {
978 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
980 MaxAlign = MaxAlign ? MaxAlign : 4;
984 // Calculate required stack adjustment.
985 uint64_t FrameSize = StackSize - SlotSize;
986 if (RegInfo->needsStackRealignment(MF))
987 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
989 NumBytes = FrameSize - CSSize;
992 BuildMI(MBB, MBBI, DL,
993 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
995 NumBytes = StackSize - CSSize;
998 // Skip the callee-saved pop instructions.
999 MachineBasicBlock::iterator LastCSPop = MBBI;
1000 while (MBBI != MBB.begin()) {
1001 MachineBasicBlock::iterator PI = prior(MBBI);
1002 unsigned Opc = PI->getOpcode();
1004 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1005 !PI->isTerminator())
1011 DL = MBBI->getDebugLoc();
1013 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1014 // instruction, merge the two instructions.
1015 if (NumBytes || MFI->hasVarSizedObjects())
1016 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1018 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1019 // slot before popping them off! Same applies for the case, when stack was
1021 if (RegInfo->needsStackRealignment(MF)) {
1022 // We cannot use LEA here, because stack pointer was realigned. We need to
1023 // deallocate local frame back.
1025 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII, *RegInfo);
1026 MBBI = prior(LastCSPop);
1029 BuildMI(MBB, MBBI, DL,
1030 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1031 StackPtr).addReg(FramePtr);
1032 } else if (MFI->hasVarSizedObjects()) {
1034 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1036 addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1037 FramePtr, false, -CSSize);
1038 MBB.insert(MBBI, MI);
1040 BuildMI(MBB, MBBI, DL,
1041 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1044 } else if (NumBytes) {
1045 // Adjust stack pointer back: ESP += numbytes.
1046 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII, *RegInfo);
1049 // We're returning from function via eh_return.
1050 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1051 MBBI = MBB.getLastNonDebugInstr();
1052 MachineOperand &DestAddr = MBBI->getOperand(0);
1053 assert(DestAddr.isReg() && "Offset should be in register!");
1054 BuildMI(MBB, MBBI, DL,
1055 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1056 StackPtr).addReg(DestAddr.getReg());
1057 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1058 RetOpcode == X86::TCRETURNmi ||
1059 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1060 RetOpcode == X86::TCRETURNmi64) {
1061 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1062 // Tail call return: adjust the stack pointer and jump to callee.
1063 MBBI = MBB.getLastNonDebugInstr();
1064 MachineOperand &JumpTarget = MBBI->getOperand(0);
1065 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1066 assert(StackAdjust.isImm() && "Expecting immediate value.");
1068 // Adjust stack pointer.
1069 int StackAdj = StackAdjust.getImm();
1070 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1072 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1074 // Incoporate the retaddr area.
1075 Offset = StackAdj-MaxTCDelta;
1076 assert(Offset >= 0 && "Offset should never be negative");
1079 // Check for possible merge with preceding ADD instruction.
1080 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1081 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII, *RegInfo);
1084 // Jump to label or value in register.
1085 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1086 MachineInstrBuilder MIB =
1087 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1088 ? X86::TAILJMPd : X86::TAILJMPd64));
1089 if (JumpTarget.isGlobal())
1090 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1091 JumpTarget.getTargetFlags());
1093 assert(JumpTarget.isSymbol());
1094 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1095 JumpTarget.getTargetFlags());
1097 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1098 MachineInstrBuilder MIB =
1099 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1100 ? X86::TAILJMPm : X86::TAILJMPm64));
1101 for (unsigned i = 0; i != 5; ++i)
1102 MIB.addOperand(MBBI->getOperand(i));
1103 } else if (RetOpcode == X86::TCRETURNri64) {
1104 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1105 addReg(JumpTarget.getReg(), RegState::Kill);
1107 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1108 addReg(JumpTarget.getReg(), RegState::Kill);
1111 MachineInstr *NewMI = prior(MBBI);
1112 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1113 NewMI->addOperand(MBBI->getOperand(i));
1115 // Delete the pseudo instruction TCRETURN.
1117 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1118 (X86FI->getTCReturnAddrDelta() < 0)) {
1119 // Add the return addr area delta back since we are not tail calling.
1120 int delta = -1*X86FI->getTCReturnAddrDelta();
1121 MBBI = MBB.getLastNonDebugInstr();
1123 // Check for possible merge with preceding ADD instruction.
1124 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1125 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII, *RegInfo);
1129 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
1130 const X86RegisterInfo *RI =
1131 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1132 const MachineFrameInfo *MFI = MF.getFrameInfo();
1133 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1134 uint64_t StackSize = MFI->getStackSize();
1136 if (RI->needsStackRealignment(MF)) {
1138 // Skip the saved EBP.
1139 Offset += RI->getSlotSize();
1141 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1142 return Offset + StackSize;
1144 // FIXME: Support tail calls
1147 return Offset + StackSize;
1149 // Skip the saved EBP.
1150 Offset += RI->getSlotSize();
1152 // Skip the RETADDR move area
1153 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1154 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1155 if (TailCallReturnAddrDelta < 0)
1156 Offset -= TailCallReturnAddrDelta;
1162 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1163 MachineBasicBlock::iterator MI,
1164 const std::vector<CalleeSavedInfo> &CSI,
1165 const TargetRegisterInfo *TRI) const {
1169 DebugLoc DL = MBB.findDebugLoc(MI);
1171 MachineFunction &MF = *MBB.getParent();
1173 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
1174 unsigned FPReg = TRI->getFrameRegister(MF);
1175 unsigned CalleeFrameSize = 0;
1177 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1178 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1180 // Push GPRs. It increases frame size.
1181 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1182 for (unsigned i = CSI.size(); i != 0; --i) {
1183 unsigned Reg = CSI[i-1].getReg();
1184 if (!X86::GR64RegClass.contains(Reg) &&
1185 !X86::GR32RegClass.contains(Reg))
1187 // Add the callee-saved register as live-in. It's killed at the spill.
1190 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
1192 CalleeFrameSize += SlotSize;
1193 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1194 .setMIFlag(MachineInstr::FrameSetup);
1197 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
1199 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1200 // It can be done by spilling XMMs to stack frame.
1201 // Note that only Win64 ABI might spill XMMs.
1202 for (unsigned i = CSI.size(); i != 0; --i) {
1203 unsigned Reg = CSI[i-1].getReg();
1204 if (X86::GR64RegClass.contains(Reg) ||
1205 X86::GR32RegClass.contains(Reg))
1207 // Add the callee-saved register as live-in. It's killed at the spill.
1209 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1210 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1217 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1218 MachineBasicBlock::iterator MI,
1219 const std::vector<CalleeSavedInfo> &CSI,
1220 const TargetRegisterInfo *TRI) const {
1224 DebugLoc DL = MBB.findDebugLoc(MI);
1226 MachineFunction &MF = *MBB.getParent();
1227 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1229 // Reload XMMs from stack frame.
1230 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1231 unsigned Reg = CSI[i].getReg();
1232 if (X86::GR64RegClass.contains(Reg) ||
1233 X86::GR32RegClass.contains(Reg))
1235 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1236 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1241 unsigned FPReg = TRI->getFrameRegister(MF);
1242 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1243 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1244 unsigned Reg = CSI[i].getReg();
1245 if (!X86::GR64RegClass.contains(Reg) &&
1246 !X86::GR32RegClass.contains(Reg))
1249 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
1251 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1257 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1258 RegScavenger *RS) const {
1259 MachineFrameInfo *MFI = MF.getFrameInfo();
1260 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
1261 unsigned SlotSize = RegInfo->getSlotSize();
1263 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1264 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1266 if (TailCallReturnAddrDelta < 0) {
1267 // create RETURNADDR area
1276 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1277 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
1281 assert((TailCallReturnAddrDelta <= 0) &&
1282 "The Delta should always be zero or negative");
1283 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
1285 // Create a frame entry for the EBP register that must be saved.
1286 int FrameIdx = MFI->CreateFixedObject(SlotSize,
1288 TFI.getOffsetOfLocalArea() +
1289 TailCallReturnAddrDelta,
1291 assert(FrameIdx == MFI->getObjectIndexBegin() &&
1292 "Slot for EBP register must be last in order to be found!");
1298 HasNestArgument(const MachineFunction *MF) {
1299 const Function *F = MF->getFunction();
1300 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1302 if (I->hasNestAttr())
1309 /// GetScratchRegister - Get a register for performing work in the segmented
1310 /// stack prologue. Depending on platform and the properties of the function
1311 /// either one or two registers will be needed. Set primary to true for
1312 /// the first register, false for the second.
1314 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1316 return Primary ? X86::R11 : X86::R12;
1318 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1319 bool IsNested = HasNestArgument(&MF);
1321 if (CallingConvention == CallingConv::X86_FastCall ||
1322 CallingConvention == CallingConv::Fast) {
1324 report_fatal_error("Segmented stacks does not support fastcall with "
1325 "nested function.");
1328 return Primary ? X86::EAX : X86::ECX;
1332 return Primary ? X86::EDX : X86::EAX;
1334 return Primary ? X86::ECX : X86::EAX;
1339 // The stack limit in the TCB is set to this many bytes above the actual stack
1341 static const uint64_t kSplitStackAvailable = 256;
1344 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1345 MachineBasicBlock &prologueMBB = MF.front();
1346 MachineFrameInfo *MFI = MF.getFrameInfo();
1347 const X86InstrInfo &TII = *TM.getInstrInfo();
1349 bool Is64Bit = STI.is64Bit();
1350 unsigned TlsReg, TlsOffset;
1352 const X86Subtarget *ST = &MF.getTarget().getSubtarget<X86Subtarget>();
1354 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1355 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1356 "Scratch register is live-in");
1358 if (MF.getFunction()->isVarArg())
1359 report_fatal_error("Segmented stacks do not support vararg functions.");
1360 if (!ST->isTargetLinux() && !ST->isTargetDarwin() && !ST->isTargetWin32())
1361 report_fatal_error("Segmented stacks supported only on linux, darwin and win32.");
1363 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1364 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1365 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1366 bool IsNested = false;
1368 // We need to know if the function has a nest argument only in 64 bit mode.
1370 IsNested = HasNestArgument(&MF);
1372 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1373 // allocMBB needs to be last (terminating) instruction.
1375 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1376 e = prologueMBB.livein_end(); i != e; i++) {
1377 allocMBB->addLiveIn(*i);
1378 checkMBB->addLiveIn(*i);
1382 allocMBB->addLiveIn(X86::R10);
1384 MF.push_front(allocMBB);
1385 MF.push_front(checkMBB);
1387 // Eventually StackSize will be calculated by a link-time pass; which will
1388 // also decide whether checking code needs to be injected into this particular
1390 StackSize = MFI->getStackSize();
1392 // When the frame size is less than 256 we just compare the stack
1393 // boundary directly to the value of the stack pointer, per gcc.
1394 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1396 // Read the limit off the current stacklet off the stack_guard location.
1398 if (ST->isTargetLinux()) {
1401 } else if (ST->isTargetDarwin()) {
1403 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1405 report_fatal_error("Segmented stacks not supported on this platform.");
1408 if (CompareStackPointer)
1409 ScratchReg = X86::RSP;
1411 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1412 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1414 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1415 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1417 if (ST->isTargetLinux()) {
1420 } else if (ST->isTargetDarwin()) {
1422 TlsOffset = 0x48 + 90*4;
1423 } else if (ST->isTargetWin32()) {
1425 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1427 report_fatal_error("Segmented stacks not supported on this platform.");
1430 if (CompareStackPointer)
1431 ScratchReg = X86::ESP;
1433 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1434 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1436 if (ST->isTargetLinux() || ST->isTargetWin32()) {
1437 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1438 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1439 } else if (ST->isTargetDarwin()) {
1441 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
1442 unsigned ScratchReg2;
1444 if (CompareStackPointer) {
1445 // The primary scratch register is available for holding the TLS offset
1446 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1447 SaveScratch2 = false;
1449 // Need to use a second register to hold the TLS offset
1450 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1452 // Unfortunately, with fastcc the second scratch register may hold an arg
1453 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1456 // If Scratch2 is live-in then it needs to be saved
1457 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1458 "Scratch register is live-in and not saved");
1461 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1462 .addReg(ScratchReg2, RegState::Kill);
1464 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1466 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1468 .addReg(ScratchReg2).addImm(1).addReg(0)
1473 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1477 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1478 // It jumps to normal execution of the function body.
1479 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1481 // On 32 bit we first push the arguments size and then the frame size. On 64
1482 // bit, we pass the stack frame size in r10 and the argument size in r11.
1484 // Functions with nested arguments use R10, so it needs to be saved across
1485 // the call to _morestack
1488 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1490 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1492 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1493 .addImm(X86FI->getArgumentStackSize());
1494 MF.getRegInfo().setPhysRegUsed(X86::R10);
1495 MF.getRegInfo().setPhysRegUsed(X86::R11);
1497 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1498 .addImm(X86FI->getArgumentStackSize());
1499 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1503 // __morestack is in libgcc
1505 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1506 .addExternalSymbol("__morestack");
1508 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1509 .addExternalSymbol("__morestack");
1512 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1514 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1516 allocMBB->addSuccessor(&prologueMBB);
1518 checkMBB->addSuccessor(allocMBB);
1519 checkMBB->addSuccessor(&prologueMBB);