1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/ADT/SmallSet.h"
35 // FIXME: completely move here.
36 extern cl::opt<bool> ForceStackAlign;
38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
39 return !MF.getFrameInfo()->hasVarSizedObjects();
42 /// hasFP - Return true if the specified function should have a dedicated frame
43 /// pointer register. This is true if the function has variable sized allocas
44 /// or if frame pointer elimination is disabled.
45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 const MachineModuleInfo &MMI = MF.getMMI();
48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
50 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
51 RegInfo->needsStackRealignment(MF) ||
52 MFI->hasVarSizedObjects() ||
53 MFI->isFrameAddressTaken() ||
54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
55 MMI.callsUnwindInit() || MMI.callsEHReturn());
58 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
62 return X86::SUB64ri32;
70 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
74 return X86::ADD64ri32;
82 static unsigned getLEArOpcode(unsigned is64Bit) {
83 return is64Bit ? X86::LEA64r : X86::LEA32r;
86 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
87 /// when it reaches the "return" instruction. We can then pop a stack object
88 /// to this register without worry about clobbering it.
89 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator &MBBI,
91 const TargetRegisterInfo &TRI,
93 const MachineFunction *MF = MBB.getParent();
94 const Function *F = MF->getFunction();
95 if (!F || MF->getMMI().callsEHReturn())
98 static const uint16_t CallerSavedRegs32Bit[] = {
99 X86::EAX, X86::EDX, X86::ECX, 0
102 static const uint16_t CallerSavedRegs64Bit[] = {
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
107 unsigned Opc = MBBI->getOpcode();
112 case X86::TCRETURNdi:
113 case X86::TCRETURNri:
114 case X86::TCRETURNmi:
115 case X86::TCRETURNdi64:
116 case X86::TCRETURNri64:
117 case X86::TCRETURNmi64:
119 case X86::EH_RETURN64: {
120 SmallSet<uint16_t, 8> Uses;
121 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
122 MachineOperand &MO = MBBI->getOperand(i);
123 if (!MO.isReg() || MO.isDef())
125 unsigned Reg = MO.getReg();
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
134 if (!Uses.count(*CS))
143 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
144 /// stack pointer by a constant value.
146 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
147 unsigned StackPtr, int64_t NumBytes,
148 bool Is64Bit, bool UseLEA,
149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
150 bool isSub = NumBytes < 0;
151 uint64_t Offset = isSub ? -NumBytes : NumBytes;
154 Opc = getLEArOpcode(Is64Bit);
157 ? getSUBriOpcode(Is64Bit, Offset)
158 : getADDriOpcode(Is64Bit, Offset);
160 uint64_t Chunk = (1LL << 31) - 1;
161 DebugLoc DL = MBB.findDebugLoc(MBBI);
164 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
165 if (ThisVal == (Is64Bit ? 8 : 4)) {
166 // Use push / pop instead.
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
177 MI->setFlag(MachineInstr::FrameSetup);
183 MachineInstr *MI = NULL;
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
187 StackPtr, false, isSub ? -ThisVal : ThisVal);
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
192 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
196 MI->setFlag(MachineInstr::FrameSetup);
202 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
204 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
205 unsigned StackPtr, uint64_t *NumBytes = NULL) {
206 if (MBBI == MBB.begin()) return;
208 MachineBasicBlock::iterator PI = prior(MBBI);
209 unsigned Opc = PI->getOpcode();
210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
213 PI->getOperand(0).getReg() == StackPtr) {
215 *NumBytes += PI->getOperand(2).getImm();
217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
219 PI->getOperand(0).getReg() == StackPtr) {
221 *NumBytes -= PI->getOperand(2).getImm();
226 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
228 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator &MBBI,
230 unsigned StackPtr, uint64_t *NumBytes = NULL) {
231 // FIXME: THIS ISN'T RUN!!!
234 if (MBBI == MBB.end()) return;
236 MachineBasicBlock::iterator NI = llvm::next(MBBI);
237 if (NI == MBB.end()) return;
239 unsigned Opc = NI->getOpcode();
240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
242 NI->getOperand(0).getReg() == StackPtr) {
244 *NumBytes -= NI->getOperand(2).getImm();
247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
249 NI->getOperand(0).getReg() == StackPtr) {
251 *NumBytes += NI->getOperand(2).getImm();
257 /// mergeSPUpdates - Checks the instruction before/after the passed
258 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the
259 /// stack adjustment is returned as a positive value for ADD/LEA and a negative for
261 static int mergeSPUpdates(MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator &MBBI,
264 bool doMergeWithPrevious) {
265 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
266 (!doMergeWithPrevious && MBBI == MBB.end()))
269 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
270 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
271 unsigned Opc = PI->getOpcode();
274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
277 PI->getOperand(0).getReg() == StackPtr){
278 Offset += PI->getOperand(2).getImm();
280 if (!doMergeWithPrevious) MBBI = NI;
281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
283 PI->getOperand(0).getReg() == StackPtr) {
284 Offset -= PI->getOperand(2).getImm();
286 if (!doMergeWithPrevious) MBBI = NI;
292 static bool isEAXLiveIn(MachineFunction &MF) {
293 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
294 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL)
305 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
307 unsigned FramePtr) const {
308 MachineFrameInfo *MFI = MF.getFrameInfo();
309 MachineModuleInfo &MMI = MF.getMMI();
311 // Add callee saved registers to move list.
312 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
313 if (CSI.empty()) return;
315 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
316 const TargetData *TD = TM.getTargetData();
317 bool HasFP = hasFP(MF);
319 // Calculate amount of bytes used for return address storing.
320 int stackGrowth = -TD->getPointerSize();
322 // FIXME: This is dirty hack. The code itself is pretty mess right now.
323 // It should be rewritten from scratch and generalized sometimes.
325 // Determine maximum offset (minimum due to stack growth).
326 int64_t MaxOffset = 0;
327 for (std::vector<CalleeSavedInfo>::const_iterator
328 I = CSI.begin(), E = CSI.end(); I != E; ++I)
329 MaxOffset = std::min(MaxOffset,
330 MFI->getObjectOffset(I->getFrameIdx()));
332 // Calculate offsets.
333 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
334 for (std::vector<CalleeSavedInfo>::const_iterator
335 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
336 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
337 unsigned Reg = I->getReg();
338 Offset = MaxOffset - Offset + saveAreaOffset;
340 // Don't output a new machine move if we're re-saving the frame
341 // pointer. This happens when the PrologEpilogInserter has inserted an extra
342 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
343 // generates one when frame pointers are used. If we generate a "machine
344 // move" for this extra "PUSH", the linker will lose track of the fact that
345 // the frame pointer should have the value of the first "PUSH" when it's
348 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
349 // another bug. I.e., one where we generate a prolog like this:
357 // The immediate re-push of EBP is unnecessary. At the least, it's an
358 // optimization bug. EBP can be used as a scratch register in certain
359 // cases, but probably not when we have a frame pointer.
360 if (HasFP && FramePtr == Reg)
363 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
364 MachineLocation CSSrc(Reg);
365 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
369 /// getCompactUnwindRegNum - Get the compact unwind number for a given
370 /// register. The number corresponds to the enum lists in
371 /// compact_unwind_encoding.h.
372 static int getCompactUnwindRegNum(const uint16_t *CURegs, unsigned Reg) {
373 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
380 // Number of registers that can be saved in a compact unwind encoding.
381 #define CU_NUM_SAVED_REGS 6
383 /// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding
384 /// used with frameless stacks. It is passed the number of registers to be saved
385 /// and an array of the registers saved.
387 encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
388 unsigned RegCount, bool Is64Bit) {
389 // The saved registers are numbered from 1 to 6. In order to encode the order
390 // in which they were saved, we re-number them according to their place in the
391 // register order. The re-numbering is relative to the last re-numbered
392 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
401 static const uint16_t CU32BitRegs[] = {
402 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
404 static const uint16_t CU64BitRegs[] = {
405 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
407 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
409 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
410 int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]);
411 if (CUReg == -1) return ~0U;
412 SavedRegs[i] = CUReg;
416 std::swap(SavedRegs[0], SavedRegs[5]);
417 std::swap(SavedRegs[1], SavedRegs[4]);
418 std::swap(SavedRegs[2], SavedRegs[3]);
420 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
421 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i) {
422 unsigned Countless = 0;
423 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
424 if (SavedRegs[j] < SavedRegs[i])
427 RenumRegs[i] = SavedRegs[i] - Countless - 1;
430 // Take the renumbered values and encode them into a 10-bit number.
431 uint32_t permutationEncoding = 0;
434 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
435 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
439 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
440 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
444 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
445 + 3 * RenumRegs[4] + RenumRegs[5];
448 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
452 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
455 permutationEncoding |= RenumRegs[5];
459 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
460 "Invalid compact register encoding!");
461 return permutationEncoding;
464 /// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a
465 /// compact encoding with a frame pointer.
467 encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
469 static const uint16_t CU32BitRegs[] = {
470 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
472 static const uint16_t CU64BitRegs[] = {
473 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
475 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
477 // Encode the registers in the order they were saved, 3-bits per register. The
478 // registers are numbered from 1 to CU_NUM_SAVED_REGS.
480 for (int I = CU_NUM_SAVED_REGS - 1, Idx = 0; I != -1; --I) {
481 unsigned Reg = SavedRegs[I];
482 if (Reg == 0) continue;
484 int CURegNum = getCompactUnwindRegNum(CURegs, Reg);
485 if (CURegNum == -1) return ~0U;
487 // Encode the 3-bit register number in order, skipping over 3-bits for each
489 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
492 assert((RegEnc & 0x3FFFF) == RegEnc && "Invalid compact register encoding!");
496 uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const {
497 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
498 unsigned FramePtr = RegInfo->getFrameRegister(MF);
499 unsigned StackPtr = RegInfo->getStackRegister();
501 bool Is64Bit = STI.is64Bit();
502 bool HasFP = hasFP(MF);
504 unsigned SavedRegs[CU_NUM_SAVED_REGS] = { 0, 0, 0, 0, 0, 0 };
505 unsigned SavedRegIdx = 0;
507 unsigned OffsetSize = (Is64Bit ? 8 : 4);
509 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
510 unsigned PushInstrSize = 1;
511 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
512 unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
513 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
515 unsigned StackDivide = (Is64Bit ? 8 : 4);
517 unsigned InstrOffset = 0;
518 unsigned StackAdjust = 0;
519 unsigned StackSize = 0;
521 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB.
522 bool ExpectEnd = false;
523 for (MachineBasicBlock::iterator
524 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) {
525 MachineInstr &MI = *MBBI;
526 unsigned Opc = MI.getOpcode();
527 if (Opc == X86::PROLOG_LABEL) continue;
528 if (!MI.getFlag(MachineInstr::FrameSetup)) break;
530 // We don't exect any more prolog instructions.
531 if (ExpectEnd) return 0;
533 if (Opc == PushInstr) {
534 // If there are too many saved registers, we cannot use compact encoding.
535 if (SavedRegIdx >= CU_NUM_SAVED_REGS) return 0;
537 SavedRegs[SavedRegIdx++] = MI.getOperand(0).getReg();
538 StackAdjust += OffsetSize;
539 InstrOffset += PushInstrSize;
540 } else if (Opc == MoveInstr) {
541 unsigned SrcReg = MI.getOperand(1).getReg();
542 unsigned DstReg = MI.getOperand(0).getReg();
544 if (DstReg != FramePtr || SrcReg != StackPtr)
548 memset(SavedRegs, 0, sizeof(SavedRegs));
550 InstrOffset += MoveInstrSize;
551 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
552 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
554 // We already have a stack size.
557 if (!MI.getOperand(0).isReg() ||
558 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() ||
559 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm())
560 // We need this to be a stack adjustment pointer. Something like:
562 // %RSP<def> = SUB64ri8 %RSP, 48
565 StackSize = MI.getOperand(2).getImm() / StackDivide;
566 SubtractInstrIdx += InstrOffset;
571 // Encode that we are using EBP/RBP as the frame pointer.
572 uint32_t CompactUnwindEncoding = 0;
573 StackAdjust /= StackDivide;
575 if ((StackAdjust & 0xFF) != StackAdjust)
576 // Offset was too big for compact encoding.
579 // Get the encoding of the saved registers when we have a frame pointer.
580 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
581 if (RegEnc == ~0U) return 0;
583 CompactUnwindEncoding |= 0x01000000;
584 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
585 CompactUnwindEncoding |= RegEnc & 0x7FFF;
588 uint32_t TotalStackSize = StackAdjust + StackSize;
589 if ((TotalStackSize & 0xFF) == TotalStackSize) {
590 // Frameless stack with a small stack size.
591 CompactUnwindEncoding |= 0x02000000;
593 // Encode the stack size.
594 CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16;
596 if ((StackAdjust & 0x7) != StackAdjust)
597 // The extra stack adjustments are too big for us to handle.
600 // Frameless stack with an offset too large for us to encode compactly.
601 CompactUnwindEncoding |= 0x03000000;
603 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
605 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
607 // Encode any extra stack stack adjustments (done via push instructions).
608 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
611 // Encode the number of registers saved.
612 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
614 // Get the encoding of the saved registers when we don't have a frame
617 encodeCompactUnwindRegistersWithoutFrame(SavedRegs, SavedRegIdx,
619 if (RegEnc == ~0U) return 0;
621 // Encode the register encoding.
622 CompactUnwindEncoding |= RegEnc & 0x3FF;
625 return CompactUnwindEncoding;
628 /// emitPrologue - Push callee-saved registers onto the stack, which
629 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
630 /// space for local variables. Also emit labels used by the exception handler to
631 /// generate the exception handling frames.
632 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
633 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
634 MachineBasicBlock::iterator MBBI = MBB.begin();
635 MachineFrameInfo *MFI = MF.getFrameInfo();
636 const Function *Fn = MF.getFunction();
637 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
638 const X86InstrInfo &TII = *TM.getInstrInfo();
639 MachineModuleInfo &MMI = MF.getMMI();
640 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
641 bool needsFrameMoves = MMI.hasDebugInfo() ||
642 Fn->needsUnwindTableEntry();
643 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
644 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
645 bool HasFP = hasFP(MF);
646 bool Is64Bit = STI.is64Bit();
647 bool IsWin64 = STI.isTargetWin64();
648 bool UseLEA = STI.useLeaForSP();
649 unsigned StackAlign = getStackAlignment();
650 unsigned SlotSize = RegInfo->getSlotSize();
651 unsigned FramePtr = RegInfo->getFrameRegister(MF);
652 unsigned StackPtr = RegInfo->getStackRegister();
655 // If we're forcing a stack realignment we can't rely on just the frame
656 // info, we need to know the ABI stack alignment as well in case we
657 // have a call out. Otherwise just make sure we have some alignment - we'll
658 // go with the minimum SlotSize.
659 if (ForceStackAlign) {
661 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
662 else if (MaxAlign < SlotSize)
666 // Add RETADDR move area to callee saved frame size.
667 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
668 if (TailCallReturnAddrDelta < 0)
669 X86FI->setCalleeSavedFrameSize(
670 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
672 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
673 // function, and use up to 128 bytes of stack space, don't have a frame
674 // pointer, calls, or dynamic alloca then we do not need to adjust the
675 // stack pointer (we fit in the Red Zone).
676 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
677 !RegInfo->needsStackRealignment(MF) &&
678 !MFI->hasVarSizedObjects() && // No dynamic alloca.
679 !MFI->adjustsStack() && // No calls.
680 !IsWin64 && // Win64 has no Red Zone
681 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack
682 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
683 if (HasFP) MinSize += SlotSize;
684 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
685 MFI->setStackSize(StackSize);
688 // Insert stack pointer adjustment for later moving of return addr. Only
689 // applies to tail call optimized functions where the callee argument stack
690 // size is bigger than the callers.
691 if (TailCallReturnAddrDelta < 0) {
693 BuildMI(MBB, MBBI, DL,
694 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
697 .addImm(-TailCallReturnAddrDelta)
698 .setMIFlag(MachineInstr::FrameSetup);
699 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
702 // Mapping for machine moves:
704 // DST: VirtualFP AND
705 // SRC: VirtualFP => DW_CFA_def_cfa_offset
706 // ELSE => DW_CFA_def_cfa
708 // SRC: VirtualFP AND
709 // DST: Register => DW_CFA_def_cfa_register
712 // OFFSET < 0 => DW_CFA_offset_extended_sf
713 // REG < 64 => DW_CFA_offset + Reg
714 // ELSE => DW_CFA_offset_extended
716 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
717 const TargetData *TD = MF.getTarget().getTargetData();
718 uint64_t NumBytes = 0;
719 int stackGrowth = -TD->getPointerSize();
722 // Calculate required stack adjustment.
723 uint64_t FrameSize = StackSize - SlotSize;
724 if (RegInfo->needsStackRealignment(MF))
725 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
727 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
729 // Get the offset of the stack slot for the EBP register, which is
730 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
731 // Update the frame offset adjustment.
732 MFI->setOffsetAdjustment(-NumBytes);
734 // Save EBP/RBP into the appropriate stack slot.
735 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
736 .addReg(FramePtr, RegState::Kill)
737 .setMIFlag(MachineInstr::FrameSetup);
739 if (needsFrameMoves) {
740 // Mark the place where EBP/RBP was saved.
741 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
742 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
745 // Define the current CFA rule to use the provided offset.
747 MachineLocation SPDst(MachineLocation::VirtualFP);
748 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
749 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
751 MachineLocation SPDst(StackPtr);
752 MachineLocation SPSrc(StackPtr, stackGrowth);
753 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
756 // Change the rule for the FramePtr to be an "offset" rule.
757 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
758 MachineLocation FPSrc(FramePtr);
759 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
762 // Update EBP with the new base value.
763 BuildMI(MBB, MBBI, DL,
764 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
766 .setMIFlag(MachineInstr::FrameSetup);
768 if (needsFrameMoves) {
769 // Mark effective beginning of when frame pointer becomes valid.
770 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
771 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
774 // Define the current CFA to use the EBP/RBP register.
775 MachineLocation FPDst(FramePtr);
776 MachineLocation FPSrc(MachineLocation::VirtualFP);
777 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
780 // Mark the FramePtr as live-in in every block except the entry.
781 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
783 I->addLiveIn(FramePtr);
786 if (RegInfo->needsStackRealignment(MF)) {
788 BuildMI(MBB, MBBI, DL,
789 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
792 .setMIFlag(MachineInstr::FrameSetup);
794 // The EFLAGS implicit def is dead.
795 MI->getOperand(3).setIsDead();
798 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
801 // Skip the callee-saved push instructions.
802 bool PushedRegs = false;
803 int StackOffset = 2 * stackGrowth;
805 while (MBBI != MBB.end() &&
806 (MBBI->getOpcode() == X86::PUSH32r ||
807 MBBI->getOpcode() == X86::PUSH64r)) {
809 MBBI->setFlag(MachineInstr::FrameSetup);
812 if (!HasFP && needsFrameMoves) {
813 // Mark callee-saved push instruction.
814 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
815 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
817 // Define the current CFA rule to use the provided offset.
818 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr;
819 MachineLocation SPDst(Ptr);
820 MachineLocation SPSrc(Ptr, StackOffset);
821 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
822 StackOffset += stackGrowth;
826 DL = MBB.findDebugLoc(MBBI);
828 // If there is an SUB32ri of ESP immediately before this instruction, merge
829 // the two. This can be the case when tail call elimination is enabled and
830 // the callee has more arguments then the caller.
831 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
833 // If there is an ADD32ri or SUB32ri of ESP immediately after this
834 // instruction, merge the two instructions.
835 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
837 // Adjust stack pointer: ESP -= numbytes.
839 // Windows and cygwin/mingw require a prologue helper routine when allocating
840 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
841 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
842 // stack and adjust the stack pointer in one go. The 64-bit version of
843 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
844 // responsible for adjusting the stack pointer. Touching the stack at 4K
845 // increments is necessary to ensure that the guard pages used by the OS
846 // virtual memory manager are allocated in correct sequence.
847 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) {
848 const char *StackProbeSymbol;
849 bool isSPUpdateNeeded = false;
852 if (STI.isTargetCygMing())
853 StackProbeSymbol = "___chkstk";
855 StackProbeSymbol = "__chkstk";
856 isSPUpdateNeeded = true;
858 } else if (STI.isTargetCygMing())
859 StackProbeSymbol = "_alloca";
861 StackProbeSymbol = "_chkstk";
863 // Check whether EAX is livein for this function.
864 bool isEAXAlive = isEAXLiveIn(MF);
867 // Sanity check that EAX is not livein for this function.
868 // It should not be, so throw an assert.
869 assert(!Is64Bit && "EAX is livein in x64 case!");
872 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
873 .addReg(X86::EAX, RegState::Kill)
874 .setMIFlag(MachineInstr::FrameSetup);
878 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
879 // Function prologue is responsible for adjusting the stack pointer.
880 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
882 .setMIFlag(MachineInstr::FrameSetup);
884 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
885 // We'll also use 4 already allocated bytes for EAX.
886 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
887 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
888 .setMIFlag(MachineInstr::FrameSetup);
891 BuildMI(MBB, MBBI, DL,
892 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
893 .addExternalSymbol(StackProbeSymbol)
894 .addReg(StackPtr, RegState::Define | RegState::Implicit)
895 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
896 .setMIFlag(MachineInstr::FrameSetup);
898 // MSVC x64's __chkstk needs to adjust %rsp.
899 // FIXME: %rax preserves the offset and should be available.
900 if (isSPUpdateNeeded)
901 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
902 UseLEA, TII, *RegInfo);
906 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
908 StackPtr, false, NumBytes - 4);
909 MI->setFlag(MachineInstr::FrameSetup);
910 MBB.insert(MBBI, MI);
913 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit,
914 UseLEA, TII, *RegInfo);
916 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
917 // Mark end of stack pointer adjustment.
918 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
919 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
922 if (!HasFP && NumBytes) {
923 // Define the current CFA rule to use the provided offset.
925 MachineLocation SPDst(MachineLocation::VirtualFP);
926 MachineLocation SPSrc(MachineLocation::VirtualFP,
927 -StackSize + stackGrowth);
928 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
930 MachineLocation SPDst(StackPtr);
931 MachineLocation SPSrc(StackPtr, stackGrowth);
932 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
936 // Emit DWARF info specifying the offsets of the callee-saved registers.
938 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
941 // Darwin 10.7 and greater has support for compact unwind encoding.
942 if (STI.getTargetTriple().isMacOSX() &&
943 !STI.getTargetTriple().isMacOSXVersionLT(10, 7))
944 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
947 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
948 MachineBasicBlock &MBB) const {
949 const MachineFrameInfo *MFI = MF.getFrameInfo();
950 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
951 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
952 const X86InstrInfo &TII = *TM.getInstrInfo();
953 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
954 assert(MBBI != MBB.end() && "Returning block has no instructions");
955 unsigned RetOpcode = MBBI->getOpcode();
956 DebugLoc DL = MBBI->getDebugLoc();
957 bool Is64Bit = STI.is64Bit();
958 bool UseLEA = STI.useLeaForSP();
959 unsigned StackAlign = getStackAlignment();
960 unsigned SlotSize = RegInfo->getSlotSize();
961 unsigned FramePtr = RegInfo->getFrameRegister(MF);
962 unsigned StackPtr = RegInfo->getStackRegister();
966 llvm_unreachable("Can only insert epilog into returning blocks");
969 case X86::TCRETURNdi:
970 case X86::TCRETURNri:
971 case X86::TCRETURNmi:
972 case X86::TCRETURNdi64:
973 case X86::TCRETURNri64:
974 case X86::TCRETURNmi64:
976 case X86::EH_RETURN64:
977 break; // These are ok
980 // Get the number of bytes to allocate from the FrameInfo.
981 uint64_t StackSize = MFI->getStackSize();
982 uint64_t MaxAlign = MFI->getMaxAlignment();
983 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
984 uint64_t NumBytes = 0;
986 // If we're forcing a stack realignment we can't rely on just the frame
987 // info, we need to know the ABI stack alignment as well in case we
988 // have a call out. Otherwise just make sure we have some alignment - we'll
989 // go with the minimum.
990 if (ForceStackAlign) {
992 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
994 MaxAlign = MaxAlign ? MaxAlign : 4;
998 // Calculate required stack adjustment.
999 uint64_t FrameSize = StackSize - SlotSize;
1000 if (RegInfo->needsStackRealignment(MF))
1001 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1003 NumBytes = FrameSize - CSSize;
1006 BuildMI(MBB, MBBI, DL,
1007 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1009 NumBytes = StackSize - CSSize;
1012 // Skip the callee-saved pop instructions.
1013 MachineBasicBlock::iterator LastCSPop = MBBI;
1014 while (MBBI != MBB.begin()) {
1015 MachineBasicBlock::iterator PI = prior(MBBI);
1016 unsigned Opc = PI->getOpcode();
1018 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1019 !PI->isTerminator())
1025 DL = MBBI->getDebugLoc();
1027 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1028 // instruction, merge the two instructions.
1029 if (NumBytes || MFI->hasVarSizedObjects())
1030 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1032 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1033 // slot before popping them off! Same applies for the case, when stack was
1035 if (RegInfo->needsStackRealignment(MF)) {
1036 // We cannot use LEA here, because stack pointer was realigned. We need to
1037 // deallocate local frame back.
1039 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, UseLEA, TII,
1041 MBBI = prior(LastCSPop);
1044 BuildMI(MBB, MBBI, DL,
1045 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1046 StackPtr).addReg(FramePtr);
1047 } else if (MFI->hasVarSizedObjects()) {
1049 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1051 addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1052 FramePtr, false, -CSSize);
1053 MBB.insert(MBBI, MI);
1055 BuildMI(MBB, MBBI, DL,
1056 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1059 } else if (NumBytes) {
1060 // Adjust stack pointer back: ESP += numbytes.
1061 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, UseLEA, TII, *RegInfo);
1064 // We're returning from function via eh_return.
1065 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1066 MBBI = MBB.getLastNonDebugInstr();
1067 MachineOperand &DestAddr = MBBI->getOperand(0);
1068 assert(DestAddr.isReg() && "Offset should be in register!");
1069 BuildMI(MBB, MBBI, DL,
1070 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1071 StackPtr).addReg(DestAddr.getReg());
1072 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1073 RetOpcode == X86::TCRETURNmi ||
1074 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1075 RetOpcode == X86::TCRETURNmi64) {
1076 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1077 // Tail call return: adjust the stack pointer and jump to callee.
1078 MBBI = MBB.getLastNonDebugInstr();
1079 MachineOperand &JumpTarget = MBBI->getOperand(0);
1080 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1081 assert(StackAdjust.isImm() && "Expecting immediate value.");
1083 // Adjust stack pointer.
1084 int StackAdj = StackAdjust.getImm();
1085 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1087 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1089 // Incoporate the retaddr area.
1090 Offset = StackAdj-MaxTCDelta;
1091 assert(Offset >= 0 && "Offset should never be negative");
1094 // Check for possible merge with preceding ADD instruction.
1095 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1096 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, UseLEA, TII, *RegInfo);
1099 // Jump to label or value in register.
1100 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1101 MachineInstrBuilder MIB =
1102 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1103 ? X86::TAILJMPd : X86::TAILJMPd64));
1104 if (JumpTarget.isGlobal())
1105 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1106 JumpTarget.getTargetFlags());
1108 assert(JumpTarget.isSymbol());
1109 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1110 JumpTarget.getTargetFlags());
1112 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1113 MachineInstrBuilder MIB =
1114 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1115 ? X86::TAILJMPm : X86::TAILJMPm64));
1116 for (unsigned i = 0; i != 5; ++i)
1117 MIB.addOperand(MBBI->getOperand(i));
1118 } else if (RetOpcode == X86::TCRETURNri64) {
1119 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1120 addReg(JumpTarget.getReg(), RegState::Kill);
1122 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1123 addReg(JumpTarget.getReg(), RegState::Kill);
1126 MachineInstr *NewMI = prior(MBBI);
1127 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1128 NewMI->addOperand(MBBI->getOperand(i));
1130 // Delete the pseudo instruction TCRETURN.
1132 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1133 (X86FI->getTCReturnAddrDelta() < 0)) {
1134 // Add the return addr area delta back since we are not tail calling.
1135 int delta = -1*X86FI->getTCReturnAddrDelta();
1136 MBBI = MBB.getLastNonDebugInstr();
1138 // Check for possible merge with preceding ADD instruction.
1139 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1140 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, UseLEA, TII, *RegInfo);
1144 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
1145 const X86RegisterInfo *RegInfo =
1146 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1147 const MachineFrameInfo *MFI = MF.getFrameInfo();
1148 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1149 uint64_t StackSize = MFI->getStackSize();
1151 if (RegInfo->needsStackRealignment(MF)) {
1153 // Skip the saved EBP.
1154 return Offset + RegInfo->getSlotSize();
1156 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1157 return Offset + StackSize;
1159 // FIXME: Support tail calls
1162 return Offset + StackSize;
1164 // Skip the saved EBP.
1165 Offset += RegInfo->getSlotSize();
1167 // Skip the RETADDR move area
1168 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1169 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1170 if (TailCallReturnAddrDelta < 0)
1171 Offset -= TailCallReturnAddrDelta;
1177 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1178 unsigned &FrameReg) const {
1179 const X86RegisterInfo *RegInfo =
1180 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1181 // We can't calculate offset from frame pointer if the stack is realigned,
1182 // so enforce usage of stack pointer.
1183 FrameReg = (RegInfo->needsStackRealignment(MF)) ?
1184 RegInfo->getStackRegister() : RegInfo->getFrameRegister(MF);
1185 return getFrameIndexOffset(MF, FI);
1188 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1189 MachineBasicBlock::iterator MI,
1190 const std::vector<CalleeSavedInfo> &CSI,
1191 const TargetRegisterInfo *TRI) const {
1195 DebugLoc DL = MBB.findDebugLoc(MI);
1197 MachineFunction &MF = *MBB.getParent();
1199 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
1200 unsigned FPReg = TRI->getFrameRegister(MF);
1201 unsigned CalleeFrameSize = 0;
1203 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1204 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1206 // Push GPRs. It increases frame size.
1207 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1208 for (unsigned i = CSI.size(); i != 0; --i) {
1209 unsigned Reg = CSI[i-1].getReg();
1210 if (!X86::GR64RegClass.contains(Reg) &&
1211 !X86::GR32RegClass.contains(Reg))
1213 // Add the callee-saved register as live-in. It's killed at the spill.
1216 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
1218 CalleeFrameSize += SlotSize;
1219 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1220 .setMIFlag(MachineInstr::FrameSetup);
1223 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
1225 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1226 // It can be done by spilling XMMs to stack frame.
1227 // Note that only Win64 ABI might spill XMMs.
1228 for (unsigned i = CSI.size(); i != 0; --i) {
1229 unsigned Reg = CSI[i-1].getReg();
1230 if (X86::GR64RegClass.contains(Reg) ||
1231 X86::GR32RegClass.contains(Reg))
1233 // Add the callee-saved register as live-in. It's killed at the spill.
1235 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1236 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1243 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1244 MachineBasicBlock::iterator MI,
1245 const std::vector<CalleeSavedInfo> &CSI,
1246 const TargetRegisterInfo *TRI) const {
1250 DebugLoc DL = MBB.findDebugLoc(MI);
1252 MachineFunction &MF = *MBB.getParent();
1253 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1255 // Reload XMMs from stack frame.
1256 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1257 unsigned Reg = CSI[i].getReg();
1258 if (X86::GR64RegClass.contains(Reg) ||
1259 X86::GR32RegClass.contains(Reg))
1261 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1262 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1267 unsigned FPReg = TRI->getFrameRegister(MF);
1268 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1269 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1270 unsigned Reg = CSI[i].getReg();
1271 if (!X86::GR64RegClass.contains(Reg) &&
1272 !X86::GR32RegClass.contains(Reg))
1275 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
1277 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1283 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1284 RegScavenger *RS) const {
1285 MachineFrameInfo *MFI = MF.getFrameInfo();
1286 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
1287 unsigned SlotSize = RegInfo->getSlotSize();
1289 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1290 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1292 if (TailCallReturnAddrDelta < 0) {
1293 // create RETURNADDR area
1302 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1303 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
1307 assert((TailCallReturnAddrDelta <= 0) &&
1308 "The Delta should always be zero or negative");
1309 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
1311 // Create a frame entry for the EBP register that must be saved.
1312 int FrameIdx = MFI->CreateFixedObject(SlotSize,
1314 TFI.getOffsetOfLocalArea() +
1315 TailCallReturnAddrDelta,
1317 assert(FrameIdx == MFI->getObjectIndexBegin() &&
1318 "Slot for EBP register must be last in order to be found!");
1324 HasNestArgument(const MachineFunction *MF) {
1325 const Function *F = MF->getFunction();
1326 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1328 if (I->hasNestAttr())
1335 /// GetScratchRegister - Get a register for performing work in the segmented
1336 /// stack prologue. Depending on platform and the properties of the function
1337 /// either one or two registers will be needed. Set primary to true for
1338 /// the first register, false for the second.
1340 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1342 return Primary ? X86::R11 : X86::R12;
1344 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1345 bool IsNested = HasNestArgument(&MF);
1347 if (CallingConvention == CallingConv::X86_FastCall ||
1348 CallingConvention == CallingConv::Fast) {
1350 report_fatal_error("Segmented stacks does not support fastcall with "
1351 "nested function.");
1352 return Primary ? X86::EAX : X86::ECX;
1355 return Primary ? X86::EDX : X86::EAX;
1356 return Primary ? X86::ECX : X86::EAX;
1359 // The stack limit in the TCB is set to this many bytes above the actual stack
1361 static const uint64_t kSplitStackAvailable = 256;
1364 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1365 MachineBasicBlock &prologueMBB = MF.front();
1366 MachineFrameInfo *MFI = MF.getFrameInfo();
1367 const X86InstrInfo &TII = *TM.getInstrInfo();
1369 bool Is64Bit = STI.is64Bit();
1370 unsigned TlsReg, TlsOffset;
1372 const X86Subtarget *ST = &MF.getTarget().getSubtarget<X86Subtarget>();
1374 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1375 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1376 "Scratch register is live-in");
1378 if (MF.getFunction()->isVarArg())
1379 report_fatal_error("Segmented stacks do not support vararg functions.");
1380 if (!ST->isTargetLinux() && !ST->isTargetDarwin() &&
1381 !ST->isTargetWin32() && !ST->isTargetFreeBSD())
1382 report_fatal_error("Segmented stacks not supported on this platform.");
1384 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1385 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1386 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1387 bool IsNested = false;
1389 // We need to know if the function has a nest argument only in 64 bit mode.
1391 IsNested = HasNestArgument(&MF);
1393 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1394 // allocMBB needs to be last (terminating) instruction.
1396 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1397 e = prologueMBB.livein_end(); i != e; i++) {
1398 allocMBB->addLiveIn(*i);
1399 checkMBB->addLiveIn(*i);
1403 allocMBB->addLiveIn(X86::R10);
1405 MF.push_front(allocMBB);
1406 MF.push_front(checkMBB);
1408 // Eventually StackSize will be calculated by a link-time pass; which will
1409 // also decide whether checking code needs to be injected into this particular
1411 StackSize = MFI->getStackSize();
1413 // When the frame size is less than 256 we just compare the stack
1414 // boundary directly to the value of the stack pointer, per gcc.
1415 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1417 // Read the limit off the current stacklet off the stack_guard location.
1419 if (ST->isTargetLinux()) {
1422 } else if (ST->isTargetDarwin()) {
1424 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1425 } else if (ST->isTargetFreeBSD()) {
1429 report_fatal_error("Segmented stacks not supported on this platform.");
1432 if (CompareStackPointer)
1433 ScratchReg = X86::RSP;
1435 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1436 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1438 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1439 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1441 if (ST->isTargetLinux()) {
1444 } else if (ST->isTargetDarwin()) {
1446 TlsOffset = 0x48 + 90*4;
1447 } else if (ST->isTargetWin32()) {
1449 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1450 } else if (ST->isTargetFreeBSD()) {
1451 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1453 report_fatal_error("Segmented stacks not supported on this platform.");
1456 if (CompareStackPointer)
1457 ScratchReg = X86::ESP;
1459 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1460 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1462 if (ST->isTargetLinux() || ST->isTargetWin32()) {
1463 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1464 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1465 } else if (ST->isTargetDarwin()) {
1467 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
1468 unsigned ScratchReg2;
1470 if (CompareStackPointer) {
1471 // The primary scratch register is available for holding the TLS offset
1472 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1473 SaveScratch2 = false;
1475 // Need to use a second register to hold the TLS offset
1476 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1478 // Unfortunately, with fastcc the second scratch register may hold an arg
1479 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1482 // If Scratch2 is live-in then it needs to be saved
1483 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1484 "Scratch register is live-in and not saved");
1487 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1488 .addReg(ScratchReg2, RegState::Kill);
1490 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1492 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1494 .addReg(ScratchReg2).addImm(1).addReg(0)
1499 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1503 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1504 // It jumps to normal execution of the function body.
1505 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1507 // On 32 bit we first push the arguments size and then the frame size. On 64
1508 // bit, we pass the stack frame size in r10 and the argument size in r11.
1510 // Functions with nested arguments use R10, so it needs to be saved across
1511 // the call to _morestack
1514 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1516 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1518 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1519 .addImm(X86FI->getArgumentStackSize());
1520 MF.getRegInfo().setPhysRegUsed(X86::R10);
1521 MF.getRegInfo().setPhysRegUsed(X86::R11);
1523 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1524 .addImm(X86FI->getArgumentStackSize());
1525 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1529 // __morestack is in libgcc
1531 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1532 .addExternalSymbol("__morestack");
1534 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1535 .addExternalSymbol("__morestack");
1538 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1540 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1542 allocMBB->addSuccessor(&prologueMBB);
1544 checkMBB->addSuccessor(allocMBB);
1545 checkMBB->addSuccessor(&prologueMBB);