1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
35 // FIXME: completely move here.
36 extern cl::opt<bool> ForceStackAlign;
38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
39 return !MF.getFrameInfo()->hasVarSizedObjects();
42 /// hasFP - Return true if the specified function should have a dedicated frame
43 /// pointer register. This is true if the function has variable sized allocas
44 /// or if frame pointer elimination is disabled.
45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 const MachineModuleInfo &MMI = MF.getMMI();
48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
50 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
51 RegInfo->needsStackRealignment(MF) ||
52 MFI->hasVarSizedObjects() ||
53 MFI->isFrameAddressTaken() || MF.hasMSInlineAsm() ||
54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
55 MMI.callsUnwindInit() || MMI.callsEHReturn());
58 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
62 return X86::SUB64ri32;
70 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
74 return X86::ADD64ri32;
82 static unsigned getLEArOpcode(unsigned IsLP64) {
83 return IsLP64 ? X86::LEA64r : X86::LEA32r;
86 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
87 /// when it reaches the "return" instruction. We can then pop a stack object
88 /// to this register without worry about clobbering it.
89 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator &MBBI,
91 const TargetRegisterInfo &TRI,
93 const MachineFunction *MF = MBB.getParent();
94 const Function *F = MF->getFunction();
95 if (!F || MF->getMMI().callsEHReturn())
98 static const uint16_t CallerSavedRegs32Bit[] = {
99 X86::EAX, X86::EDX, X86::ECX, 0
102 static const uint16_t CallerSavedRegs64Bit[] = {
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
107 unsigned Opc = MBBI->getOpcode();
112 case X86::TCRETURNdi:
113 case X86::TCRETURNri:
114 case X86::TCRETURNmi:
115 case X86::TCRETURNdi64:
116 case X86::TCRETURNri64:
117 case X86::TCRETURNmi64:
119 case X86::EH_RETURN64: {
120 SmallSet<uint16_t, 8> Uses;
121 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
122 MachineOperand &MO = MBBI->getOperand(i);
123 if (!MO.isReg() || MO.isDef())
125 unsigned Reg = MO.getReg();
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
134 if (!Uses.count(*CS))
143 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
144 /// stack pointer by a constant value.
146 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
147 unsigned StackPtr, int64_t NumBytes,
148 bool Is64Bit, bool IsLP64, bool UseLEA,
149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
150 bool isSub = NumBytes < 0;
151 uint64_t Offset = isSub ? -NumBytes : NumBytes;
154 Opc = getLEArOpcode(IsLP64);
157 ? getSUBriOpcode(IsLP64, Offset)
158 : getADDriOpcode(IsLP64, Offset);
160 uint64_t Chunk = (1LL << 31) - 1;
161 DebugLoc DL = MBB.findDebugLoc(MBBI);
164 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
165 if (ThisVal == (Is64Bit ? 8 : 4)) {
166 // Use push / pop instead.
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
177 MI->setFlag(MachineInstr::FrameSetup);
183 MachineInstr *MI = NULL;
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
187 StackPtr, false, isSub ? -ThisVal : ThisVal);
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
192 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
196 MI->setFlag(MachineInstr::FrameSetup);
202 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
204 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
205 unsigned StackPtr, uint64_t *NumBytes = NULL) {
206 if (MBBI == MBB.begin()) return;
208 MachineBasicBlock::iterator PI = prior(MBBI);
209 unsigned Opc = PI->getOpcode();
210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
213 PI->getOperand(0).getReg() == StackPtr) {
215 *NumBytes += PI->getOperand(2).getImm();
217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
219 PI->getOperand(0).getReg() == StackPtr) {
221 *NumBytes -= PI->getOperand(2).getImm();
226 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
228 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator &MBBI,
230 unsigned StackPtr, uint64_t *NumBytes = NULL) {
231 // FIXME: THIS ISN'T RUN!!!
234 if (MBBI == MBB.end()) return;
236 MachineBasicBlock::iterator NI = llvm::next(MBBI);
237 if (NI == MBB.end()) return;
239 unsigned Opc = NI->getOpcode();
240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
242 NI->getOperand(0).getReg() == StackPtr) {
244 *NumBytes -= NI->getOperand(2).getImm();
247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
249 NI->getOperand(0).getReg() == StackPtr) {
251 *NumBytes += NI->getOperand(2).getImm();
257 /// mergeSPUpdates - Checks the instruction before/after the passed
258 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the
259 /// stack adjustment is returned as a positive value for ADD/LEA and a negative for
261 static int mergeSPUpdates(MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator &MBBI,
264 bool doMergeWithPrevious) {
265 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
266 (!doMergeWithPrevious && MBBI == MBB.end()))
269 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
270 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
271 unsigned Opc = PI->getOpcode();
274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
277 PI->getOperand(0).getReg() == StackPtr){
278 Offset += PI->getOperand(2).getImm();
280 if (!doMergeWithPrevious) MBBI = NI;
281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
283 PI->getOperand(0).getReg() == StackPtr) {
284 Offset -= PI->getOperand(2).getImm();
286 if (!doMergeWithPrevious) MBBI = NI;
292 static bool isEAXLiveIn(MachineFunction &MF) {
293 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
294 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL)
305 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
307 unsigned FramePtr) const {
308 MachineFrameInfo *MFI = MF.getFrameInfo();
309 MachineModuleInfo &MMI = MF.getMMI();
311 // Add callee saved registers to move list.
312 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
313 if (CSI.empty()) return;
315 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
316 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
317 bool HasFP = hasFP(MF);
319 // Calculate amount of bytes used for return address storing.
320 int stackGrowth = -RegInfo->getSlotSize();
322 // FIXME: This is dirty hack. The code itself is pretty mess right now.
323 // It should be rewritten from scratch and generalized sometimes.
325 // Determine maximum offset (minimum due to stack growth).
326 int64_t MaxOffset = 0;
327 for (std::vector<CalleeSavedInfo>::const_iterator
328 I = CSI.begin(), E = CSI.end(); I != E; ++I)
329 MaxOffset = std::min(MaxOffset,
330 MFI->getObjectOffset(I->getFrameIdx()));
332 // Calculate offsets.
333 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
334 for (std::vector<CalleeSavedInfo>::const_iterator
335 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
336 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
337 unsigned Reg = I->getReg();
338 Offset = MaxOffset - Offset + saveAreaOffset;
340 // Don't output a new machine move if we're re-saving the frame
341 // pointer. This happens when the PrologEpilogInserter has inserted an extra
342 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
343 // generates one when frame pointers are used. If we generate a "machine
344 // move" for this extra "PUSH", the linker will lose track of the fact that
345 // the frame pointer should have the value of the first "PUSH" when it's
348 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
349 // another bug. I.e., one where we generate a prolog like this:
357 // The immediate re-push of EBP is unnecessary. At the least, it's an
358 // optimization bug. EBP can be used as a scratch register in certain
359 // cases, but probably not when we have a frame pointer.
360 if (HasFP && FramePtr == Reg)
363 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
364 MachineLocation CSSrc(Reg);
365 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
369 /// getCompactUnwindRegNum - Get the compact unwind number for a given
370 /// register. The number corresponds to the enum lists in
371 /// compact_unwind_encoding.h.
372 static int getCompactUnwindRegNum(unsigned Reg, bool is64Bit) {
373 static const uint16_t CU32BitRegs[] = {
374 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
376 static const uint16_t CU64BitRegs[] = {
377 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
379 const uint16_t *CURegs = is64Bit ? CU64BitRegs : CU32BitRegs;
380 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
387 // Number of registers that can be saved in a compact unwind encoding.
388 #define CU_NUM_SAVED_REGS 6
390 /// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding
391 /// used with frameless stacks. It is passed the number of registers to be saved
392 /// and an array of the registers saved.
394 encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
395 unsigned RegCount, bool Is64Bit) {
396 // The saved registers are numbered from 1 to 6. In order to encode the order
397 // in which they were saved, we re-number them according to their place in the
398 // register order. The re-numbering is relative to the last re-numbered
399 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
408 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
409 int CUReg = getCompactUnwindRegNum(SavedRegs[i], Is64Bit);
410 if (CUReg == -1) return ~0U;
411 SavedRegs[i] = CUReg;
415 std::swap(SavedRegs[0], SavedRegs[5]);
416 std::swap(SavedRegs[1], SavedRegs[4]);
417 std::swap(SavedRegs[2], SavedRegs[3]);
419 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
420 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i) {
421 unsigned Countless = 0;
422 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
423 if (SavedRegs[j] < SavedRegs[i])
426 RenumRegs[i] = SavedRegs[i] - Countless - 1;
429 // Take the renumbered values and encode them into a 10-bit number.
430 uint32_t permutationEncoding = 0;
433 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
434 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
438 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
439 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
443 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
444 + 3 * RenumRegs[4] + RenumRegs[5];
447 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
451 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
454 permutationEncoding |= RenumRegs[5];
458 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
459 "Invalid compact register encoding!");
460 return permutationEncoding;
463 /// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a
464 /// compact encoding with a frame pointer.
466 encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
468 // Encode the registers in the order they were saved, 3-bits per register. The
469 // registers are numbered from 1 to CU_NUM_SAVED_REGS.
471 for (int I = CU_NUM_SAVED_REGS - 1, Idx = 0; I != -1; --I) {
472 unsigned Reg = SavedRegs[I];
473 if (Reg == 0) continue;
475 int CURegNum = getCompactUnwindRegNum(Reg, Is64Bit);
476 if (CURegNum == -1) return ~0U;
478 // Encode the 3-bit register number in order, skipping over 3-bits for each
480 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
483 assert((RegEnc & 0x3FFFF) == RegEnc && "Invalid compact register encoding!");
487 uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const {
488 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
489 unsigned FramePtr = RegInfo->getFrameRegister(MF);
490 unsigned StackPtr = RegInfo->getStackRegister();
492 bool Is64Bit = STI.is64Bit();
493 bool HasFP = hasFP(MF);
495 unsigned SavedRegs[CU_NUM_SAVED_REGS] = { 0, 0, 0, 0, 0, 0 };
496 unsigned SavedRegIdx = 0;
498 unsigned OffsetSize = (Is64Bit ? 8 : 4);
500 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
501 unsigned PushInstrSize = 1;
502 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
503 unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
504 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
506 unsigned StackDivide = (Is64Bit ? 8 : 4);
508 unsigned InstrOffset = 0;
509 unsigned StackAdjust = 0;
510 unsigned StackSize = 0;
512 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB.
513 bool ExpectEnd = false;
514 for (MachineBasicBlock::iterator
515 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) {
516 MachineInstr &MI = *MBBI;
517 unsigned Opc = MI.getOpcode();
518 if (Opc == X86::PROLOG_LABEL) continue;
519 if (!MI.getFlag(MachineInstr::FrameSetup)) break;
521 // We don't exect any more prolog instructions.
522 if (ExpectEnd) return CU::UNWIND_MODE_DWARF;
524 if (Opc == PushInstr) {
525 // If there are too many saved registers, we cannot use compact encoding.
526 if (SavedRegIdx >= CU_NUM_SAVED_REGS) return CU::UNWIND_MODE_DWARF;
528 SavedRegs[SavedRegIdx++] = MI.getOperand(0).getReg();
529 StackAdjust += OffsetSize;
530 InstrOffset += PushInstrSize;
531 } else if (Opc == MoveInstr) {
532 unsigned SrcReg = MI.getOperand(1).getReg();
533 unsigned DstReg = MI.getOperand(0).getReg();
535 if (DstReg != FramePtr || SrcReg != StackPtr)
536 return CU::UNWIND_MODE_DWARF;
539 memset(SavedRegs, 0, sizeof(SavedRegs));
541 InstrOffset += MoveInstrSize;
542 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
543 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
545 // We already have a stack size.
546 return CU::UNWIND_MODE_DWARF;
548 if (!MI.getOperand(0).isReg() ||
549 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() ||
550 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm())
551 // We need this to be a stack adjustment pointer. Something like:
553 // %RSP<def> = SUB64ri8 %RSP, 48
554 return CU::UNWIND_MODE_DWARF;
556 StackSize = MI.getOperand(2).getImm() / StackDivide;
557 SubtractInstrIdx += InstrOffset;
562 // Encode that we are using EBP/RBP as the frame pointer.
563 uint32_t CompactUnwindEncoding = 0;
564 StackAdjust /= StackDivide;
566 if ((StackAdjust & 0xFF) != StackAdjust)
567 // Offset was too big for compact encoding.
568 return CU::UNWIND_MODE_DWARF;
570 // Get the encoding of the saved registers when we have a frame pointer.
571 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
572 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
574 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
575 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
576 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
579 uint32_t TotalStackSize = StackAdjust + StackSize;
580 if ((TotalStackSize & 0xFF) == TotalStackSize) {
581 // Frameless stack with a small stack size.
582 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
584 // Encode the stack size.
585 CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16;
587 if ((StackAdjust & 0x7) != StackAdjust)
588 // The extra stack adjustments are too big for us to handle.
589 return CU::UNWIND_MODE_DWARF;
591 // Frameless stack with an offset too large for us to encode compactly.
592 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
594 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
596 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
598 // Encode any extra stack stack adjustments (done via push instructions).
599 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
602 // Encode the number of registers saved.
603 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
605 // Get the encoding of the saved registers when we don't have a frame
608 encodeCompactUnwindRegistersWithoutFrame(SavedRegs, SavedRegIdx,
610 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
612 // Encode the register encoding.
613 CompactUnwindEncoding |=
614 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
617 return CompactUnwindEncoding;
620 /// usesTheStack - This function checks if any of the users of EFLAGS
621 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
622 /// to use the stack, and if we don't adjust the stack we clobber the first
624 /// See X86InstrInfo::copyPhysReg.
625 static bool usesTheStack(MachineFunction &MF) {
626 MachineRegisterInfo &MRI = MF.getRegInfo();
628 for (MachineRegisterInfo::reg_iterator ri = MRI.reg_begin(X86::EFLAGS),
629 re = MRI.reg_end(); ri != re; ++ri)
636 /// emitPrologue - Push callee-saved registers onto the stack, which
637 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
638 /// space for local variables. Also emit labels used by the exception handler to
639 /// generate the exception handling frames.
640 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
641 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
642 MachineBasicBlock::iterator MBBI = MBB.begin();
643 MachineFrameInfo *MFI = MF.getFrameInfo();
644 const Function *Fn = MF.getFunction();
645 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
646 const X86InstrInfo &TII = *TM.getInstrInfo();
647 MachineModuleInfo &MMI = MF.getMMI();
648 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
649 bool needsFrameMoves = MMI.hasDebugInfo() ||
650 Fn->needsUnwindTableEntry();
651 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
652 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
653 bool HasFP = hasFP(MF);
654 bool Is64Bit = STI.is64Bit();
655 bool IsLP64 = STI.isTarget64BitLP64();
656 bool IsWin64 = STI.isTargetWin64();
657 bool UseLEA = STI.useLeaForSP();
658 unsigned StackAlign = getStackAlignment();
659 unsigned SlotSize = RegInfo->getSlotSize();
660 unsigned FramePtr = RegInfo->getFrameRegister(MF);
661 unsigned StackPtr = RegInfo->getStackRegister();
662 unsigned BasePtr = RegInfo->getBaseRegister();
665 // If we're forcing a stack realignment we can't rely on just the frame
666 // info, we need to know the ABI stack alignment as well in case we
667 // have a call out. Otherwise just make sure we have some alignment - we'll
668 // go with the minimum SlotSize.
669 if (ForceStackAlign) {
671 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
672 else if (MaxAlign < SlotSize)
676 // Add RETADDR move area to callee saved frame size.
677 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
678 if (TailCallReturnAddrDelta < 0)
679 X86FI->setCalleeSavedFrameSize(
680 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
682 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
683 // function, and use up to 128 bytes of stack space, don't have a frame
684 // pointer, calls, or dynamic alloca then we do not need to adjust the
685 // stack pointer (we fit in the Red Zone). We also check that we don't
686 // push and pop from the stack.
687 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
688 Attribute::NoRedZone) &&
689 !RegInfo->needsStackRealignment(MF) &&
690 !MFI->hasVarSizedObjects() && // No dynamic alloca.
691 !MFI->adjustsStack() && // No calls.
692 !IsWin64 && // Win64 has no Red Zone
693 !usesTheStack(MF) && // Don't push and pop.
694 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack
695 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
696 if (HasFP) MinSize += SlotSize;
697 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
698 MFI->setStackSize(StackSize);
701 // Insert stack pointer adjustment for later moving of return addr. Only
702 // applies to tail call optimized functions where the callee argument stack
703 // size is bigger than the callers.
704 if (TailCallReturnAddrDelta < 0) {
706 BuildMI(MBB, MBBI, DL,
707 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
710 .addImm(-TailCallReturnAddrDelta)
711 .setMIFlag(MachineInstr::FrameSetup);
712 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
715 // Mapping for machine moves:
717 // DST: VirtualFP AND
718 // SRC: VirtualFP => DW_CFA_def_cfa_offset
719 // ELSE => DW_CFA_def_cfa
721 // SRC: VirtualFP AND
722 // DST: Register => DW_CFA_def_cfa_register
725 // OFFSET < 0 => DW_CFA_offset_extended_sf
726 // REG < 64 => DW_CFA_offset + Reg
727 // ELSE => DW_CFA_offset_extended
729 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
730 uint64_t NumBytes = 0;
731 int stackGrowth = -SlotSize;
734 // Calculate required stack adjustment.
735 uint64_t FrameSize = StackSize - SlotSize;
736 if (RegInfo->needsStackRealignment(MF)) {
737 // Callee-saved registers are pushed on stack before the stack
739 FrameSize -= X86FI->getCalleeSavedFrameSize();
740 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
742 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
745 // Get the offset of the stack slot for the EBP register, which is
746 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
747 // Update the frame offset adjustment.
748 MFI->setOffsetAdjustment(-NumBytes);
750 // Save EBP/RBP into the appropriate stack slot.
751 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
752 .addReg(FramePtr, RegState::Kill)
753 .setMIFlag(MachineInstr::FrameSetup);
755 if (needsFrameMoves) {
756 // Mark the place where EBP/RBP was saved.
757 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
758 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
761 // Define the current CFA rule to use the provided offset.
763 MachineLocation SPDst(MachineLocation::VirtualFP);
764 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
765 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
767 MachineLocation SPDst(StackPtr);
768 MachineLocation SPSrc(StackPtr, stackGrowth);
769 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
772 // Change the rule for the FramePtr to be an "offset" rule.
773 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
774 MachineLocation FPSrc(FramePtr);
775 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
778 // Update EBP with the new base value.
779 BuildMI(MBB, MBBI, DL,
780 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
782 .setMIFlag(MachineInstr::FrameSetup);
784 if (needsFrameMoves) {
785 // Mark effective beginning of when frame pointer becomes valid.
786 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
787 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
790 // Define the current CFA to use the EBP/RBP register.
791 MachineLocation FPDst(FramePtr);
792 MachineLocation FPSrc(MachineLocation::VirtualFP);
793 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
796 // Mark the FramePtr as live-in in every block except the entry.
797 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
799 I->addLiveIn(FramePtr);
801 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
804 // Skip the callee-saved push instructions.
805 bool PushedRegs = false;
806 int StackOffset = 2 * stackGrowth;
808 while (MBBI != MBB.end() &&
809 (MBBI->getOpcode() == X86::PUSH32r ||
810 MBBI->getOpcode() == X86::PUSH64r)) {
812 MBBI->setFlag(MachineInstr::FrameSetup);
815 if (!HasFP && needsFrameMoves) {
816 // Mark callee-saved push instruction.
817 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
818 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
820 // Define the current CFA rule to use the provided offset.
821 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr;
822 MachineLocation SPDst(Ptr);
823 MachineLocation SPSrc(Ptr, StackOffset);
824 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
825 StackOffset += stackGrowth;
829 // Realign stack after we pushed callee-saved registers (so that we'll be
830 // able to calculate their offsets from the frame pointer).
832 // NOTE: We push the registers before realigning the stack, so
833 // vector callee-saved (xmm) registers may be saved w/o proper
834 // alignment in this way. However, currently these regs are saved in
835 // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so
836 // this shouldn't be a problem.
837 if (RegInfo->needsStackRealignment(MF)) {
838 assert(HasFP && "There should be a frame pointer if stack is realigned.");
840 BuildMI(MBB, MBBI, DL,
841 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
844 .setMIFlag(MachineInstr::FrameSetup);
846 // The EFLAGS implicit def is dead.
847 MI->getOperand(3).setIsDead();
850 // If there is an SUB32ri of ESP immediately before this instruction, merge
851 // the two. This can be the case when tail call elimination is enabled and
852 // the callee has more arguments then the caller.
853 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
855 // If there is an ADD32ri or SUB32ri of ESP immediately after this
856 // instruction, merge the two instructions.
857 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
859 // Adjust stack pointer: ESP -= numbytes.
861 // Windows and cygwin/mingw require a prologue helper routine when allocating
862 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
863 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
864 // stack and adjust the stack pointer in one go. The 64-bit version of
865 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
866 // responsible for adjusting the stack pointer. Touching the stack at 4K
867 // increments is necessary to ensure that the guard pages used by the OS
868 // virtual memory manager are allocated in correct sequence.
869 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) {
870 const char *StackProbeSymbol;
871 bool isSPUpdateNeeded = false;
874 if (STI.isTargetCygMing())
875 StackProbeSymbol = "___chkstk";
877 StackProbeSymbol = "__chkstk";
878 isSPUpdateNeeded = true;
880 } else if (STI.isTargetCygMing())
881 StackProbeSymbol = "_alloca";
883 StackProbeSymbol = "_chkstk";
885 // Check whether EAX is livein for this function.
886 bool isEAXAlive = isEAXLiveIn(MF);
889 // Sanity check that EAX is not livein for this function.
890 // It should not be, so throw an assert.
891 assert(!Is64Bit && "EAX is livein in x64 case!");
894 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
895 .addReg(X86::EAX, RegState::Kill)
896 .setMIFlag(MachineInstr::FrameSetup);
900 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
901 // Function prologue is responsible for adjusting the stack pointer.
902 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
904 .setMIFlag(MachineInstr::FrameSetup);
906 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
907 // We'll also use 4 already allocated bytes for EAX.
908 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
909 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
910 .setMIFlag(MachineInstr::FrameSetup);
913 BuildMI(MBB, MBBI, DL,
914 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
915 .addExternalSymbol(StackProbeSymbol)
916 .addReg(StackPtr, RegState::Define | RegState::Implicit)
917 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
918 .setMIFlag(MachineInstr::FrameSetup);
920 // MSVC x64's __chkstk needs to adjust %rsp.
921 // FIXME: %rax preserves the offset and should be available.
922 if (isSPUpdateNeeded)
923 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
924 UseLEA, TII, *RegInfo);
928 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
930 StackPtr, false, NumBytes - 4);
931 MI->setFlag(MachineInstr::FrameSetup);
932 MBB.insert(MBBI, MI);
935 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
936 UseLEA, TII, *RegInfo);
938 // If we need a base pointer, set it up here. It's whatever the value
939 // of the stack pointer is at this point. Any variable size objects
940 // will be allocated after this, so we can still use the base pointer
941 // to reference locals.
942 if (RegInfo->hasBasePointer(MF)) {
943 // Update the frame pointer with the current stack pointer.
944 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
945 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
947 .setMIFlag(MachineInstr::FrameSetup);
950 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
951 // Mark end of stack pointer adjustment.
952 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
953 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
956 if (!HasFP && NumBytes) {
957 // Define the current CFA rule to use the provided offset.
959 MachineLocation SPDst(MachineLocation::VirtualFP);
960 MachineLocation SPSrc(MachineLocation::VirtualFP,
961 -StackSize + stackGrowth);
962 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
964 MachineLocation SPDst(StackPtr);
965 MachineLocation SPSrc(StackPtr, stackGrowth);
966 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
970 // Emit DWARF info specifying the offsets of the callee-saved registers.
972 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
975 // Darwin 10.7 and greater has support for compact unwind encoding.
976 if (STI.getTargetTriple().isMacOSX() &&
977 !STI.getTargetTriple().isMacOSXVersionLT(10, 7))
978 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
981 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
982 MachineBasicBlock &MBB) const {
983 const MachineFrameInfo *MFI = MF.getFrameInfo();
984 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
985 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
986 const X86InstrInfo &TII = *TM.getInstrInfo();
987 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
988 assert(MBBI != MBB.end() && "Returning block has no instructions");
989 unsigned RetOpcode = MBBI->getOpcode();
990 DebugLoc DL = MBBI->getDebugLoc();
991 bool Is64Bit = STI.is64Bit();
992 bool IsLP64 = STI.isTarget64BitLP64();
993 bool UseLEA = STI.useLeaForSP();
994 unsigned StackAlign = getStackAlignment();
995 unsigned SlotSize = RegInfo->getSlotSize();
996 unsigned FramePtr = RegInfo->getFrameRegister(MF);
997 unsigned StackPtr = RegInfo->getStackRegister();
1001 llvm_unreachable("Can only insert epilog into returning blocks");
1004 case X86::TCRETURNdi:
1005 case X86::TCRETURNri:
1006 case X86::TCRETURNmi:
1007 case X86::TCRETURNdi64:
1008 case X86::TCRETURNri64:
1009 case X86::TCRETURNmi64:
1010 case X86::EH_RETURN:
1011 case X86::EH_RETURN64:
1012 break; // These are ok
1015 // Get the number of bytes to allocate from the FrameInfo.
1016 uint64_t StackSize = MFI->getStackSize();
1017 uint64_t MaxAlign = MFI->getMaxAlignment();
1018 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1019 uint64_t NumBytes = 0;
1021 // If we're forcing a stack realignment we can't rely on just the frame
1022 // info, we need to know the ABI stack alignment as well in case we
1023 // have a call out. Otherwise just make sure we have some alignment - we'll
1024 // go with the minimum.
1025 if (ForceStackAlign) {
1026 if (MFI->hasCalls())
1027 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1029 MaxAlign = MaxAlign ? MaxAlign : 4;
1033 // Calculate required stack adjustment.
1034 uint64_t FrameSize = StackSize - SlotSize;
1035 if (RegInfo->needsStackRealignment(MF)) {
1036 // Callee-saved registers were pushed on stack before the stack
1038 FrameSize -= CSSize;
1039 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
1041 NumBytes = FrameSize - CSSize;
1045 BuildMI(MBB, MBBI, DL,
1046 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1048 NumBytes = StackSize - CSSize;
1051 // Skip the callee-saved pop instructions.
1052 while (MBBI != MBB.begin()) {
1053 MachineBasicBlock::iterator PI = prior(MBBI);
1054 unsigned Opc = PI->getOpcode();
1056 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1057 !PI->isTerminator())
1062 MachineBasicBlock::iterator FirstCSPop = MBBI;
1064 DL = MBBI->getDebugLoc();
1066 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1067 // instruction, merge the two instructions.
1068 if (NumBytes || MFI->hasVarSizedObjects())
1069 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1071 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1072 // slot before popping them off! Same applies for the case, when stack was
1074 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1075 if (RegInfo->needsStackRealignment(MF))
1078 unsigned Opc = getLEArOpcode(IsLP64);
1079 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1080 FramePtr, false, -CSSize);
1082 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1083 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1086 } else if (NumBytes) {
1087 // Adjust stack pointer back: ESP += numbytes.
1088 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
1092 // We're returning from function via eh_return.
1093 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1094 MBBI = MBB.getLastNonDebugInstr();
1095 MachineOperand &DestAddr = MBBI->getOperand(0);
1096 assert(DestAddr.isReg() && "Offset should be in register!");
1097 BuildMI(MBB, MBBI, DL,
1098 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1099 StackPtr).addReg(DestAddr.getReg());
1100 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1101 RetOpcode == X86::TCRETURNmi ||
1102 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1103 RetOpcode == X86::TCRETURNmi64) {
1104 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1105 // Tail call return: adjust the stack pointer and jump to callee.
1106 MBBI = MBB.getLastNonDebugInstr();
1107 MachineOperand &JumpTarget = MBBI->getOperand(0);
1108 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1109 assert(StackAdjust.isImm() && "Expecting immediate value.");
1111 // Adjust stack pointer.
1112 int StackAdj = StackAdjust.getImm();
1113 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1115 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1117 // Incoporate the retaddr area.
1118 Offset = StackAdj-MaxTCDelta;
1119 assert(Offset >= 0 && "Offset should never be negative");
1122 // Check for possible merge with preceding ADD instruction.
1123 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1124 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
1125 UseLEA, TII, *RegInfo);
1128 // Jump to label or value in register.
1129 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1130 MachineInstrBuilder MIB =
1131 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1132 ? X86::TAILJMPd : X86::TAILJMPd64));
1133 if (JumpTarget.isGlobal())
1134 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1135 JumpTarget.getTargetFlags());
1137 assert(JumpTarget.isSymbol());
1138 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1139 JumpTarget.getTargetFlags());
1141 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1142 MachineInstrBuilder MIB =
1143 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1144 ? X86::TAILJMPm : X86::TAILJMPm64));
1145 for (unsigned i = 0; i != 5; ++i)
1146 MIB.addOperand(MBBI->getOperand(i));
1147 } else if (RetOpcode == X86::TCRETURNri64) {
1148 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1149 addReg(JumpTarget.getReg(), RegState::Kill);
1151 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1152 addReg(JumpTarget.getReg(), RegState::Kill);
1155 MachineInstr *NewMI = prior(MBBI);
1156 NewMI->copyImplicitOps(MF, MBBI);
1158 // Delete the pseudo instruction TCRETURN.
1160 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1161 (X86FI->getTCReturnAddrDelta() < 0)) {
1162 // Add the return addr area delta back since we are not tail calling.
1163 int delta = -1*X86FI->getTCReturnAddrDelta();
1164 MBBI = MBB.getLastNonDebugInstr();
1166 // Check for possible merge with preceding ADD instruction.
1167 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1168 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
1173 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
1174 const X86RegisterInfo *RegInfo =
1175 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1176 const MachineFrameInfo *MFI = MF.getFrameInfo();
1177 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1178 uint64_t StackSize = MFI->getStackSize();
1180 if (RegInfo->hasBasePointer(MF)) {
1181 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1183 // Skip the saved EBP.
1184 return Offset + RegInfo->getSlotSize();
1186 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1187 return Offset + StackSize;
1189 } else if (RegInfo->needsStackRealignment(MF)) {
1191 // Skip the saved EBP.
1192 return Offset + RegInfo->getSlotSize();
1194 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1195 return Offset + StackSize;
1197 // FIXME: Support tail calls
1200 return Offset + StackSize;
1202 // Skip the saved EBP.
1203 Offset += RegInfo->getSlotSize();
1205 // Skip the RETADDR move area
1206 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1207 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1208 if (TailCallReturnAddrDelta < 0)
1209 Offset -= TailCallReturnAddrDelta;
1215 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1216 unsigned &FrameReg) const {
1217 const X86RegisterInfo *RegInfo =
1218 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1219 // We can't calculate offset from frame pointer if the stack is realigned,
1220 // so enforce usage of stack/base pointer. The base pointer is used when we
1221 // have dynamic allocas in addition to dynamic realignment.
1222 if (RegInfo->hasBasePointer(MF))
1223 FrameReg = RegInfo->getBaseRegister();
1224 else if (RegInfo->needsStackRealignment(MF))
1225 FrameReg = RegInfo->getStackRegister();
1227 FrameReg = RegInfo->getFrameRegister(MF);
1228 return getFrameIndexOffset(MF, FI);
1231 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1232 MachineBasicBlock::iterator MI,
1233 const std::vector<CalleeSavedInfo> &CSI,
1234 const TargetRegisterInfo *TRI) const {
1238 DebugLoc DL = MBB.findDebugLoc(MI);
1240 MachineFunction &MF = *MBB.getParent();
1242 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
1243 unsigned FPReg = TRI->getFrameRegister(MF);
1244 unsigned CalleeFrameSize = 0;
1246 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1247 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1249 // Push GPRs. It increases frame size.
1250 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1251 for (unsigned i = CSI.size(); i != 0; --i) {
1252 unsigned Reg = CSI[i-1].getReg();
1253 if (!X86::GR64RegClass.contains(Reg) &&
1254 !X86::GR32RegClass.contains(Reg))
1256 // Add the callee-saved register as live-in. It's killed at the spill.
1259 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
1261 CalleeFrameSize += SlotSize;
1262 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1263 .setMIFlag(MachineInstr::FrameSetup);
1266 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
1268 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1269 // It can be done by spilling XMMs to stack frame.
1270 // Note that only Win64 ABI might spill XMMs.
1271 for (unsigned i = CSI.size(); i != 0; --i) {
1272 unsigned Reg = CSI[i-1].getReg();
1273 if (X86::GR64RegClass.contains(Reg) ||
1274 X86::GR32RegClass.contains(Reg))
1276 // Add the callee-saved register as live-in. It's killed at the spill.
1278 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1279 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1286 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1287 MachineBasicBlock::iterator MI,
1288 const std::vector<CalleeSavedInfo> &CSI,
1289 const TargetRegisterInfo *TRI) const {
1293 DebugLoc DL = MBB.findDebugLoc(MI);
1295 MachineFunction &MF = *MBB.getParent();
1296 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1298 // Reload XMMs from stack frame.
1299 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1300 unsigned Reg = CSI[i].getReg();
1301 if (X86::GR64RegClass.contains(Reg) ||
1302 X86::GR32RegClass.contains(Reg))
1304 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1305 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1310 unsigned FPReg = TRI->getFrameRegister(MF);
1311 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1312 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1313 unsigned Reg = CSI[i].getReg();
1314 if (!X86::GR64RegClass.contains(Reg) &&
1315 !X86::GR32RegClass.contains(Reg))
1318 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
1320 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1326 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1327 RegScavenger *RS) const {
1328 MachineFrameInfo *MFI = MF.getFrameInfo();
1329 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
1330 unsigned SlotSize = RegInfo->getSlotSize();
1332 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1333 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1335 if (TailCallReturnAddrDelta < 0) {
1336 // create RETURNADDR area
1345 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1346 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
1350 assert((TailCallReturnAddrDelta <= 0) &&
1351 "The Delta should always be zero or negative");
1352 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
1354 // Create a frame entry for the EBP register that must be saved.
1355 int FrameIdx = MFI->CreateFixedObject(SlotSize,
1357 TFI.getOffsetOfLocalArea() +
1358 TailCallReturnAddrDelta,
1360 assert(FrameIdx == MFI->getObjectIndexBegin() &&
1361 "Slot for EBP register must be last in order to be found!");
1365 // Spill the BasePtr if it's used.
1366 if (RegInfo->hasBasePointer(MF))
1367 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1371 HasNestArgument(const MachineFunction *MF) {
1372 const Function *F = MF->getFunction();
1373 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1375 if (I->hasNestAttr())
1381 /// GetScratchRegister - Get a temp register for performing work in the
1382 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1383 /// and the properties of the function either one or two registers will be
1384 /// needed. Set primary to true for the first register, false for the second.
1386 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1387 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1390 if (CallingConvention == CallingConv::HiPE) {
1392 return Primary ? X86::R14 : X86::R13;
1394 return Primary ? X86::EBX : X86::EDI;
1398 return Primary ? X86::R11 : X86::R12;
1400 bool IsNested = HasNestArgument(&MF);
1402 if (CallingConvention == CallingConv::X86_FastCall ||
1403 CallingConvention == CallingConv::Fast) {
1405 report_fatal_error("Segmented stacks does not support fastcall with "
1406 "nested function.");
1407 return Primary ? X86::EAX : X86::ECX;
1410 return Primary ? X86::EDX : X86::EAX;
1411 return Primary ? X86::ECX : X86::EAX;
1414 // The stack limit in the TCB is set to this many bytes above the actual stack
1416 static const uint64_t kSplitStackAvailable = 256;
1419 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1420 MachineBasicBlock &prologueMBB = MF.front();
1421 MachineFrameInfo *MFI = MF.getFrameInfo();
1422 const X86InstrInfo &TII = *TM.getInstrInfo();
1424 bool Is64Bit = STI.is64Bit();
1425 unsigned TlsReg, TlsOffset;
1428 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1429 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1430 "Scratch register is live-in");
1432 if (MF.getFunction()->isVarArg())
1433 report_fatal_error("Segmented stacks do not support vararg functions.");
1434 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1435 !STI.isTargetWin32() && !STI.isTargetFreeBSD())
1436 report_fatal_error("Segmented stacks not supported on this platform.");
1438 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1439 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1440 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1441 bool IsNested = false;
1443 // We need to know if the function has a nest argument only in 64 bit mode.
1445 IsNested = HasNestArgument(&MF);
1447 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1448 // allocMBB needs to be last (terminating) instruction.
1450 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1451 e = prologueMBB.livein_end(); i != e; i++) {
1452 allocMBB->addLiveIn(*i);
1453 checkMBB->addLiveIn(*i);
1457 allocMBB->addLiveIn(X86::R10);
1459 MF.push_front(allocMBB);
1460 MF.push_front(checkMBB);
1462 // Eventually StackSize will be calculated by a link-time pass; which will
1463 // also decide whether checking code needs to be injected into this particular
1465 StackSize = MFI->getStackSize();
1467 // When the frame size is less than 256 we just compare the stack
1468 // boundary directly to the value of the stack pointer, per gcc.
1469 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1471 // Read the limit off the current stacklet off the stack_guard location.
1473 if (STI.isTargetLinux()) {
1476 } else if (STI.isTargetDarwin()) {
1478 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1479 } else if (STI.isTargetFreeBSD()) {
1483 report_fatal_error("Segmented stacks not supported on this platform.");
1486 if (CompareStackPointer)
1487 ScratchReg = X86::RSP;
1489 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1490 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1492 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1493 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1495 if (STI.isTargetLinux()) {
1498 } else if (STI.isTargetDarwin()) {
1500 TlsOffset = 0x48 + 90*4;
1501 } else if (STI.isTargetWin32()) {
1503 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1504 } else if (STI.isTargetFreeBSD()) {
1505 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1507 report_fatal_error("Segmented stacks not supported on this platform.");
1510 if (CompareStackPointer)
1511 ScratchReg = X86::ESP;
1513 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1514 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1516 if (STI.isTargetLinux() || STI.isTargetWin32()) {
1517 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1518 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1519 } else if (STI.isTargetDarwin()) {
1521 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
1522 unsigned ScratchReg2;
1524 if (CompareStackPointer) {
1525 // The primary scratch register is available for holding the TLS offset
1526 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1527 SaveScratch2 = false;
1529 // Need to use a second register to hold the TLS offset
1530 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1532 // Unfortunately, with fastcc the second scratch register may hold an arg
1533 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1536 // If Scratch2 is live-in then it needs to be saved
1537 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1538 "Scratch register is live-in and not saved");
1541 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1542 .addReg(ScratchReg2, RegState::Kill);
1544 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1546 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1548 .addReg(ScratchReg2).addImm(1).addReg(0)
1553 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1557 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1558 // It jumps to normal execution of the function body.
1559 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1561 // On 32 bit we first push the arguments size and then the frame size. On 64
1562 // bit, we pass the stack frame size in r10 and the argument size in r11.
1564 // Functions with nested arguments use R10, so it needs to be saved across
1565 // the call to _morestack
1568 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1570 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1572 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1573 .addImm(X86FI->getArgumentStackSize());
1574 MF.getRegInfo().setPhysRegUsed(X86::R10);
1575 MF.getRegInfo().setPhysRegUsed(X86::R11);
1577 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1578 .addImm(X86FI->getArgumentStackSize());
1579 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1583 // __morestack is in libgcc
1585 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1586 .addExternalSymbol("__morestack");
1588 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1589 .addExternalSymbol("__morestack");
1592 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1594 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1596 allocMBB->addSuccessor(&prologueMBB);
1598 checkMBB->addSuccessor(allocMBB);
1599 checkMBB->addSuccessor(&prologueMBB);
1606 /// Erlang programs may need a special prologue to handle the stack size they
1607 /// might need at runtime. That is because Erlang/OTP does not implement a C
1608 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1609 /// (for more information see Eric Stenman's Ph.D. thesis:
1610 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1613 /// temp0 = sp - MaxStack
1614 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1618 /// call inc_stack # doubles the stack space
1619 /// temp0 = sp - MaxStack
1620 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1621 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1622 const X86InstrInfo &TII = *TM.getInstrInfo();
1623 MachineFrameInfo *MFI = MF.getFrameInfo();
1624 const unsigned SlotSize = TM.getRegisterInfo()->getSlotSize();
1625 const bool Is64Bit = STI.is64Bit();
1627 // HiPE-specific values
1628 const unsigned HipeLeafWords = 24;
1629 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1630 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1631 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1632 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1633 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1635 assert(STI.isTargetLinux() &&
1636 "HiPE prologue is only supported on Linux operating systems.");
1638 // Compute the largest caller's frame that is needed to fit the callees'
1639 // frames. This 'MaxStack' is computed from:
1641 // a) the fixed frame size, which is the space needed for all spilled temps,
1642 // b) outgoing on-stack parameter areas, and
1643 // c) the minimum stack space this function needs to make available for the
1644 // functions it calls (a tunable ABI property).
1645 if (MFI->hasCalls()) {
1646 unsigned MoreStackForCalls = 0;
1648 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1649 MBBI != MBBE; ++MBBI)
1650 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1655 // Get callee operand.
1656 const MachineOperand &MO = MI->getOperand(0);
1658 // Only take account of global function calls (no closures etc.).
1662 const Function *F = dyn_cast<Function>(MO.getGlobal());
1666 // Do not update 'MaxStack' for primitive and built-in functions
1667 // (encoded with names either starting with "erlang."/"bif_" or not
1668 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1669 // "_", such as the BIF "suspend_0") as they are executed on another
1671 if (F->getName().find("erlang.") != StringRef::npos ||
1672 F->getName().find("bif_") != StringRef::npos ||
1673 F->getName().find_first_of("._") == StringRef::npos)
1676 unsigned CalleeStkArity =
1677 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1678 if (HipeLeafWords - 1 > CalleeStkArity)
1679 MoreStackForCalls = std::max(MoreStackForCalls,
1680 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1682 MaxStack += MoreStackForCalls;
1685 // If the stack frame needed is larger than the guaranteed then runtime checks
1686 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1687 if (MaxStack > Guaranteed) {
1688 MachineBasicBlock &prologueMBB = MF.front();
1689 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1690 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1692 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1693 E = prologueMBB.livein_end(); I != E; I++) {
1694 stackCheckMBB->addLiveIn(*I);
1695 incStackMBB->addLiveIn(*I);
1698 MF.push_front(incStackMBB);
1699 MF.push_front(stackCheckMBB);
1701 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1702 unsigned LEAop, CMPop, CALLop;
1706 LEAop = X86::LEA64r;
1707 CMPop = X86::CMP64rm;
1708 CALLop = X86::CALL64pcrel32;
1709 SPLimitOffset = 0x90;
1713 LEAop = X86::LEA32r;
1714 CMPop = X86::CMP32rm;
1715 CALLop = X86::CALLpcrel32;
1716 SPLimitOffset = 0x4c;
1719 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1720 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1721 "HiPE prologue scratch register is live-in");
1723 // Create new MBB for StackCheck:
1724 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1725 SPReg, false, -MaxStack);
1726 // SPLimitOffset is in a fixed heap location (pointed by BP).
1727 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1728 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1729 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1731 // Create new MBB for IncStack:
1732 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1733 addExternalSymbol("inc_stack_0");
1734 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1735 SPReg, false, -MaxStack);
1736 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1737 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1738 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1740 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1741 stackCheckMBB->addSuccessor(incStackMBB, 1);
1742 incStackMBB->addSuccessor(&prologueMBB, 99);
1743 incStackMBB->addSuccessor(incStackMBB, 1);
1750 void X86FrameLowering::
1751 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1752 MachineBasicBlock::iterator I) const {
1753 const X86InstrInfo &TII = *TM.getInstrInfo();
1754 const X86RegisterInfo &RegInfo = *TM.getRegisterInfo();
1755 unsigned StackPtr = RegInfo.getStackRegister();
1756 bool reseveCallFrame = hasReservedCallFrame(MF);
1757 int Opcode = I->getOpcode();
1758 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1759 bool IsLP64 = STI.isTarget64BitLP64();
1760 DebugLoc DL = I->getDebugLoc();
1761 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
1762 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1765 if (!reseveCallFrame) {
1766 // If the stack pointer can be changed after prologue, turn the
1767 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1768 // adjcallstackdown instruction into 'add ESP, <amt>'
1769 // TODO: consider using push / pop instead of sub + store / add
1773 // We need to keep the stack aligned properly. To do this, we round the
1774 // amount of space needed for the outgoing arguments up to the next
1775 // alignment boundary.
1776 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1777 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1779 MachineInstr *New = 0;
1780 if (Opcode == TII.getCallFrameSetupOpcode()) {
1781 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1786 assert(Opcode == TII.getCallFrameDestroyOpcode());
1788 // Factor out the amount the callee already popped.
1789 Amount -= CalleeAmt;
1792 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1793 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1794 .addReg(StackPtr).addImm(Amount);
1799 // The EFLAGS implicit def is dead.
1800 New->getOperand(3).setIsDead();
1802 // Replace the pseudo instruction with a new instruction.
1809 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1810 // If we are performing frame pointer elimination and if the callee pops
1811 // something off the stack pointer, add it back. We do this until we have
1812 // more advanced stack pointer tracking ability.
1813 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1814 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1815 .addReg(StackPtr).addImm(CalleeAmt);
1817 // The EFLAGS implicit def is dead.
1818 New->getOperand(3).setIsDead();
1820 // We are not tracking the stack pointer adjustment by the callee, so make
1821 // sure we restore the stack pointer immediately after the call, there may
1822 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1823 MachineBasicBlock::iterator B = MBB.begin();
1824 while (I != B && !llvm::prior(I)->isCall())